1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
3 */
4
5 #include <stdint.h>
6 #include <ethdev_driver.h>
7 #include <rte_malloc.h>
8
9 #include "iavf.h"
10 #include "iavf_rxtx.h"
11 #include "iavf_rxtx_vec_common.h"
12
13 #include <tmmintrin.h>
14
15 #ifndef __INTEL_COMPILER
16 #pragma GCC diagnostic ignored "-Wcast-qual"
17 #endif
18
19 static inline void
iavf_rxq_rearm(struct iavf_rx_queue * rxq)20 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
21 {
22 int i;
23 uint16_t rx_id;
24
25 volatile union iavf_rx_desc *rxdp;
26 struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
27 struct rte_mbuf *mb0, *mb1;
28 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
29 RTE_PKTMBUF_HEADROOM);
30 __m128i dma_addr0, dma_addr1;
31
32 rxdp = rxq->rx_ring + rxq->rxrearm_start;
33
34 /* Pull 'n' more MBUFs into the software ring */
35 if (rte_mempool_get_bulk(rxq->mp, (void *)rxp,
36 rxq->rx_free_thresh) < 0) {
37 if (rxq->rxrearm_nb + rxq->rx_free_thresh >= rxq->nb_rx_desc) {
38 dma_addr0 = _mm_setzero_si128();
39 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
40 rxp[i] = &rxq->fake_mbuf;
41 _mm_store_si128((__m128i *)&rxdp[i].read,
42 dma_addr0);
43 }
44 }
45 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
46 rxq->rx_free_thresh;
47 return;
48 }
49
50 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
51 for (i = 0; i < rxq->rx_free_thresh; i += 2, rxp += 2) {
52 __m128i vaddr0, vaddr1;
53
54 mb0 = rxp[0];
55 mb1 = rxp[1];
56
57 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
58 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
59 offsetof(struct rte_mbuf, buf_addr) + 8);
60 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
61 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
62
63 /* convert pa to dma_addr hdr/data */
64 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
65 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
66
67 /* add headroom to pa values */
68 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
69 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
70
71 /* flush desc with pa dma_addr */
72 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
73 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
74 }
75
76 rxq->rxrearm_start += rxq->rx_free_thresh;
77 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
78 rxq->rxrearm_start = 0;
79
80 rxq->rxrearm_nb -= rxq->rx_free_thresh;
81
82 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
83 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
84
85 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
86 "rearm_start=%u rearm_nb=%u",
87 rxq->port_id, rxq->queue_id,
88 rx_id, rxq->rxrearm_start, rxq->rxrearm_nb);
89
90 /* Update the tail pointer on the NIC */
91 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
92 }
93
94 static inline void
desc_to_olflags_v(struct iavf_rx_queue * rxq,__m128i descs[4],struct rte_mbuf ** rx_pkts)95 desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
96 struct rte_mbuf **rx_pkts)
97 {
98 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
99 __m128i rearm0, rearm1, rearm2, rearm3;
100
101 __m128i vlan0, vlan1, rss, l3_l4e;
102
103 /* mask everything except RSS, flow director and VLAN flags
104 * bit2 is for VLAN tag, bit11 for flow director indication
105 * bit13:12 for RSS indication.
106 */
107 const __m128i rss_vlan_msk = _mm_set_epi32(
108 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
109
110 const __m128i cksum_mask = _mm_set_epi32(
111 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
112 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
113 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
114 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
115 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
116 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
117 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
118 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
119 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
120 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
121 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
122 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
123
124 /* map rss and vlan type to rss hash and vlan flag */
125 const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
126 0, 0, 0, 0,
127 0, 0, 0, RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
128 0, 0, 0, 0);
129
130 const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
131 0, 0, 0, 0,
132 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR, RTE_MBUF_F_RX_RSS_HASH, 0, 0,
133 0, 0, RTE_MBUF_F_RX_FDIR, 0);
134
135 const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
136 /* shift right 1 bit to make sure it not exceed 255 */
137 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
138 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
139 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
140 RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
141 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
142 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
143 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
144 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
145 RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
146 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1);
147
148 vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
149 vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
150 vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
151
152 vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
153 vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
154
155 rss = _mm_srli_epi32(vlan1, 11);
156 rss = _mm_shuffle_epi8(rss_flags, rss);
157
158 l3_l4e = _mm_srli_epi32(vlan1, 22);
159 l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
160 /* then we shift left 1 bit */
161 l3_l4e = _mm_slli_epi32(l3_l4e, 1);
162 /* we need to mask out the redundant bits */
163 l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
164
165 vlan0 = _mm_or_si128(vlan0, rss);
166 vlan0 = _mm_or_si128(vlan0, l3_l4e);
167
168 /* At this point, we have the 4 sets of flags in the low 16-bits
169 * of each 32-bit value in vlan0.
170 * We want to extract these, and merge them with the mbuf init data
171 * so we can do a single 16-byte write to the mbuf to set the flags
172 * and all the other initialization fields. Extracting the
173 * appropriate flags means that we have to do a shift and blend for
174 * each mbuf before we do the write.
175 */
176 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
177 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
178 rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
179 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
180
181 /* write the rearm data and the olflags in one write */
182 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
183 offsetof(struct rte_mbuf, rearm_data) + 8);
184 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
185 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
186 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
187 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
188 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
189 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
190 }
191
192 static inline __m128i
flex_rxd_to_fdir_flags_vec(const __m128i fdir_id0_3)193 flex_rxd_to_fdir_flags_vec(const __m128i fdir_id0_3)
194 {
195 #define FDID_MIS_MAGIC 0xFFFFFFFF
196 RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR != (1 << 2));
197 RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13));
198 const __m128i pkt_fdir_bit = _mm_set1_epi32(RTE_MBUF_F_RX_FDIR |
199 RTE_MBUF_F_RX_FDIR_ID);
200 /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
201 const __m128i fdir_mis_mask = _mm_set1_epi32(FDID_MIS_MAGIC);
202 __m128i fdir_mask = _mm_cmpeq_epi32(fdir_id0_3,
203 fdir_mis_mask);
204 /* this XOR op results to bit-reverse the fdir_mask */
205 fdir_mask = _mm_xor_si128(fdir_mask, fdir_mis_mask);
206 const __m128i fdir_flags = _mm_and_si128(fdir_mask, pkt_fdir_bit);
207
208 return fdir_flags;
209 }
210
211 static inline void
flex_desc_to_olflags_v(struct iavf_rx_queue * rxq,__m128i descs[4],struct rte_mbuf ** rx_pkts)212 flex_desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
213 struct rte_mbuf **rx_pkts)
214 {
215 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
216 __m128i rearm0, rearm1, rearm2, rearm3;
217
218 __m128i tmp_desc, flags, rss_vlan;
219
220 /* mask everything except checksum, RSS and VLAN flags.
221 * bit6:4 for checksum.
222 * bit12 for RSS indication.
223 * bit13 for VLAN indication.
224 */
225 const __m128i desc_mask = _mm_set_epi32(0x3070, 0x3070,
226 0x3070, 0x3070);
227
228 const __m128i cksum_mask = _mm_set_epi32(RTE_MBUF_F_RX_IP_CKSUM_MASK |
229 RTE_MBUF_F_RX_L4_CKSUM_MASK |
230 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
231 RTE_MBUF_F_RX_IP_CKSUM_MASK |
232 RTE_MBUF_F_RX_L4_CKSUM_MASK |
233 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
234 RTE_MBUF_F_RX_IP_CKSUM_MASK |
235 RTE_MBUF_F_RX_L4_CKSUM_MASK |
236 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
237 RTE_MBUF_F_RX_IP_CKSUM_MASK |
238 RTE_MBUF_F_RX_L4_CKSUM_MASK |
239 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
240
241 /* map the checksum, rss and vlan fields to the checksum, rss
242 * and vlan flag
243 */
244 const __m128i cksum_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
245 /* shift right 1 bit to make sure it not exceed 255 */
246 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
247 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
248 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
249 RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
250 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
251 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
252 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
253 RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
254 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
255 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
256 (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
257 (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1);
258
259 const __m128i rss_vlan_flags = _mm_set_epi8(0, 0, 0, 0,
260 0, 0, 0, 0,
261 0, 0, 0, 0,
262 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
263 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
264 RTE_MBUF_F_RX_RSS_HASH, 0);
265
266 /* merge 4 descriptors */
267 flags = _mm_unpackhi_epi32(descs[0], descs[1]);
268 tmp_desc = _mm_unpackhi_epi32(descs[2], descs[3]);
269 tmp_desc = _mm_unpacklo_epi64(flags, tmp_desc);
270 tmp_desc = _mm_and_si128(tmp_desc, desc_mask);
271
272 /* checksum flags */
273 tmp_desc = _mm_srli_epi32(tmp_desc, 4);
274 flags = _mm_shuffle_epi8(cksum_flags, tmp_desc);
275 /* then we shift left 1 bit */
276 flags = _mm_slli_epi32(flags, 1);
277 /* we need to mask out the redundant bits introduced by RSS or
278 * VLAN fields.
279 */
280 flags = _mm_and_si128(flags, cksum_mask);
281
282 /* RSS, VLAN flag */
283 tmp_desc = _mm_srli_epi32(tmp_desc, 8);
284 rss_vlan = _mm_shuffle_epi8(rss_vlan_flags, tmp_desc);
285
286 /* merge the flags */
287 flags = _mm_or_si128(flags, rss_vlan);
288
289 if (rxq->fdir_enabled) {
290 const __m128i fdir_id0_1 =
291 _mm_unpackhi_epi32(descs[0], descs[1]);
292
293 const __m128i fdir_id2_3 =
294 _mm_unpackhi_epi32(descs[2], descs[3]);
295
296 const __m128i fdir_id0_3 =
297 _mm_unpackhi_epi64(fdir_id0_1, fdir_id2_3);
298
299 const __m128i fdir_flags =
300 flex_rxd_to_fdir_flags_vec(fdir_id0_3);
301
302 /* merge with fdir_flags */
303 flags = _mm_or_si128(flags, fdir_flags);
304
305 /* write fdir_id to mbuf */
306 rx_pkts[0]->hash.fdir.hi =
307 _mm_extract_epi32(fdir_id0_3, 0);
308
309 rx_pkts[1]->hash.fdir.hi =
310 _mm_extract_epi32(fdir_id0_3, 1);
311
312 rx_pkts[2]->hash.fdir.hi =
313 _mm_extract_epi32(fdir_id0_3, 2);
314
315 rx_pkts[3]->hash.fdir.hi =
316 _mm_extract_epi32(fdir_id0_3, 3);
317 } /* if() on fdir_enabled */
318
319 /**
320 * At this point, we have the 4 sets of flags in the low 16-bits
321 * of each 32-bit value in flags.
322 * We want to extract these, and merge them with the mbuf init data
323 * so we can do a single 16-byte write to the mbuf to set the flags
324 * and all the other initialization fields. Extracting the
325 * appropriate flags means that we have to do a shift and blend for
326 * each mbuf before we do the write.
327 */
328 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 8), 0x10);
329 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 4), 0x10);
330 rearm2 = _mm_blend_epi16(mbuf_init, flags, 0x10);
331 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(flags, 4), 0x10);
332
333 /* write the rearm data and the olflags in one write */
334 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
335 offsetof(struct rte_mbuf, rearm_data) + 8);
336 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
337 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
338 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
339 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
340 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
341 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
342 }
343
344 #define PKTLEN_SHIFT 10
345
346 static inline void
desc_to_ptype_v(__m128i descs[4],struct rte_mbuf ** rx_pkts,const uint32_t * type_table)347 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
348 const uint32_t *type_table)
349 {
350 __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
351 __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
352
353 ptype0 = _mm_srli_epi64(ptype0, 30);
354 ptype1 = _mm_srli_epi64(ptype1, 30);
355
356 rx_pkts[0]->packet_type = type_table[_mm_extract_epi8(ptype0, 0)];
357 rx_pkts[1]->packet_type = type_table[_mm_extract_epi8(ptype0, 8)];
358 rx_pkts[2]->packet_type = type_table[_mm_extract_epi8(ptype1, 0)];
359 rx_pkts[3]->packet_type = type_table[_mm_extract_epi8(ptype1, 8)];
360 }
361
362 static inline void
flex_desc_to_ptype_v(__m128i descs[4],struct rte_mbuf ** rx_pkts,const uint32_t * type_table)363 flex_desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
364 const uint32_t *type_table)
365 {
366 const __m128i ptype_mask =
367 _mm_set_epi16(IAVF_RX_FLEX_DESC_PTYPE_M, 0x0,
368 IAVF_RX_FLEX_DESC_PTYPE_M, 0x0,
369 IAVF_RX_FLEX_DESC_PTYPE_M, 0x0,
370 IAVF_RX_FLEX_DESC_PTYPE_M, 0x0);
371
372 __m128i ptype_01 = _mm_unpacklo_epi32(descs[0], descs[1]);
373 __m128i ptype_23 = _mm_unpacklo_epi32(descs[2], descs[3]);
374 __m128i ptype_all = _mm_unpacklo_epi64(ptype_01, ptype_23);
375
376 ptype_all = _mm_and_si128(ptype_all, ptype_mask);
377
378 rx_pkts[0]->packet_type = type_table[_mm_extract_epi16(ptype_all, 1)];
379 rx_pkts[1]->packet_type = type_table[_mm_extract_epi16(ptype_all, 3)];
380 rx_pkts[2]->packet_type = type_table[_mm_extract_epi16(ptype_all, 5)];
381 rx_pkts[3]->packet_type = type_table[_mm_extract_epi16(ptype_all, 7)];
382 }
383
384 /**
385 * vPMD raw receive routine, only accept(nb_pkts >= IAVF_VPMD_DESCS_PER_LOOP)
386 *
387 * Notice:
388 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
389 * - floor align nb_pkts to a IAVF_VPMD_DESCS_PER_LOOP power-of-two
390 */
391 static inline uint16_t
_recv_raw_pkts_vec(struct iavf_rx_queue * rxq,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts,uint8_t * split_packet)392 _recv_raw_pkts_vec(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts,
393 uint16_t nb_pkts, uint8_t *split_packet)
394 {
395 volatile union iavf_rx_desc *rxdp;
396 struct rte_mbuf **sw_ring;
397 uint16_t nb_pkts_recd;
398 int pos;
399 uint64_t var;
400 __m128i shuf_msk;
401 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
402
403 __m128i crc_adjust = _mm_set_epi16(
404 0, 0, 0, /* ignore non-length fields */
405 -rxq->crc_len, /* sub crc on data_len */
406 0, /* ignore high-16bits of pkt_len */
407 -rxq->crc_len, /* sub crc on pkt_len */
408 0, 0 /* ignore pkt_type field */
409 );
410 /* compile-time check the above crc_adjust layout is correct.
411 * NOTE: the first field (lowest address) is given last in set_epi16
412 * call above.
413 */
414 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
415 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
416 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
417 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
418 __m128i dd_check, eop_check;
419
420 /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
421 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
422
423 /* Just the act of getting into the function from the application is
424 * going to cost about 7 cycles
425 */
426 rxdp = rxq->rx_ring + rxq->rx_tail;
427
428 rte_prefetch0(rxdp);
429
430 /* See if we need to rearm the RX queue - gives the prefetch a bit
431 * of time to act
432 */
433 if (rxq->rxrearm_nb > rxq->rx_free_thresh)
434 iavf_rxq_rearm(rxq);
435
436 /* Before we start moving massive data around, check to see if
437 * there is actually a packet available
438 */
439 if (!(rxdp->wb.qword1.status_error_len &
440 rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
441 return 0;
442
443 /* 4 packets DD mask */
444 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
445
446 /* 4 packets EOP mask */
447 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
448
449 /* mask to shuffle from desc. to mbuf */
450 shuf_msk = _mm_set_epi8(
451 7, 6, 5, 4, /* octet 4~7, 32bits rss */
452 3, 2, /* octet 2~3, low 16 bits vlan_macip */
453 15, 14, /* octet 15~14, 16 bits data_len */
454 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
455 15, 14, /* octet 15~14, low 16 bits pkt_len */
456 0xFF, 0xFF, 0xFF, 0xFF /* pkt_type set as unknown */
457 );
458 /* Compile-time verify the shuffle mask
459 * NOTE: some field positions already verified above, but duplicated
460 * here for completeness in case of future modifications.
461 */
462 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
463 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
464 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
465 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
466 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
467 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
468 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
469 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
470
471 /* Cache is empty -> need to scan the buffer rings, but first move
472 * the next 'n' mbufs into the cache
473 */
474 sw_ring = &rxq->sw_ring[rxq->rx_tail];
475
476 /* A. load 4 packet in one loop
477 * [A*. mask out 4 unused dirty field in desc]
478 * B. copy 4 mbuf point from swring to rx_pkts
479 * C. calc the number of DD bits among the 4 packets
480 * [C*. extract the end-of-packet bit, if requested]
481 * D. fill info. from desc to mbuf
482 */
483
484 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
485 pos += IAVF_VPMD_DESCS_PER_LOOP,
486 rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
487 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
488 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
489 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
490 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
491 __m128i mbp1;
492 #if defined(RTE_ARCH_X86_64)
493 __m128i mbp2;
494 #endif
495
496 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
497 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
498 /* Read desc statuses backwards to avoid race condition */
499 /* A.1 load desc[3] */
500 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
501 rte_compiler_barrier();
502
503 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
504 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
505
506 #if defined(RTE_ARCH_X86_64)
507 /* B.1 load 2 64 bit mbuf points */
508 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
509 #endif
510
511 /* A.1 load desc[2-0] */
512 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
513 rte_compiler_barrier();
514 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
515 rte_compiler_barrier();
516 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
517
518 #if defined(RTE_ARCH_X86_64)
519 /* B.2 copy 2 mbuf point into rx_pkts */
520 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
521 #endif
522
523 if (split_packet) {
524 rte_mbuf_prefetch_part2(rx_pkts[pos]);
525 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
526 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
527 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
528 }
529
530 /* avoid compiler reorder optimization */
531 rte_compiler_barrier();
532
533 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
534 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
535 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
536
537 /* merge the now-aligned packet length fields back in */
538 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
539 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
540
541 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
542 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
543 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
544
545 /* C.1 4=>2 status err info only */
546 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
547 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
548
549 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
550
551 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
552 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
553 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
554
555 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
556 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
557 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
558
559 /* merge the now-aligned packet length fields back in */
560 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
561 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
562
563 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
564 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
565 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
566
567 /* C.2 get 4 pkts status err value */
568 zero = _mm_xor_si128(dd_check, dd_check);
569 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
570
571 /* D.3 copy final 3,4 data to rx_pkts */
572 _mm_storeu_si128(
573 (void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
574 pkt_mb4);
575 _mm_storeu_si128(
576 (void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
577 pkt_mb3);
578
579 /* D.2 pkt 1,2 remove crc */
580 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
581 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
582
583 /* C* extract and record EOP bit */
584 if (split_packet) {
585 __m128i eop_shuf_mask = _mm_set_epi8(
586 0xFF, 0xFF, 0xFF, 0xFF,
587 0xFF, 0xFF, 0xFF, 0xFF,
588 0xFF, 0xFF, 0xFF, 0xFF,
589 0x04, 0x0C, 0x00, 0x08
590 );
591
592 /* and with mask to extract bits, flipping 1-0 */
593 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
594 /* the staterr values are not in order, as the count
595 * of dd bits doesn't care. However, for end of
596 * packet tracking, we do care, so shuffle. This also
597 * compresses the 32-bit values to 8-bit
598 */
599 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
600 /* store the resulting 32-bit value */
601 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
602 split_packet += IAVF_VPMD_DESCS_PER_LOOP;
603 }
604
605 /* C.3 calc available number of desc */
606 staterr = _mm_and_si128(staterr, dd_check);
607 staterr = _mm_packs_epi32(staterr, zero);
608
609 /* D.3 copy final 1,2 data to rx_pkts */
610 _mm_storeu_si128(
611 (void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
612 pkt_mb2);
613 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
614 pkt_mb1);
615 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
616 /* C.4 calc available number of desc */
617 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
618 nb_pkts_recd += var;
619 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
620 break;
621 }
622
623 /* Update our internal tail pointer */
624 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
625 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
626 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
627
628 return nb_pkts_recd;
629 }
630
631 /**
632 * vPMD raw receive routine for flex RxD,
633 * only accept(nb_pkts >= IAVF_VPMD_DESCS_PER_LOOP)
634 *
635 * Notice:
636 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
637 * - floor align nb_pkts to a IAVF_VPMD_DESCS_PER_LOOP power-of-two
638 */
639 static inline uint16_t
_recv_raw_pkts_vec_flex_rxd(struct iavf_rx_queue * rxq,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts,uint8_t * split_packet)640 _recv_raw_pkts_vec_flex_rxd(struct iavf_rx_queue *rxq,
641 struct rte_mbuf **rx_pkts,
642 uint16_t nb_pkts, uint8_t *split_packet)
643 {
644 volatile union iavf_rx_flex_desc *rxdp;
645 struct rte_mbuf **sw_ring;
646 uint16_t nb_pkts_recd;
647 int pos;
648 uint64_t var;
649 struct iavf_adapter *adapter = rxq->vsi->adapter;
650 uint64_t offloads = adapter->dev_data->dev_conf.rxmode.offloads;
651 const uint32_t *ptype_tbl = adapter->ptype_tbl;
652 __m128i crc_adjust = _mm_set_epi16
653 (0, 0, 0, /* ignore non-length fields */
654 -rxq->crc_len, /* sub crc on data_len */
655 0, /* ignore high-16bits of pkt_len */
656 -rxq->crc_len, /* sub crc on pkt_len */
657 0, 0 /* ignore pkt_type field */
658 );
659 const __m128i zero = _mm_setzero_si128();
660 /* mask to shuffle from desc. to mbuf */
661 const __m128i shuf_msk = _mm_set_epi8
662 (0xFF, 0xFF,
663 0xFF, 0xFF, /* rss hash parsed separately */
664 11, 10, /* octet 10~11, 16 bits vlan_macip */
665 5, 4, /* octet 4~5, 16 bits data_len */
666 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
667 5, 4, /* octet 4~5, low 16 bits pkt_len */
668 0xFF, 0xFF, /* pkt_type set as unknown */
669 0xFF, 0xFF /* pkt_type set as unknown */
670 );
671 const __m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,
672 0xFF, 0xFF,
673 0xFF, 0xFF,
674 0xFF, 0xFF,
675 0xFF, 0xFF,
676 0xFF, 0xFF,
677 0x04, 0x0C,
678 0x00, 0x08);
679
680 /**
681 * compile-time check the above crc_adjust layout is correct.
682 * NOTE: the first field (lowest address) is given last in set_epi16
683 * call above.
684 */
685 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
686 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
687 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
688 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
689
690 /* 4 packets DD mask */
691 const __m128i dd_check = _mm_set_epi64x(0x0000000100000001LL,
692 0x0000000100000001LL);
693 /* 4 packets EOP mask */
694 const __m128i eop_check = _mm_set_epi64x(0x0000000200000002LL,
695 0x0000000200000002LL);
696
697 /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
698 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
699
700 /* Just the act of getting into the function from the application is
701 * going to cost about 7 cycles
702 */
703 rxdp = (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
704
705 rte_prefetch0(rxdp);
706
707 /* See if we need to rearm the RX queue - gives the prefetch a bit
708 * of time to act
709 */
710 if (rxq->rxrearm_nb > rxq->rx_free_thresh)
711 iavf_rxq_rearm(rxq);
712
713 /* Before we start moving massive data around, check to see if
714 * there is actually a packet available
715 */
716 if (!(rxdp->wb.status_error0 &
717 rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
718 return 0;
719
720 /**
721 * Compile-time verify the shuffle mask
722 * NOTE: some field positions already verified above, but duplicated
723 * here for completeness in case of future modifications.
724 */
725 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
726 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
727 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
728 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
729 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
730 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
731 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
732 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
733
734 /* Cache is empty -> need to scan the buffer rings, but first move
735 * the next 'n' mbufs into the cache
736 */
737 sw_ring = &rxq->sw_ring[rxq->rx_tail];
738
739 /* A. load 4 packet in one loop
740 * [A*. mask out 4 unused dirty field in desc]
741 * B. copy 4 mbuf point from swring to rx_pkts
742 * C. calc the number of DD bits among the 4 packets
743 * [C*. extract the end-of-packet bit, if requested]
744 * D. fill info. from desc to mbuf
745 */
746
747 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
748 pos += IAVF_VPMD_DESCS_PER_LOOP,
749 rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
750 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
751 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
752 __m128i staterr, sterr_tmp1, sterr_tmp2;
753 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
754 __m128i mbp1;
755 #if defined(RTE_ARCH_X86_64)
756 __m128i mbp2;
757 #endif
758
759 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
760 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
761 /* Read desc statuses backwards to avoid race condition */
762 /* A.1 load desc[3] */
763 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
764 rte_compiler_barrier();
765
766 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
767 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
768
769 #if defined(RTE_ARCH_X86_64)
770 /* B.1 load 2 64 bit mbuf points */
771 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
772 #endif
773
774 /* A.1 load desc[2-0] */
775 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
776 rte_compiler_barrier();
777 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
778 rte_compiler_barrier();
779 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
780
781 #if defined(RTE_ARCH_X86_64)
782 /* B.2 copy 2 mbuf point into rx_pkts */
783 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
784 #endif
785
786 if (split_packet) {
787 rte_mbuf_prefetch_part2(rx_pkts[pos]);
788 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
789 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
790 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
791 }
792
793 /* avoid compiler reorder optimization */
794 rte_compiler_barrier();
795
796 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
797 pkt_mb3 = _mm_shuffle_epi8(descs[3], shuf_msk);
798 pkt_mb2 = _mm_shuffle_epi8(descs[2], shuf_msk);
799
800 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
801 pkt_mb1 = _mm_shuffle_epi8(descs[1], shuf_msk);
802 pkt_mb0 = _mm_shuffle_epi8(descs[0], shuf_msk);
803
804 /* C.1 4=>2 filter staterr info only */
805 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
806 /* C.1 4=>2 filter staterr info only */
807 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
808
809 flex_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
810
811 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
812 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
813 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
814
815 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
816 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
817 pkt_mb0 = _mm_add_epi16(pkt_mb0, crc_adjust);
818
819 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
820 /**
821 * needs to load 2nd 16B of each desc for RSS hash parsing,
822 * will cause performance drop to get into this context.
823 */
824 if (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH) {
825 /* load bottom half of every 32B desc */
826 const __m128i raw_desc_bh3 =
827 _mm_load_si128
828 ((void *)(&rxdp[3].wb.status_error1));
829 rte_compiler_barrier();
830 const __m128i raw_desc_bh2 =
831 _mm_load_si128
832 ((void *)(&rxdp[2].wb.status_error1));
833 rte_compiler_barrier();
834 const __m128i raw_desc_bh1 =
835 _mm_load_si128
836 ((void *)(&rxdp[1].wb.status_error1));
837 rte_compiler_barrier();
838 const __m128i raw_desc_bh0 =
839 _mm_load_si128
840 ((void *)(&rxdp[0].wb.status_error1));
841
842 /**
843 * to shift the 32b RSS hash value to the
844 * highest 32b of each 128b before mask
845 */
846 __m128i rss_hash3 =
847 _mm_slli_epi64(raw_desc_bh3, 32);
848 __m128i rss_hash2 =
849 _mm_slli_epi64(raw_desc_bh2, 32);
850 __m128i rss_hash1 =
851 _mm_slli_epi64(raw_desc_bh1, 32);
852 __m128i rss_hash0 =
853 _mm_slli_epi64(raw_desc_bh0, 32);
854
855 __m128i rss_hash_msk =
856 _mm_set_epi32(0xFFFFFFFF, 0, 0, 0);
857
858 rss_hash3 = _mm_and_si128
859 (rss_hash3, rss_hash_msk);
860 rss_hash2 = _mm_and_si128
861 (rss_hash2, rss_hash_msk);
862 rss_hash1 = _mm_and_si128
863 (rss_hash1, rss_hash_msk);
864 rss_hash0 = _mm_and_si128
865 (rss_hash0, rss_hash_msk);
866
867 pkt_mb3 = _mm_or_si128(pkt_mb3, rss_hash3);
868 pkt_mb2 = _mm_or_si128(pkt_mb2, rss_hash2);
869 pkt_mb1 = _mm_or_si128(pkt_mb1, rss_hash1);
870 pkt_mb0 = _mm_or_si128(pkt_mb0, rss_hash0);
871 } /* if() on RSS hash parsing */
872 #endif
873
874 /* C.2 get 4 pkts staterr value */
875 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
876
877 /* D.3 copy final 3,4 data to rx_pkts */
878 _mm_storeu_si128
879 ((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
880 pkt_mb3);
881 _mm_storeu_si128
882 ((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
883 pkt_mb2);
884
885 /* C* extract and record EOP bit */
886 if (split_packet) {
887 /* and with mask to extract bits, flipping 1-0 */
888 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
889 /* the staterr values are not in order, as the count
890 * of dd bits doesn't care. However, for end of
891 * packet tracking, we do care, so shuffle. This also
892 * compresses the 32-bit values to 8-bit
893 */
894 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
895 /* store the resulting 32-bit value */
896 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
897 split_packet += IAVF_VPMD_DESCS_PER_LOOP;
898 }
899
900 /* C.3 calc available number of desc */
901 staterr = _mm_and_si128(staterr, dd_check);
902 staterr = _mm_packs_epi32(staterr, zero);
903
904 /* D.3 copy final 1,2 data to rx_pkts */
905 _mm_storeu_si128
906 ((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
907 pkt_mb1);
908 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
909 pkt_mb0);
910 flex_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
911 /* C.4 calc available number of desc */
912 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
913 nb_pkts_recd += var;
914 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
915 break;
916 }
917
918 /* Update our internal tail pointer */
919 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
920 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
921 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
922
923 return nb_pkts_recd;
924 }
925
926 /* Notice:
927 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
928 * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
929 * numbers of DD bits
930 */
931 uint16_t
iavf_recv_pkts_vec(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)932 iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
933 uint16_t nb_pkts)
934 {
935 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
936 }
937
938 /* Notice:
939 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
940 * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
941 * numbers of DD bits
942 */
943 uint16_t
iavf_recv_pkts_vec_flex_rxd(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)944 iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
945 uint16_t nb_pkts)
946 {
947 return _recv_raw_pkts_vec_flex_rxd(rx_queue, rx_pkts, nb_pkts, NULL);
948 }
949
950 /**
951 * vPMD receive routine that reassembles single burst of 32 scattered packets
952 *
953 * Notice:
954 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
955 */
956 static uint16_t
iavf_recv_scattered_burst_vec(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)957 iavf_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
958 uint16_t nb_pkts)
959 {
960 struct iavf_rx_queue *rxq = rx_queue;
961 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
962 unsigned int i = 0;
963
964 /* get some new buffers */
965 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
966 split_flags);
967 if (nb_bufs == 0)
968 return 0;
969
970 /* happy day case, full burst + no packets to be joined */
971 const uint64_t *split_fl64 = (uint64_t *)split_flags;
972
973 if (!rxq->pkt_first_seg &&
974 split_fl64[0] == 0 && split_fl64[1] == 0 &&
975 split_fl64[2] == 0 && split_fl64[3] == 0)
976 return nb_bufs;
977
978 /* reassemble any packets that need reassembly*/
979 if (!rxq->pkt_first_seg) {
980 /* find the first split flag, and only reassemble then*/
981 while (i < nb_bufs && !split_flags[i])
982 i++;
983 if (i == nb_bufs)
984 return nb_bufs;
985 rxq->pkt_first_seg = rx_pkts[i];
986 }
987 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
988 &split_flags[i]);
989 }
990
991 /**
992 * vPMD receive routine that reassembles scattered packets.
993 */
994 uint16_t
iavf_recv_scattered_pkts_vec(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)995 iavf_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
996 uint16_t nb_pkts)
997 {
998 uint16_t retval = 0;
999
1000 while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1001 uint16_t burst;
1002
1003 burst = iavf_recv_scattered_burst_vec(rx_queue,
1004 rx_pkts + retval,
1005 IAVF_VPMD_RX_MAX_BURST);
1006 retval += burst;
1007 nb_pkts -= burst;
1008 if (burst < IAVF_VPMD_RX_MAX_BURST)
1009 return retval;
1010 }
1011
1012 return retval + iavf_recv_scattered_burst_vec(rx_queue,
1013 rx_pkts + retval,
1014 nb_pkts);
1015 }
1016
1017 /**
1018 * vPMD receive routine that reassembles single burst of 32 scattered packets
1019 * for flex RxD
1020 *
1021 * Notice:
1022 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
1023 */
1024 static uint16_t
iavf_recv_scattered_burst_vec_flex_rxd(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1025 iavf_recv_scattered_burst_vec_flex_rxd(void *rx_queue,
1026 struct rte_mbuf **rx_pkts,
1027 uint16_t nb_pkts)
1028 {
1029 struct iavf_rx_queue *rxq = rx_queue;
1030 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1031 unsigned int i = 0;
1032
1033 /* get some new buffers */
1034 uint16_t nb_bufs = _recv_raw_pkts_vec_flex_rxd(rxq, rx_pkts, nb_pkts,
1035 split_flags);
1036 if (nb_bufs == 0)
1037 return 0;
1038
1039 /* happy day case, full burst + no packets to be joined */
1040 const uint64_t *split_fl64 = (uint64_t *)split_flags;
1041
1042 if (!rxq->pkt_first_seg &&
1043 split_fl64[0] == 0 && split_fl64[1] == 0 &&
1044 split_fl64[2] == 0 && split_fl64[3] == 0)
1045 return nb_bufs;
1046
1047 /* reassemble any packets that need reassembly*/
1048 if (!rxq->pkt_first_seg) {
1049 /* find the first split flag, and only reassemble then*/
1050 while (i < nb_bufs && !split_flags[i])
1051 i++;
1052 if (i == nb_bufs)
1053 return nb_bufs;
1054 rxq->pkt_first_seg = rx_pkts[i];
1055 }
1056 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1057 &split_flags[i]);
1058 }
1059
1060 /**
1061 * vPMD receive routine that reassembles scattered packets for flex RxD
1062 */
1063 uint16_t
iavf_recv_scattered_pkts_vec_flex_rxd(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1064 iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
1065 struct rte_mbuf **rx_pkts,
1066 uint16_t nb_pkts)
1067 {
1068 uint16_t retval = 0;
1069
1070 while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1071 uint16_t burst;
1072
1073 burst = iavf_recv_scattered_burst_vec_flex_rxd(rx_queue,
1074 rx_pkts + retval,
1075 IAVF_VPMD_RX_MAX_BURST);
1076 retval += burst;
1077 nb_pkts -= burst;
1078 if (burst < IAVF_VPMD_RX_MAX_BURST)
1079 return retval;
1080 }
1081
1082 return retval + iavf_recv_scattered_burst_vec_flex_rxd(rx_queue,
1083 rx_pkts + retval,
1084 nb_pkts);
1085 }
1086
1087 static inline void
vtx1(volatile struct iavf_tx_desc * txdp,struct rte_mbuf * pkt,uint64_t flags)1088 vtx1(volatile struct iavf_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags)
1089 {
1090 uint64_t high_qw =
1091 (IAVF_TX_DESC_DTYPE_DATA |
1092 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) |
1093 ((uint64_t)pkt->data_len <<
1094 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1095
1096 __m128i descriptor = _mm_set_epi64x(high_qw,
1097 pkt->buf_iova + pkt->data_off);
1098 _mm_store_si128((__m128i *)txdp, descriptor);
1099 }
1100
1101 static inline void
iavf_vtx(volatile struct iavf_tx_desc * txdp,struct rte_mbuf ** pkt,uint16_t nb_pkts,uint64_t flags)1102 iavf_vtx(volatile struct iavf_tx_desc *txdp, struct rte_mbuf **pkt,
1103 uint16_t nb_pkts, uint64_t flags)
1104 {
1105 int i;
1106
1107 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
1108 vtx1(txdp, *pkt, flags);
1109 }
1110
1111 uint16_t
iavf_xmit_fixed_burst_vec(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1112 iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1113 uint16_t nb_pkts)
1114 {
1115 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1116 volatile struct iavf_tx_desc *txdp;
1117 struct iavf_tx_entry *txep;
1118 uint16_t n, nb_commit, tx_id;
1119 uint64_t flags = IAVF_TX_DESC_CMD_EOP | 0x04; /* bit 2 must be set */
1120 uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1121 int i;
1122
1123 if (txq->nb_free < txq->free_thresh)
1124 iavf_tx_free_bufs(txq);
1125
1126 nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1127 if (unlikely(nb_pkts == 0))
1128 return 0;
1129 nb_commit = nb_pkts;
1130
1131 tx_id = txq->tx_tail;
1132 txdp = &txq->tx_ring[tx_id];
1133 txep = &txq->sw_ring[tx_id];
1134
1135 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1136
1137 n = (uint16_t)(txq->nb_tx_desc - tx_id);
1138 if (nb_commit >= n) {
1139 tx_backlog_entry(txep, tx_pkts, n);
1140
1141 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
1142 vtx1(txdp, *tx_pkts, flags);
1143
1144 vtx1(txdp, *tx_pkts++, rs);
1145
1146 nb_commit = (uint16_t)(nb_commit - n);
1147
1148 tx_id = 0;
1149 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1150
1151 /* avoid reach the end of ring */
1152 txdp = &txq->tx_ring[tx_id];
1153 txep = &txq->sw_ring[tx_id];
1154 }
1155
1156 tx_backlog_entry(txep, tx_pkts, nb_commit);
1157
1158 iavf_vtx(txdp, tx_pkts, nb_commit, flags);
1159
1160 tx_id = (uint16_t)(tx_id + nb_commit);
1161 if (tx_id > txq->next_rs) {
1162 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1163 rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1164 IAVF_TXD_QW1_CMD_SHIFT);
1165 txq->next_rs =
1166 (uint16_t)(txq->next_rs + txq->rs_thresh);
1167 }
1168
1169 txq->tx_tail = tx_id;
1170
1171 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_pkts=%u",
1172 txq->port_id, txq->queue_id, tx_id, nb_pkts);
1173
1174 IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1175
1176 return nb_pkts;
1177 }
1178
1179 uint16_t
iavf_xmit_pkts_vec(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1180 iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1181 uint16_t nb_pkts)
1182 {
1183 uint16_t nb_tx = 0;
1184 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1185
1186 while (nb_pkts) {
1187 uint16_t ret, num;
1188
1189 /* cross rs_thresh boundary is not allowed */
1190 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1191 ret = iavf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
1192 nb_tx += ret;
1193 nb_pkts -= ret;
1194 if (ret < num)
1195 break;
1196 }
1197
1198 return nb_tx;
1199 }
1200
1201 static void __rte_cold
iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue * rxq)1202 iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq)
1203 {
1204 _iavf_rx_queue_release_mbufs_vec(rxq);
1205 }
1206
1207 static void __rte_cold
iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue * txq)1208 iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq)
1209 {
1210 _iavf_tx_queue_release_mbufs_vec(txq);
1211 }
1212
1213 static const struct iavf_rxq_ops sse_vec_rxq_ops = {
1214 .release_mbufs = iavf_rx_queue_release_mbufs_sse,
1215 };
1216
1217 static const struct iavf_txq_ops sse_vec_txq_ops = {
1218 .release_mbufs = iavf_tx_queue_release_mbufs_sse,
1219 };
1220
1221 int __rte_cold
iavf_txq_vec_setup(struct iavf_tx_queue * txq)1222 iavf_txq_vec_setup(struct iavf_tx_queue *txq)
1223 {
1224 txq->ops = &sse_vec_txq_ops;
1225 return 0;
1226 }
1227
1228 int __rte_cold
iavf_rxq_vec_setup(struct iavf_rx_queue * rxq)1229 iavf_rxq_vec_setup(struct iavf_rx_queue *rxq)
1230 {
1231 rxq->ops = &sse_vec_rxq_ops;
1232 return iavf_rxq_vec_setup_default(rxq);
1233 }
1234
1235 int __rte_cold
iavf_rx_vec_dev_check(struct rte_eth_dev * dev)1236 iavf_rx_vec_dev_check(struct rte_eth_dev *dev)
1237 {
1238 return iavf_rx_vec_dev_check_default(dev);
1239 }
1240
1241 int __rte_cold
iavf_tx_vec_dev_check(struct rte_eth_dev * dev)1242 iavf_tx_vec_dev_check(struct rte_eth_dev *dev)
1243 {
1244 return iavf_tx_vec_dev_check_default(dev);
1245 }
1246