1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
3 */
4
5 #include <stdio.h>
6 #include <stdlib.h>
7 #include <string.h>
8 #include <errno.h>
9 #include <stdint.h>
10 #include <stdarg.h>
11 #include <unistd.h>
12 #include <inttypes.h>
13 #include <sys/queue.h>
14
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
17 #include <rte_mbuf.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_tcp.h>
22 #include <rte_sctp.h>
23 #include <rte_udp.h>
24 #include <rte_ip.h>
25 #include <rte_net.h>
26 #include <rte_vect.h>
27
28 #include "i40e_logs.h"
29 #include "base/i40e_prototype.h"
30 #include "base/i40e_type.h"
31 #include "i40e_ethdev.h"
32 #include "i40e_rxtx.h"
33
34 #define DEFAULT_TX_RS_THRESH 32
35 #define DEFAULT_TX_FREE_THRESH 32
36
37 #define I40E_TX_MAX_BURST 32
38
39 #define I40E_DMA_MEM_ALIGN 4096
40
41 /* Base address of the HW descriptor ring should be 128B aligned. */
42 #define I40E_RING_BASE_ALIGN 128
43
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
45
46 #ifdef RTE_LIBRTE_IEEE1588
47 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
48 #else
49 #define I40E_TX_IEEE1588_TMST 0
50 #endif
51
52 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
53 PKT_TX_IP_CKSUM | \
54 PKT_TX_L4_MASK | \
55 PKT_TX_TCP_SEG | \
56 PKT_TX_OUTER_IP_CKSUM)
57
58 #define I40E_TX_OFFLOAD_MASK ( \
59 PKT_TX_OUTER_IPV4 | \
60 PKT_TX_OUTER_IPV6 | \
61 PKT_TX_IPV4 | \
62 PKT_TX_IPV6 | \
63 PKT_TX_IP_CKSUM | \
64 PKT_TX_L4_MASK | \
65 PKT_TX_OUTER_IP_CKSUM | \
66 PKT_TX_TCP_SEG | \
67 PKT_TX_QINQ_PKT | \
68 PKT_TX_VLAN_PKT | \
69 PKT_TX_TUNNEL_MASK | \
70 I40E_TX_IEEE1588_TMST)
71
72 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
73 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
74
75 static inline void
i40e_rxd_to_vlan_tci(struct rte_mbuf * mb,volatile union i40e_rx_desc * rxdp)76 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
77 {
78 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
79 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
80 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
81 mb->vlan_tci =
82 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
83 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
84 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
85 } else {
86 mb->vlan_tci = 0;
87 }
88 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
89 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
90 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
91 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
92 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
93 mb->vlan_tci_outer = mb->vlan_tci;
94 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
95 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
96 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
97 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
98 } else {
99 mb->vlan_tci_outer = 0;
100 }
101 #endif
102 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
103 mb->vlan_tci, mb->vlan_tci_outer);
104 }
105
106 /* Translate the rx descriptor status to pkt flags */
107 static inline uint64_t
i40e_rxd_status_to_pkt_flags(uint64_t qword)108 i40e_rxd_status_to_pkt_flags(uint64_t qword)
109 {
110 uint64_t flags;
111
112 /* Check if RSS_HASH */
113 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
114 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
115 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
116
117 /* Check if FDIR Match */
118 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
119 PKT_RX_FDIR : 0);
120
121 return flags;
122 }
123
124 static inline uint64_t
i40e_rxd_error_to_pkt_flags(uint64_t qword)125 i40e_rxd_error_to_pkt_flags(uint64_t qword)
126 {
127 uint64_t flags = 0;
128 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
129
130 #define I40E_RX_ERR_BITS 0x3f
131 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
132 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
133 return flags;
134 }
135
136 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
137 flags |= PKT_RX_IP_CKSUM_BAD;
138 else
139 flags |= PKT_RX_IP_CKSUM_GOOD;
140
141 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
142 flags |= PKT_RX_L4_CKSUM_BAD;
143 else
144 flags |= PKT_RX_L4_CKSUM_GOOD;
145
146 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
147 flags |= PKT_RX_EIP_CKSUM_BAD;
148
149 return flags;
150 }
151
152 /* Function to check and set the ieee1588 timesync index and get the
153 * appropriate flags.
154 */
155 #ifdef RTE_LIBRTE_IEEE1588
156 static inline uint64_t
i40e_get_iee15888_flags(struct rte_mbuf * mb,uint64_t qword)157 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
158 {
159 uint64_t pkt_flags = 0;
160 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
161 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
162 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
163
164 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
165 == RTE_PTYPE_L2_ETHER_TIMESYNC)
166 pkt_flags = PKT_RX_IEEE1588_PTP;
167 if (tsyn & 0x04) {
168 pkt_flags |= PKT_RX_IEEE1588_TMST;
169 mb->timesync = tsyn & 0x03;
170 }
171
172 return pkt_flags;
173 }
174 #endif
175
176 static inline uint64_t
i40e_rxd_build_fdir(volatile union i40e_rx_desc * rxdp,struct rte_mbuf * mb)177 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
178 {
179 uint64_t flags = 0;
180 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
181 uint16_t flexbh, flexbl;
182
183 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
184 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
185 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
186 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
187 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
188 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
189
190
191 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
192 mb->hash.fdir.hi =
193 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
194 flags |= PKT_RX_FDIR_ID;
195 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
196 mb->hash.fdir.hi =
197 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
198 flags |= PKT_RX_FDIR_FLX;
199 }
200 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
201 mb->hash.fdir.lo =
202 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
203 flags |= PKT_RX_FDIR_FLX;
204 }
205 #else
206 mb->hash.fdir.hi =
207 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
208 flags |= PKT_RX_FDIR_ID;
209 #endif
210 return flags;
211 }
212
213 static inline void
i40e_parse_tunneling_params(uint64_t ol_flags,union i40e_tx_offload tx_offload,uint32_t * cd_tunneling)214 i40e_parse_tunneling_params(uint64_t ol_flags,
215 union i40e_tx_offload tx_offload,
216 uint32_t *cd_tunneling)
217 {
218 /* EIPT: External (outer) IP header type */
219 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
220 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
221 else if (ol_flags & PKT_TX_OUTER_IPV4)
222 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
223 else if (ol_flags & PKT_TX_OUTER_IPV6)
224 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
225
226 /* EIPLEN: External (outer) IP header length, in DWords */
227 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
228 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
229
230 /* L4TUNT: L4 Tunneling Type */
231 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
232 case PKT_TX_TUNNEL_IPIP:
233 /* for non UDP / GRE tunneling, set to 00b */
234 break;
235 case PKT_TX_TUNNEL_VXLAN:
236 case PKT_TX_TUNNEL_GENEVE:
237 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
238 break;
239 case PKT_TX_TUNNEL_GRE:
240 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
241 break;
242 default:
243 PMD_TX_LOG(ERR, "Tunnel type not supported");
244 return;
245 }
246
247 /* L4TUNLEN: L4 Tunneling Length, in Words
248 *
249 * We depend on app to set rte_mbuf.l2_len correctly.
250 * For IP in GRE it should be set to the length of the GRE
251 * header;
252 * for MAC in GRE or MAC in UDP it should be set to the length
253 * of the GRE or UDP headers plus the inner MAC up to including
254 * its last Ethertype.
255 */
256 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
257 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
258 }
259
260 static inline void
i40e_txd_enable_checksum(uint64_t ol_flags,uint32_t * td_cmd,uint32_t * td_offset,union i40e_tx_offload tx_offload)261 i40e_txd_enable_checksum(uint64_t ol_flags,
262 uint32_t *td_cmd,
263 uint32_t *td_offset,
264 union i40e_tx_offload tx_offload)
265 {
266 /* Set MACLEN */
267 if (ol_flags & PKT_TX_TUNNEL_MASK)
268 *td_offset |= (tx_offload.outer_l2_len >> 1)
269 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
270 else
271 *td_offset |= (tx_offload.l2_len >> 1)
272 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
273
274 /* Enable L3 checksum offloads */
275 if (ol_flags & PKT_TX_IP_CKSUM) {
276 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
277 *td_offset |= (tx_offload.l3_len >> 2)
278 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
279 } else if (ol_flags & PKT_TX_IPV4) {
280 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
281 *td_offset |= (tx_offload.l3_len >> 2)
282 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
283 } else if (ol_flags & PKT_TX_IPV6) {
284 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
285 *td_offset |= (tx_offload.l3_len >> 2)
286 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
287 }
288
289 if (ol_flags & PKT_TX_TCP_SEG) {
290 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
291 *td_offset |= (tx_offload.l4_len >> 2)
292 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
293 return;
294 }
295
296 /* Enable L4 checksum offloads */
297 switch (ol_flags & PKT_TX_L4_MASK) {
298 case PKT_TX_TCP_CKSUM:
299 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
300 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
301 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
302 break;
303 case PKT_TX_SCTP_CKSUM:
304 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
305 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
306 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
307 break;
308 case PKT_TX_UDP_CKSUM:
309 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
310 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
311 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
312 break;
313 default:
314 break;
315 }
316 }
317
318 /* Construct the tx flags */
319 static inline uint64_t
i40e_build_ctob(uint32_t td_cmd,uint32_t td_offset,unsigned int size,uint32_t td_tag)320 i40e_build_ctob(uint32_t td_cmd,
321 uint32_t td_offset,
322 unsigned int size,
323 uint32_t td_tag)
324 {
325 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
326 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
327 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
328 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
329 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
330 }
331
332 static inline int
i40e_xmit_cleanup(struct i40e_tx_queue * txq)333 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
334 {
335 struct i40e_tx_entry *sw_ring = txq->sw_ring;
336 volatile struct i40e_tx_desc *txd = txq->tx_ring;
337 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
338 uint16_t nb_tx_desc = txq->nb_tx_desc;
339 uint16_t desc_to_clean_to;
340 uint16_t nb_tx_to_clean;
341
342 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
343 if (desc_to_clean_to >= nb_tx_desc)
344 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
345
346 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
347 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
348 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
349 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
350 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
351 "(port=%d queue=%d)", desc_to_clean_to,
352 txq->port_id, txq->queue_id);
353 return -1;
354 }
355
356 if (last_desc_cleaned > desc_to_clean_to)
357 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
358 desc_to_clean_to);
359 else
360 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
361 last_desc_cleaned);
362
363 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
364
365 txq->last_desc_cleaned = desc_to_clean_to;
366 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
367
368 return 0;
369 }
370
371 static inline int
372 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue * rxq)373 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
374 #else
375 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
376 #endif
377 {
378 int ret = 0;
379
380 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
381 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
382 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
383 "rxq->rx_free_thresh=%d, "
384 "RTE_PMD_I40E_RX_MAX_BURST=%d",
385 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
386 ret = -EINVAL;
387 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
388 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
389 "rxq->rx_free_thresh=%d, "
390 "rxq->nb_rx_desc=%d",
391 rxq->rx_free_thresh, rxq->nb_rx_desc);
392 ret = -EINVAL;
393 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
394 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
395 "rxq->nb_rx_desc=%d, "
396 "rxq->rx_free_thresh=%d",
397 rxq->nb_rx_desc, rxq->rx_free_thresh);
398 ret = -EINVAL;
399 }
400 #else
401 ret = -EINVAL;
402 #endif
403
404 return ret;
405 }
406
407 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
408 #define I40E_LOOK_AHEAD 8
409 #if (I40E_LOOK_AHEAD != 8)
410 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
411 #endif
412 static inline int
i40e_rx_scan_hw_ring(struct i40e_rx_queue * rxq)413 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
414 {
415 volatile union i40e_rx_desc *rxdp;
416 struct i40e_rx_entry *rxep;
417 struct rte_mbuf *mb;
418 uint16_t pkt_len;
419 uint64_t qword1;
420 uint32_t rx_status;
421 int32_t s[I40E_LOOK_AHEAD], nb_dd;
422 int32_t i, j, nb_rx = 0;
423 uint64_t pkt_flags;
424 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
425
426 rxdp = &rxq->rx_ring[rxq->rx_tail];
427 rxep = &rxq->sw_ring[rxq->rx_tail];
428
429 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
430 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
431 I40E_RXD_QW1_STATUS_SHIFT;
432
433 /* Make sure there is at least 1 packet to receive */
434 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
435 return 0;
436
437 /**
438 * Scan LOOK_AHEAD descriptors at a time to determine which
439 * descriptors reference packets that are ready to be received.
440 */
441 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
442 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
443 /* Read desc statuses backwards to avoid race condition */
444 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
445 qword1 = rte_le_to_cpu_64(\
446 rxdp[j].wb.qword1.status_error_len);
447 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
448 I40E_RXD_QW1_STATUS_SHIFT;
449 }
450
451 rte_smp_rmb();
452
453 /* Compute how many status bits were set */
454 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
455 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
456
457 nb_rx += nb_dd;
458
459 /* Translate descriptor info to mbuf parameters */
460 for (j = 0; j < nb_dd; j++) {
461 mb = rxep[j].mbuf;
462 qword1 = rte_le_to_cpu_64(\
463 rxdp[j].wb.qword1.status_error_len);
464 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
465 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
466 mb->data_len = pkt_len;
467 mb->pkt_len = pkt_len;
468 mb->ol_flags = 0;
469 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
470 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
471 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
472 mb->packet_type =
473 ptype_tbl[(uint8_t)((qword1 &
474 I40E_RXD_QW1_PTYPE_MASK) >>
475 I40E_RXD_QW1_PTYPE_SHIFT)];
476 if (pkt_flags & PKT_RX_RSS_HASH)
477 mb->hash.rss = rte_le_to_cpu_32(\
478 rxdp[j].wb.qword0.hi_dword.rss);
479 if (pkt_flags & PKT_RX_FDIR)
480 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
481
482 #ifdef RTE_LIBRTE_IEEE1588
483 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
484 #endif
485 mb->ol_flags |= pkt_flags;
486
487 }
488
489 for (j = 0; j < I40E_LOOK_AHEAD; j++)
490 rxq->rx_stage[i + j] = rxep[j].mbuf;
491
492 if (nb_dd != I40E_LOOK_AHEAD)
493 break;
494 }
495
496 /* Clear software ring entries */
497 for (i = 0; i < nb_rx; i++)
498 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
499
500 return nb_rx;
501 }
502
503 static inline uint16_t
i40e_rx_fill_from_stage(struct i40e_rx_queue * rxq,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)504 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
505 struct rte_mbuf **rx_pkts,
506 uint16_t nb_pkts)
507 {
508 uint16_t i;
509 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
510
511 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
512
513 for (i = 0; i < nb_pkts; i++)
514 rx_pkts[i] = stage[i];
515
516 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
517 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
518
519 return nb_pkts;
520 }
521
522 static inline int
i40e_rx_alloc_bufs(struct i40e_rx_queue * rxq)523 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
524 {
525 volatile union i40e_rx_desc *rxdp;
526 struct i40e_rx_entry *rxep;
527 struct rte_mbuf *mb;
528 uint16_t alloc_idx, i;
529 uint64_t dma_addr;
530 int diag;
531
532 /* Allocate buffers in bulk */
533 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
534 (rxq->rx_free_thresh - 1));
535 rxep = &(rxq->sw_ring[alloc_idx]);
536 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
537 rxq->rx_free_thresh);
538 if (unlikely(diag != 0)) {
539 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
540 return -ENOMEM;
541 }
542
543 rxdp = &rxq->rx_ring[alloc_idx];
544 for (i = 0; i < rxq->rx_free_thresh; i++) {
545 if (likely(i < (rxq->rx_free_thresh - 1)))
546 /* Prefetch next mbuf */
547 rte_prefetch0(rxep[i + 1].mbuf);
548
549 mb = rxep[i].mbuf;
550 rte_mbuf_refcnt_set(mb, 1);
551 mb->next = NULL;
552 mb->data_off = RTE_PKTMBUF_HEADROOM;
553 mb->nb_segs = 1;
554 mb->port = rxq->port_id;
555 dma_addr = rte_cpu_to_le_64(\
556 rte_mbuf_data_iova_default(mb));
557 rxdp[i].read.hdr_addr = 0;
558 rxdp[i].read.pkt_addr = dma_addr;
559 }
560
561 /* Update rx tail regsiter */
562 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
563
564 rxq->rx_free_trigger =
565 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
566 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
567 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
568
569 return 0;
570 }
571
572 static inline uint16_t
rx_recv_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)573 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
574 {
575 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
576 struct rte_eth_dev *dev;
577 uint16_t nb_rx = 0;
578
579 if (!nb_pkts)
580 return 0;
581
582 if (rxq->rx_nb_avail)
583 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
584
585 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
586 rxq->rx_next_avail = 0;
587 rxq->rx_nb_avail = nb_rx;
588 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
589
590 if (rxq->rx_tail > rxq->rx_free_trigger) {
591 if (i40e_rx_alloc_bufs(rxq) != 0) {
592 uint16_t i, j;
593
594 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
595 dev->data->rx_mbuf_alloc_failed +=
596 rxq->rx_free_thresh;
597
598 rxq->rx_nb_avail = 0;
599 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
600 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
601 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
602
603 return 0;
604 }
605 }
606
607 if (rxq->rx_tail >= rxq->nb_rx_desc)
608 rxq->rx_tail = 0;
609
610 if (rxq->rx_nb_avail)
611 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
612
613 return 0;
614 }
615
616 static uint16_t
i40e_recv_pkts_bulk_alloc(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)617 i40e_recv_pkts_bulk_alloc(void *rx_queue,
618 struct rte_mbuf **rx_pkts,
619 uint16_t nb_pkts)
620 {
621 uint16_t nb_rx = 0, n, count;
622
623 if (unlikely(nb_pkts == 0))
624 return 0;
625
626 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
627 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
628
629 while (nb_pkts) {
630 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
631 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
632 nb_rx = (uint16_t)(nb_rx + count);
633 nb_pkts = (uint16_t)(nb_pkts - count);
634 if (count < n)
635 break;
636 }
637
638 return nb_rx;
639 }
640 #else
641 static uint16_t
i40e_recv_pkts_bulk_alloc(void __rte_unused * rx_queue,struct rte_mbuf __rte_unused ** rx_pkts,uint16_t __rte_unused nb_pkts)642 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
643 struct rte_mbuf __rte_unused **rx_pkts,
644 uint16_t __rte_unused nb_pkts)
645 {
646 return 0;
647 }
648 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
649
650 uint16_t
i40e_recv_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)651 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
652 {
653 struct i40e_rx_queue *rxq;
654 volatile union i40e_rx_desc *rx_ring;
655 volatile union i40e_rx_desc *rxdp;
656 union i40e_rx_desc rxd;
657 struct i40e_rx_entry *sw_ring;
658 struct i40e_rx_entry *rxe;
659 struct rte_eth_dev *dev;
660 struct rte_mbuf *rxm;
661 struct rte_mbuf *nmb;
662 uint16_t nb_rx;
663 uint32_t rx_status;
664 uint64_t qword1;
665 uint16_t rx_packet_len;
666 uint16_t rx_id, nb_hold;
667 uint64_t dma_addr;
668 uint64_t pkt_flags;
669 uint32_t *ptype_tbl;
670
671 nb_rx = 0;
672 nb_hold = 0;
673 rxq = rx_queue;
674 rx_id = rxq->rx_tail;
675 rx_ring = rxq->rx_ring;
676 sw_ring = rxq->sw_ring;
677 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
678
679 while (nb_rx < nb_pkts) {
680 rxdp = &rx_ring[rx_id];
681 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
682 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
683 >> I40E_RXD_QW1_STATUS_SHIFT;
684
685 /* Check the DD bit first */
686 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
687 break;
688
689 nmb = rte_mbuf_raw_alloc(rxq->mp);
690 if (unlikely(!nmb)) {
691 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
692 dev->data->rx_mbuf_alloc_failed++;
693 break;
694 }
695
696 rxd = *rxdp;
697 nb_hold++;
698 rxe = &sw_ring[rx_id];
699 rx_id++;
700 if (unlikely(rx_id == rxq->nb_rx_desc))
701 rx_id = 0;
702
703 /* Prefetch next mbuf */
704 rte_prefetch0(sw_ring[rx_id].mbuf);
705
706 /**
707 * When next RX descriptor is on a cache line boundary,
708 * prefetch the next 4 RX descriptors and next 8 pointers
709 * to mbufs.
710 */
711 if ((rx_id & 0x3) == 0) {
712 rte_prefetch0(&rx_ring[rx_id]);
713 rte_prefetch0(&sw_ring[rx_id]);
714 }
715 rxm = rxe->mbuf;
716 rxe->mbuf = nmb;
717 dma_addr =
718 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
719 rxdp->read.hdr_addr = 0;
720 rxdp->read.pkt_addr = dma_addr;
721
722 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
723 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
724
725 rxm->data_off = RTE_PKTMBUF_HEADROOM;
726 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
727 rxm->nb_segs = 1;
728 rxm->next = NULL;
729 rxm->pkt_len = rx_packet_len;
730 rxm->data_len = rx_packet_len;
731 rxm->port = rxq->port_id;
732 rxm->ol_flags = 0;
733 i40e_rxd_to_vlan_tci(rxm, &rxd);
734 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
735 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
736 rxm->packet_type =
737 ptype_tbl[(uint8_t)((qword1 &
738 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
739 if (pkt_flags & PKT_RX_RSS_HASH)
740 rxm->hash.rss =
741 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
742 if (pkt_flags & PKT_RX_FDIR)
743 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
744
745 #ifdef RTE_LIBRTE_IEEE1588
746 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
747 #endif
748 rxm->ol_flags |= pkt_flags;
749
750 rx_pkts[nb_rx++] = rxm;
751 }
752 rxq->rx_tail = rx_id;
753
754 /**
755 * If the number of free RX descriptors is greater than the RX free
756 * threshold of the queue, advance the receive tail register of queue.
757 * Update that register with the value of the last processed RX
758 * descriptor minus 1.
759 */
760 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
761 if (nb_hold > rxq->rx_free_thresh) {
762 rx_id = (uint16_t) ((rx_id == 0) ?
763 (rxq->nb_rx_desc - 1) : (rx_id - 1));
764 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
765 nb_hold = 0;
766 }
767 rxq->nb_rx_hold = nb_hold;
768
769 return nb_rx;
770 }
771
772 uint16_t
i40e_recv_scattered_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)773 i40e_recv_scattered_pkts(void *rx_queue,
774 struct rte_mbuf **rx_pkts,
775 uint16_t nb_pkts)
776 {
777 struct i40e_rx_queue *rxq = rx_queue;
778 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
779 volatile union i40e_rx_desc *rxdp;
780 union i40e_rx_desc rxd;
781 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
782 struct i40e_rx_entry *rxe;
783 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
784 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
785 struct rte_mbuf *nmb, *rxm;
786 uint16_t rx_id = rxq->rx_tail;
787 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
788 struct rte_eth_dev *dev;
789 uint32_t rx_status;
790 uint64_t qword1;
791 uint64_t dma_addr;
792 uint64_t pkt_flags;
793 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
794
795 while (nb_rx < nb_pkts) {
796 rxdp = &rx_ring[rx_id];
797 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
798 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
799 I40E_RXD_QW1_STATUS_SHIFT;
800
801 /* Check the DD bit */
802 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
803 break;
804
805 nmb = rte_mbuf_raw_alloc(rxq->mp);
806 if (unlikely(!nmb)) {
807 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
808 dev->data->rx_mbuf_alloc_failed++;
809 break;
810 }
811
812 rxd = *rxdp;
813 nb_hold++;
814 rxe = &sw_ring[rx_id];
815 rx_id++;
816 if (rx_id == rxq->nb_rx_desc)
817 rx_id = 0;
818
819 /* Prefetch next mbuf */
820 rte_prefetch0(sw_ring[rx_id].mbuf);
821
822 /**
823 * When next RX descriptor is on a cache line boundary,
824 * prefetch the next 4 RX descriptors and next 8 pointers
825 * to mbufs.
826 */
827 if ((rx_id & 0x3) == 0) {
828 rte_prefetch0(&rx_ring[rx_id]);
829 rte_prefetch0(&sw_ring[rx_id]);
830 }
831
832 rxm = rxe->mbuf;
833 rxe->mbuf = nmb;
834 dma_addr =
835 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
836
837 /* Set data buffer address and data length of the mbuf */
838 rxdp->read.hdr_addr = 0;
839 rxdp->read.pkt_addr = dma_addr;
840 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
841 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
842 rxm->data_len = rx_packet_len;
843 rxm->data_off = RTE_PKTMBUF_HEADROOM;
844
845 /**
846 * If this is the first buffer of the received packet, set the
847 * pointer to the first mbuf of the packet and initialize its
848 * context. Otherwise, update the total length and the number
849 * of segments of the current scattered packet, and update the
850 * pointer to the last mbuf of the current packet.
851 */
852 if (!first_seg) {
853 first_seg = rxm;
854 first_seg->nb_segs = 1;
855 first_seg->pkt_len = rx_packet_len;
856 } else {
857 first_seg->pkt_len =
858 (uint16_t)(first_seg->pkt_len +
859 rx_packet_len);
860 first_seg->nb_segs++;
861 last_seg->next = rxm;
862 }
863
864 /**
865 * If this is not the last buffer of the received packet,
866 * update the pointer to the last mbuf of the current scattered
867 * packet and continue to parse the RX ring.
868 */
869 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
870 last_seg = rxm;
871 continue;
872 }
873
874 /**
875 * This is the last buffer of the received packet. If the CRC
876 * is not stripped by the hardware:
877 * - Subtract the CRC length from the total packet length.
878 * - If the last buffer only contains the whole CRC or a part
879 * of it, free the mbuf associated to the last buffer. If part
880 * of the CRC is also contained in the previous mbuf, subtract
881 * the length of that CRC part from the data length of the
882 * previous mbuf.
883 */
884 rxm->next = NULL;
885 if (unlikely(rxq->crc_len > 0)) {
886 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
887 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
888 rte_pktmbuf_free_seg(rxm);
889 first_seg->nb_segs--;
890 last_seg->data_len =
891 (uint16_t)(last_seg->data_len -
892 (RTE_ETHER_CRC_LEN - rx_packet_len));
893 last_seg->next = NULL;
894 } else
895 rxm->data_len = (uint16_t)(rx_packet_len -
896 RTE_ETHER_CRC_LEN);
897 }
898
899 first_seg->port = rxq->port_id;
900 first_seg->ol_flags = 0;
901 i40e_rxd_to_vlan_tci(first_seg, &rxd);
902 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
903 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
904 first_seg->packet_type =
905 ptype_tbl[(uint8_t)((qword1 &
906 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
907 if (pkt_flags & PKT_RX_RSS_HASH)
908 first_seg->hash.rss =
909 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
910 if (pkt_flags & PKT_RX_FDIR)
911 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
912
913 #ifdef RTE_LIBRTE_IEEE1588
914 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
915 #endif
916 first_seg->ol_flags |= pkt_flags;
917
918 /* Prefetch data of first segment, if configured to do so. */
919 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
920 first_seg->data_off));
921 rx_pkts[nb_rx++] = first_seg;
922 first_seg = NULL;
923 }
924
925 /* Record index of the next RX descriptor to probe. */
926 rxq->rx_tail = rx_id;
927 rxq->pkt_first_seg = first_seg;
928 rxq->pkt_last_seg = last_seg;
929
930 /**
931 * If the number of free RX descriptors is greater than the RX free
932 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
933 * register. Update the RDT with the value of the last processed RX
934 * descriptor minus 1, to guarantee that the RDT register is never
935 * equal to the RDH register, which creates a "full" ring situtation
936 * from the hardware point of view.
937 */
938 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
939 if (nb_hold > rxq->rx_free_thresh) {
940 rx_id = (uint16_t)(rx_id == 0 ?
941 (rxq->nb_rx_desc - 1) : (rx_id - 1));
942 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
943 nb_hold = 0;
944 }
945 rxq->nb_rx_hold = nb_hold;
946
947 return nb_rx;
948 }
949
950 /* Check if the context descriptor is needed for TX offloading */
951 static inline uint16_t
i40e_calc_context_desc(uint64_t flags)952 i40e_calc_context_desc(uint64_t flags)
953 {
954 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
955 PKT_TX_TCP_SEG |
956 PKT_TX_QINQ_PKT |
957 PKT_TX_TUNNEL_MASK;
958
959 #ifdef RTE_LIBRTE_IEEE1588
960 mask |= PKT_TX_IEEE1588_TMST;
961 #endif
962
963 return (flags & mask) ? 1 : 0;
964 }
965
966 /* set i40e TSO context descriptor */
967 static inline uint64_t
i40e_set_tso_ctx(struct rte_mbuf * mbuf,union i40e_tx_offload tx_offload)968 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
969 {
970 uint64_t ctx_desc = 0;
971 uint32_t cd_cmd, hdr_len, cd_tso_len;
972
973 if (!tx_offload.l4_len) {
974 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
975 return ctx_desc;
976 }
977
978 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
979 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
980 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
981
982 cd_cmd = I40E_TX_CTX_DESC_TSO;
983 cd_tso_len = mbuf->pkt_len - hdr_len;
984 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
985 ((uint64_t)cd_tso_len <<
986 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
987 ((uint64_t)mbuf->tso_segsz <<
988 I40E_TXD_CTX_QW1_MSS_SHIFT);
989
990 return ctx_desc;
991 }
992
993 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
994 #define I40E_MAX_DATA_PER_TXD \
995 (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
996 /* Calculate the number of TX descriptors needed for each pkt */
997 static inline uint16_t
i40e_calc_pkt_desc(struct rte_mbuf * tx_pkt)998 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
999 {
1000 struct rte_mbuf *txd = tx_pkt;
1001 uint16_t count = 0;
1002
1003 while (txd != NULL) {
1004 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1005 txd = txd->next;
1006 }
1007
1008 return count;
1009 }
1010
1011 uint16_t
i40e_xmit_pkts(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1012 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1013 {
1014 struct i40e_tx_queue *txq;
1015 struct i40e_tx_entry *sw_ring;
1016 struct i40e_tx_entry *txe, *txn;
1017 volatile struct i40e_tx_desc *txd;
1018 volatile struct i40e_tx_desc *txr;
1019 struct rte_mbuf *tx_pkt;
1020 struct rte_mbuf *m_seg;
1021 uint32_t cd_tunneling_params;
1022 uint16_t tx_id;
1023 uint16_t nb_tx;
1024 uint32_t td_cmd;
1025 uint32_t td_offset;
1026 uint32_t td_tag;
1027 uint64_t ol_flags;
1028 uint16_t nb_used;
1029 uint16_t nb_ctx;
1030 uint16_t tx_last;
1031 uint16_t slen;
1032 uint64_t buf_dma_addr;
1033 union i40e_tx_offload tx_offload = {0};
1034
1035 txq = tx_queue;
1036 sw_ring = txq->sw_ring;
1037 txr = txq->tx_ring;
1038 tx_id = txq->tx_tail;
1039 txe = &sw_ring[tx_id];
1040
1041 /* Check if the descriptor ring needs to be cleaned. */
1042 if (txq->nb_tx_free < txq->tx_free_thresh)
1043 (void)i40e_xmit_cleanup(txq);
1044
1045 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1046 td_cmd = 0;
1047 td_tag = 0;
1048 td_offset = 0;
1049
1050 tx_pkt = *tx_pkts++;
1051 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1052
1053 ol_flags = tx_pkt->ol_flags;
1054 tx_offload.l2_len = tx_pkt->l2_len;
1055 tx_offload.l3_len = tx_pkt->l3_len;
1056 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1057 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1058 tx_offload.l4_len = tx_pkt->l4_len;
1059 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1060
1061 /* Calculate the number of context descriptors needed. */
1062 nb_ctx = i40e_calc_context_desc(ol_flags);
1063
1064 /**
1065 * The number of descriptors that must be allocated for
1066 * a packet equals to the number of the segments of that
1067 * packet plus 1 context descriptor if needed.
1068 * Recalculate the needed tx descs when TSO enabled in case
1069 * the mbuf data size exceeds max data size that hw allows
1070 * per tx desc.
1071 */
1072 if (ol_flags & PKT_TX_TCP_SEG)
1073 nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1074 nb_ctx);
1075 else
1076 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1077 tx_last = (uint16_t)(tx_id + nb_used - 1);
1078
1079 /* Circular ring */
1080 if (tx_last >= txq->nb_tx_desc)
1081 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1082
1083 if (nb_used > txq->nb_tx_free) {
1084 if (i40e_xmit_cleanup(txq) != 0) {
1085 if (nb_tx == 0)
1086 return 0;
1087 goto end_of_tx;
1088 }
1089 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1090 while (nb_used > txq->nb_tx_free) {
1091 if (i40e_xmit_cleanup(txq) != 0) {
1092 if (nb_tx == 0)
1093 return 0;
1094 goto end_of_tx;
1095 }
1096 }
1097 }
1098 }
1099
1100 /* Descriptor based VLAN insertion */
1101 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1102 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1103 td_tag = tx_pkt->vlan_tci;
1104 }
1105
1106 /* Always enable CRC offload insertion */
1107 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1108
1109 /* Fill in tunneling parameters if necessary */
1110 cd_tunneling_params = 0;
1111 if (ol_flags & PKT_TX_TUNNEL_MASK)
1112 i40e_parse_tunneling_params(ol_flags, tx_offload,
1113 &cd_tunneling_params);
1114 /* Enable checksum offloading */
1115 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1116 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1117 &td_offset, tx_offload);
1118
1119 if (nb_ctx) {
1120 /* Setup TX context descriptor if required */
1121 volatile struct i40e_tx_context_desc *ctx_txd =
1122 (volatile struct i40e_tx_context_desc *)\
1123 &txr[tx_id];
1124 uint16_t cd_l2tag2 = 0;
1125 uint64_t cd_type_cmd_tso_mss =
1126 I40E_TX_DESC_DTYPE_CONTEXT;
1127
1128 txn = &sw_ring[txe->next_id];
1129 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1130 if (txe->mbuf != NULL) {
1131 rte_pktmbuf_free_seg(txe->mbuf);
1132 txe->mbuf = NULL;
1133 }
1134
1135 /* TSO enabled means no timestamp */
1136 if (ol_flags & PKT_TX_TCP_SEG)
1137 cd_type_cmd_tso_mss |=
1138 i40e_set_tso_ctx(tx_pkt, tx_offload);
1139 else {
1140 #ifdef RTE_LIBRTE_IEEE1588
1141 if (ol_flags & PKT_TX_IEEE1588_TMST)
1142 cd_type_cmd_tso_mss |=
1143 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1144 I40E_TXD_CTX_QW1_CMD_SHIFT);
1145 #endif
1146 }
1147
1148 ctx_txd->tunneling_params =
1149 rte_cpu_to_le_32(cd_tunneling_params);
1150 if (ol_flags & PKT_TX_QINQ_PKT) {
1151 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1152 cd_type_cmd_tso_mss |=
1153 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1154 I40E_TXD_CTX_QW1_CMD_SHIFT);
1155 }
1156 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1157 ctx_txd->type_cmd_tso_mss =
1158 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1159
1160 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1161 "tunneling_params: %#x;\n"
1162 "l2tag2: %#hx;\n"
1163 "rsvd: %#hx;\n"
1164 "type_cmd_tso_mss: %#"PRIx64";\n",
1165 tx_pkt, tx_id,
1166 ctx_txd->tunneling_params,
1167 ctx_txd->l2tag2,
1168 ctx_txd->rsvd,
1169 ctx_txd->type_cmd_tso_mss);
1170
1171 txe->last_id = tx_last;
1172 tx_id = txe->next_id;
1173 txe = txn;
1174 }
1175
1176 m_seg = tx_pkt;
1177 do {
1178 txd = &txr[tx_id];
1179 txn = &sw_ring[txe->next_id];
1180
1181 if (txe->mbuf)
1182 rte_pktmbuf_free_seg(txe->mbuf);
1183 txe->mbuf = m_seg;
1184
1185 /* Setup TX Descriptor */
1186 slen = m_seg->data_len;
1187 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1188
1189 while ((ol_flags & PKT_TX_TCP_SEG) &&
1190 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1191 txd->buffer_addr =
1192 rte_cpu_to_le_64(buf_dma_addr);
1193 txd->cmd_type_offset_bsz =
1194 i40e_build_ctob(td_cmd,
1195 td_offset, I40E_MAX_DATA_PER_TXD,
1196 td_tag);
1197
1198 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1199 slen -= I40E_MAX_DATA_PER_TXD;
1200
1201 txe->last_id = tx_last;
1202 tx_id = txe->next_id;
1203 txe = txn;
1204 txd = &txr[tx_id];
1205 txn = &sw_ring[txe->next_id];
1206 }
1207 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1208 "buf_dma_addr: %#"PRIx64";\n"
1209 "td_cmd: %#x;\n"
1210 "td_offset: %#x;\n"
1211 "td_len: %u;\n"
1212 "td_tag: %#x;\n",
1213 tx_pkt, tx_id, buf_dma_addr,
1214 td_cmd, td_offset, slen, td_tag);
1215
1216 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1217 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1218 td_offset, slen, td_tag);
1219 txe->last_id = tx_last;
1220 tx_id = txe->next_id;
1221 txe = txn;
1222 m_seg = m_seg->next;
1223 } while (m_seg != NULL);
1224
1225 /* The last packet data descriptor needs End Of Packet (EOP) */
1226 td_cmd |= I40E_TX_DESC_CMD_EOP;
1227 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1228 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1229
1230 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1231 PMD_TX_FREE_LOG(DEBUG,
1232 "Setting RS bit on TXD id="
1233 "%4u (port=%d queue=%d)",
1234 tx_last, txq->port_id, txq->queue_id);
1235
1236 td_cmd |= I40E_TX_DESC_CMD_RS;
1237
1238 /* Update txq RS bit counters */
1239 txq->nb_tx_used = 0;
1240 }
1241
1242 txd->cmd_type_offset_bsz |=
1243 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1244 I40E_TXD_QW1_CMD_SHIFT);
1245 }
1246
1247 end_of_tx:
1248 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1249 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1250 (unsigned) tx_id, (unsigned) nb_tx);
1251
1252 rte_io_wmb();
1253 I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1254 txq->tx_tail = tx_id;
1255
1256 return nb_tx;
1257 }
1258
1259 static __rte_always_inline int
i40e_tx_free_bufs(struct i40e_tx_queue * txq)1260 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1261 {
1262 struct i40e_tx_entry *txep;
1263 uint16_t i;
1264
1265 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1266 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1267 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1268 return 0;
1269
1270 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1271
1272 for (i = 0; i < txq->tx_rs_thresh; i++)
1273 rte_prefetch0((txep + i)->mbuf);
1274
1275 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1276 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1277 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1278 txep->mbuf = NULL;
1279 }
1280 } else {
1281 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1282 rte_pktmbuf_free_seg(txep->mbuf);
1283 txep->mbuf = NULL;
1284 }
1285 }
1286
1287 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1288 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1289 if (txq->tx_next_dd >= txq->nb_tx_desc)
1290 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1291
1292 return txq->tx_rs_thresh;
1293 }
1294
1295 /* Populate 4 descriptors with data from 4 mbufs */
1296 static inline void
tx4(volatile struct i40e_tx_desc * txdp,struct rte_mbuf ** pkts)1297 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1298 {
1299 uint64_t dma_addr;
1300 uint32_t i;
1301
1302 for (i = 0; i < 4; i++, txdp++, pkts++) {
1303 dma_addr = rte_mbuf_data_iova(*pkts);
1304 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1305 txdp->cmd_type_offset_bsz =
1306 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1307 (*pkts)->data_len, 0);
1308 }
1309 }
1310
1311 /* Populate 1 descriptor with data from 1 mbuf */
1312 static inline void
tx1(volatile struct i40e_tx_desc * txdp,struct rte_mbuf ** pkts)1313 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1314 {
1315 uint64_t dma_addr;
1316
1317 dma_addr = rte_mbuf_data_iova(*pkts);
1318 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1319 txdp->cmd_type_offset_bsz =
1320 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1321 (*pkts)->data_len, 0);
1322 }
1323
1324 /* Fill hardware descriptor ring with mbuf data */
1325 static inline void
i40e_tx_fill_hw_ring(struct i40e_tx_queue * txq,struct rte_mbuf ** pkts,uint16_t nb_pkts)1326 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1327 struct rte_mbuf **pkts,
1328 uint16_t nb_pkts)
1329 {
1330 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1331 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1332 const int N_PER_LOOP = 4;
1333 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1334 int mainpart, leftover;
1335 int i, j;
1336
1337 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1338 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1339 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1340 for (j = 0; j < N_PER_LOOP; ++j) {
1341 (txep + i + j)->mbuf = *(pkts + i + j);
1342 }
1343 tx4(txdp + i, pkts + i);
1344 }
1345 if (unlikely(leftover > 0)) {
1346 for (i = 0; i < leftover; ++i) {
1347 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1348 tx1(txdp + mainpart + i, pkts + mainpart + i);
1349 }
1350 }
1351 }
1352
1353 static inline uint16_t
tx_xmit_pkts(struct i40e_tx_queue * txq,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1354 tx_xmit_pkts(struct i40e_tx_queue *txq,
1355 struct rte_mbuf **tx_pkts,
1356 uint16_t nb_pkts)
1357 {
1358 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1359 uint16_t n = 0;
1360
1361 /**
1362 * Begin scanning the H/W ring for done descriptors when the number
1363 * of available descriptors drops below tx_free_thresh. For each done
1364 * descriptor, free the associated buffer.
1365 */
1366 if (txq->nb_tx_free < txq->tx_free_thresh)
1367 i40e_tx_free_bufs(txq);
1368
1369 /* Use available descriptor only */
1370 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1371 if (unlikely(!nb_pkts))
1372 return 0;
1373
1374 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1375 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1376 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1377 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1378 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1379 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1380 I40E_TXD_QW1_CMD_SHIFT);
1381 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1382 txq->tx_tail = 0;
1383 }
1384
1385 /* Fill hardware descriptor ring with mbuf data */
1386 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1387 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1388
1389 /* Determin if RS bit needs to be set */
1390 if (txq->tx_tail > txq->tx_next_rs) {
1391 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1392 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1393 I40E_TXD_QW1_CMD_SHIFT);
1394 txq->tx_next_rs =
1395 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1396 if (txq->tx_next_rs >= txq->nb_tx_desc)
1397 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1398 }
1399
1400 if (txq->tx_tail >= txq->nb_tx_desc)
1401 txq->tx_tail = 0;
1402
1403 /* Update the tx tail register */
1404 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1405
1406 return nb_pkts;
1407 }
1408
1409 static uint16_t
i40e_xmit_pkts_simple(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1410 i40e_xmit_pkts_simple(void *tx_queue,
1411 struct rte_mbuf **tx_pkts,
1412 uint16_t nb_pkts)
1413 {
1414 uint16_t nb_tx = 0;
1415
1416 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1417 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1418 tx_pkts, nb_pkts);
1419
1420 while (nb_pkts) {
1421 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1422 I40E_TX_MAX_BURST);
1423
1424 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1425 &tx_pkts[nb_tx], num);
1426 nb_tx = (uint16_t)(nb_tx + ret);
1427 nb_pkts = (uint16_t)(nb_pkts - ret);
1428 if (ret < num)
1429 break;
1430 }
1431
1432 return nb_tx;
1433 }
1434
1435 static uint16_t
i40e_xmit_pkts_vec(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1436 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1437 uint16_t nb_pkts)
1438 {
1439 uint16_t nb_tx = 0;
1440 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1441
1442 while (nb_pkts) {
1443 uint16_t ret, num;
1444
1445 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1446 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1447 num);
1448 nb_tx += ret;
1449 nb_pkts -= ret;
1450 if (ret < num)
1451 break;
1452 }
1453
1454 return nb_tx;
1455 }
1456
1457 /*********************************************************************
1458 *
1459 * TX prep functions
1460 *
1461 **********************************************************************/
1462 uint16_t
i40e_prep_pkts(__rte_unused void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1463 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1464 uint16_t nb_pkts)
1465 {
1466 int i, ret;
1467 uint64_t ol_flags;
1468 struct rte_mbuf *m;
1469
1470 for (i = 0; i < nb_pkts; i++) {
1471 m = tx_pkts[i];
1472 ol_flags = m->ol_flags;
1473
1474 /* Check for m->nb_segs to not exceed the limits. */
1475 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1476 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1477 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1478 rte_errno = EINVAL;
1479 return i;
1480 }
1481 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1482 m->tso_segsz < I40E_MIN_TSO_MSS ||
1483 m->tso_segsz > I40E_MAX_TSO_MSS ||
1484 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1485 /* MSS outside the range (256B - 9674B) are considered
1486 * malicious
1487 */
1488 rte_errno = EINVAL;
1489 return i;
1490 }
1491
1492 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1493 rte_errno = ENOTSUP;
1494 return i;
1495 }
1496
1497 /* check the size of packet */
1498 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1499 rte_errno = EINVAL;
1500 return i;
1501 }
1502
1503 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1504 ret = rte_validate_tx_offload(m);
1505 if (ret != 0) {
1506 rte_errno = -ret;
1507 return i;
1508 }
1509 #endif
1510 ret = rte_net_intel_cksum_prepare(m);
1511 if (ret != 0) {
1512 rte_errno = -ret;
1513 return i;
1514 }
1515 }
1516 return i;
1517 }
1518
1519 /*
1520 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1521 * application used, which assume having sequential ones. But from driver's
1522 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1523 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1524 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1525 * use queue_idx from 0 to 95 to access queues, while real queue would be
1526 * different. This function will do a queue mapping to find VSI the queue
1527 * belongs to.
1528 */
1529 static struct i40e_vsi*
i40e_pf_get_vsi_by_qindex(struct i40e_pf * pf,uint16_t queue_idx)1530 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1531 {
1532 /* the queue in MAIN VSI range */
1533 if (queue_idx < pf->main_vsi->nb_qps)
1534 return pf->main_vsi;
1535
1536 queue_idx -= pf->main_vsi->nb_qps;
1537
1538 /* queue_idx is greater than VMDQ VSIs range */
1539 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1540 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1541 return NULL;
1542 }
1543
1544 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1545 }
1546
1547 static uint16_t
i40e_get_queue_offset_by_qindex(struct i40e_pf * pf,uint16_t queue_idx)1548 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1549 {
1550 /* the queue in MAIN VSI range */
1551 if (queue_idx < pf->main_vsi->nb_qps)
1552 return queue_idx;
1553
1554 /* It's VMDQ queues */
1555 queue_idx -= pf->main_vsi->nb_qps;
1556
1557 if (pf->nb_cfg_vmdq_vsi)
1558 return queue_idx % pf->vmdq_nb_qps;
1559 else {
1560 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1561 return (uint16_t)(-1);
1562 }
1563 }
1564
1565 int
i40e_dev_rx_queue_start(struct rte_eth_dev * dev,uint16_t rx_queue_id)1566 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1567 {
1568 struct i40e_rx_queue *rxq;
1569 int err;
1570 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571
1572 PMD_INIT_FUNC_TRACE();
1573
1574 rxq = dev->data->rx_queues[rx_queue_id];
1575 if (!rxq || !rxq->q_set) {
1576 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1577 rx_queue_id);
1578 return -EINVAL;
1579 }
1580
1581 if (rxq->rx_deferred_start)
1582 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1583 rx_queue_id);
1584
1585 err = i40e_alloc_rx_queue_mbufs(rxq);
1586 if (err) {
1587 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1588 return err;
1589 }
1590
1591 /* Init the RX tail regieter. */
1592 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1593
1594 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1595 if (err) {
1596 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1597 rx_queue_id);
1598
1599 i40e_rx_queue_release_mbufs(rxq);
1600 i40e_reset_rx_queue(rxq);
1601 return err;
1602 }
1603 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1604
1605 return 0;
1606 }
1607
1608 int
i40e_dev_rx_queue_stop(struct rte_eth_dev * dev,uint16_t rx_queue_id)1609 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1610 {
1611 struct i40e_rx_queue *rxq;
1612 int err;
1613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614
1615 rxq = dev->data->rx_queues[rx_queue_id];
1616 if (!rxq || !rxq->q_set) {
1617 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1618 rx_queue_id);
1619 return -EINVAL;
1620 }
1621
1622 /*
1623 * rx_queue_id is queue id application refers to, while
1624 * rxq->reg_idx is the real queue index.
1625 */
1626 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1627 if (err) {
1628 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1629 rx_queue_id);
1630 return err;
1631 }
1632 i40e_rx_queue_release_mbufs(rxq);
1633 i40e_reset_rx_queue(rxq);
1634 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1635
1636 return 0;
1637 }
1638
1639 int
i40e_dev_tx_queue_start(struct rte_eth_dev * dev,uint16_t tx_queue_id)1640 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1641 {
1642 int err;
1643 struct i40e_tx_queue *txq;
1644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645
1646 PMD_INIT_FUNC_TRACE();
1647
1648 txq = dev->data->tx_queues[tx_queue_id];
1649 if (!txq || !txq->q_set) {
1650 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1651 tx_queue_id);
1652 return -EINVAL;
1653 }
1654
1655 if (txq->tx_deferred_start)
1656 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1657 tx_queue_id);
1658
1659 /*
1660 * tx_queue_id is queue id application refers to, while
1661 * rxq->reg_idx is the real queue index.
1662 */
1663 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1664 if (err) {
1665 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1666 tx_queue_id);
1667 return err;
1668 }
1669 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1670
1671 return 0;
1672 }
1673
1674 int
i40e_dev_tx_queue_stop(struct rte_eth_dev * dev,uint16_t tx_queue_id)1675 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1676 {
1677 struct i40e_tx_queue *txq;
1678 int err;
1679 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680
1681 txq = dev->data->tx_queues[tx_queue_id];
1682 if (!txq || !txq->q_set) {
1683 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1684 tx_queue_id);
1685 return -EINVAL;
1686 }
1687
1688 /*
1689 * tx_queue_id is queue id application refers to, while
1690 * txq->reg_idx is the real queue index.
1691 */
1692 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1693 if (err) {
1694 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1695 tx_queue_id);
1696 return err;
1697 }
1698
1699 i40e_tx_queue_release_mbufs(txq);
1700 i40e_reset_tx_queue(txq);
1701 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1702
1703 return 0;
1704 }
1705
1706 const uint32_t *
i40e_dev_supported_ptypes_get(struct rte_eth_dev * dev)1707 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1708 {
1709 static const uint32_t ptypes[] = {
1710 /* refers to i40e_rxd_pkt_type_mapping() */
1711 RTE_PTYPE_L2_ETHER,
1712 RTE_PTYPE_L2_ETHER_TIMESYNC,
1713 RTE_PTYPE_L2_ETHER_LLDP,
1714 RTE_PTYPE_L2_ETHER_ARP,
1715 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1716 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1717 RTE_PTYPE_L4_FRAG,
1718 RTE_PTYPE_L4_ICMP,
1719 RTE_PTYPE_L4_NONFRAG,
1720 RTE_PTYPE_L4_SCTP,
1721 RTE_PTYPE_L4_TCP,
1722 RTE_PTYPE_L4_UDP,
1723 RTE_PTYPE_TUNNEL_GRENAT,
1724 RTE_PTYPE_TUNNEL_IP,
1725 RTE_PTYPE_INNER_L2_ETHER,
1726 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1727 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1728 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1729 RTE_PTYPE_INNER_L4_FRAG,
1730 RTE_PTYPE_INNER_L4_ICMP,
1731 RTE_PTYPE_INNER_L4_NONFRAG,
1732 RTE_PTYPE_INNER_L4_SCTP,
1733 RTE_PTYPE_INNER_L4_TCP,
1734 RTE_PTYPE_INNER_L4_UDP,
1735 RTE_PTYPE_UNKNOWN
1736 };
1737
1738 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1739 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1740 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1741 #endif
1742 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1743 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1744 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1745 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1746 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1747 return ptypes;
1748 return NULL;
1749 }
1750
1751 static int
i40e_dev_first_queue(uint16_t idx,void ** queues,int num)1752 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1753 {
1754 uint16_t i;
1755
1756 for (i = 0; i < num; i++) {
1757 if (i != idx && queues[i])
1758 return 0;
1759 }
1760
1761 return 1;
1762 }
1763
1764 static int
i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev * dev,struct i40e_rx_queue * rxq)1765 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1766 struct i40e_rx_queue *rxq)
1767 {
1768 struct i40e_adapter *ad =
1769 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1770 int use_def_burst_func =
1771 check_rx_burst_bulk_alloc_preconditions(rxq);
1772 uint16_t buf_size =
1773 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1774 RTE_PKTMBUF_HEADROOM);
1775 int use_scattered_rx =
1776 (rxq->max_pkt_len > buf_size);
1777
1778 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1779 PMD_DRV_LOG(ERR,
1780 "Failed to do RX queue initialization");
1781 return -EINVAL;
1782 }
1783
1784 if (i40e_dev_first_queue(rxq->queue_id,
1785 dev->data->rx_queues,
1786 dev->data->nb_rx_queues)) {
1787 /**
1788 * If it is the first queue to setup,
1789 * set all flags to default and call
1790 * i40e_set_rx_function.
1791 */
1792 ad->rx_bulk_alloc_allowed = true;
1793 ad->rx_vec_allowed = true;
1794 dev->data->scattered_rx = use_scattered_rx;
1795 if (use_def_burst_func)
1796 ad->rx_bulk_alloc_allowed = false;
1797 i40e_set_rx_function(dev);
1798 return 0;
1799 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1800 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1801 " number %d of queue %d isn't power of 2",
1802 rxq->nb_rx_desc, rxq->queue_id);
1803 return -EINVAL;
1804 }
1805
1806 /* check bulk alloc conflict */
1807 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1808 PMD_DRV_LOG(ERR, "Can't use default burst.");
1809 return -EINVAL;
1810 }
1811 /* check scatterred conflict */
1812 if (!dev->data->scattered_rx && use_scattered_rx) {
1813 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1814 return -EINVAL;
1815 }
1816 /* check vector conflict */
1817 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1818 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1819 return -EINVAL;
1820 }
1821
1822 return 0;
1823 }
1824
1825 int
i40e_dev_rx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_rxconf * rx_conf,struct rte_mempool * mp)1826 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1827 uint16_t queue_idx,
1828 uint16_t nb_desc,
1829 unsigned int socket_id,
1830 const struct rte_eth_rxconf *rx_conf,
1831 struct rte_mempool *mp)
1832 {
1833 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834 struct i40e_adapter *ad =
1835 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1836 struct i40e_vsi *vsi;
1837 struct i40e_pf *pf = NULL;
1838 struct i40e_vf *vf = NULL;
1839 struct i40e_rx_queue *rxq;
1840 const struct rte_memzone *rz;
1841 uint32_t ring_size;
1842 uint16_t len, i;
1843 uint16_t reg_idx, base, bsf, tc_mapping;
1844 int q_offset, use_def_burst_func = 1;
1845 uint64_t offloads;
1846
1847 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1848
1849 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1850 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1851 vsi = &vf->vsi;
1852 if (!vsi)
1853 return -EINVAL;
1854 reg_idx = queue_idx;
1855 } else {
1856 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1857 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1858 if (!vsi)
1859 return -EINVAL;
1860 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1861 if (q_offset < 0)
1862 return -EINVAL;
1863 reg_idx = vsi->base_queue + q_offset;
1864 }
1865
1866 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1867 (nb_desc > I40E_MAX_RING_DESC) ||
1868 (nb_desc < I40E_MIN_RING_DESC)) {
1869 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1870 "invalid", nb_desc);
1871 return -EINVAL;
1872 }
1873
1874 /* Free memory if needed */
1875 if (dev->data->rx_queues[queue_idx]) {
1876 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1877 dev->data->rx_queues[queue_idx] = NULL;
1878 }
1879
1880 /* Allocate the rx queue data structure */
1881 rxq = rte_zmalloc_socket("i40e rx queue",
1882 sizeof(struct i40e_rx_queue),
1883 RTE_CACHE_LINE_SIZE,
1884 socket_id);
1885 if (!rxq) {
1886 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1887 "rx queue data structure");
1888 return -ENOMEM;
1889 }
1890 rxq->mp = mp;
1891 rxq->nb_rx_desc = nb_desc;
1892 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1893 rxq->queue_id = queue_idx;
1894 rxq->reg_idx = reg_idx;
1895 rxq->port_id = dev->data->port_id;
1896 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1897 rxq->crc_len = RTE_ETHER_CRC_LEN;
1898 else
1899 rxq->crc_len = 0;
1900 rxq->drop_en = rx_conf->rx_drop_en;
1901 rxq->vsi = vsi;
1902 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1903 rxq->offloads = offloads;
1904
1905 /* Allocate the maximun number of RX ring hardware descriptor. */
1906 len = I40E_MAX_RING_DESC;
1907
1908 /**
1909 * Allocating a little more memory because vectorized/bulk_alloc Rx
1910 * functions doesn't check boundaries each time.
1911 */
1912 len += RTE_PMD_I40E_RX_MAX_BURST;
1913
1914 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1915 I40E_DMA_MEM_ALIGN);
1916
1917 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1918 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1919 if (!rz) {
1920 i40e_dev_rx_queue_release(rxq);
1921 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1922 return -ENOMEM;
1923 }
1924
1925 /* Zero all the descriptors in the ring. */
1926 memset(rz->addr, 0, ring_size);
1927
1928 rxq->rx_ring_phys_addr = rz->iova;
1929 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1930
1931 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1932
1933 /* Allocate the software ring. */
1934 rxq->sw_ring =
1935 rte_zmalloc_socket("i40e rx sw ring",
1936 sizeof(struct i40e_rx_entry) * len,
1937 RTE_CACHE_LINE_SIZE,
1938 socket_id);
1939 if (!rxq->sw_ring) {
1940 i40e_dev_rx_queue_release(rxq);
1941 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1942 return -ENOMEM;
1943 }
1944
1945 i40e_reset_rx_queue(rxq);
1946 rxq->q_set = TRUE;
1947
1948 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1949 if (!(vsi->enabled_tc & (1 << i)))
1950 continue;
1951 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1952 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1953 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1954 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1955 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1956
1957 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1958 rxq->dcb_tc = i;
1959 }
1960
1961 if (dev->data->dev_started) {
1962 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1963 i40e_dev_rx_queue_release(rxq);
1964 return -EINVAL;
1965 }
1966 } else {
1967 use_def_burst_func =
1968 check_rx_burst_bulk_alloc_preconditions(rxq);
1969 if (!use_def_burst_func) {
1970 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1971 PMD_INIT_LOG(DEBUG,
1972 "Rx Burst Bulk Alloc Preconditions are "
1973 "satisfied. Rx Burst Bulk Alloc function will be "
1974 "used on port=%d, queue=%d.",
1975 rxq->port_id, rxq->queue_id);
1976 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1977 } else {
1978 PMD_INIT_LOG(DEBUG,
1979 "Rx Burst Bulk Alloc Preconditions are "
1980 "not satisfied, Scattered Rx is requested, "
1981 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1982 "not enabled on port=%d, queue=%d.",
1983 rxq->port_id, rxq->queue_id);
1984 ad->rx_bulk_alloc_allowed = false;
1985 }
1986 }
1987
1988 dev->data->rx_queues[queue_idx] = rxq;
1989 return 0;
1990 }
1991
1992 void
i40e_dev_rx_queue_release(void * rxq)1993 i40e_dev_rx_queue_release(void *rxq)
1994 {
1995 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1996
1997 if (!q) {
1998 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1999 return;
2000 }
2001
2002 i40e_rx_queue_release_mbufs(q);
2003 rte_free(q->sw_ring);
2004 rte_free(q);
2005 }
2006
2007 uint32_t
i40e_dev_rx_queue_count(struct rte_eth_dev * dev,uint16_t rx_queue_id)2008 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2009 {
2010 #define I40E_RXQ_SCAN_INTERVAL 4
2011 volatile union i40e_rx_desc *rxdp;
2012 struct i40e_rx_queue *rxq;
2013 uint16_t desc = 0;
2014
2015 rxq = dev->data->rx_queues[rx_queue_id];
2016 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2017 while ((desc < rxq->nb_rx_desc) &&
2018 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2019 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2020 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2021 /**
2022 * Check the DD bit of a rx descriptor of each 4 in a group,
2023 * to avoid checking too frequently and downgrading performance
2024 * too much.
2025 */
2026 desc += I40E_RXQ_SCAN_INTERVAL;
2027 rxdp += I40E_RXQ_SCAN_INTERVAL;
2028 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2029 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2030 desc - rxq->nb_rx_desc]);
2031 }
2032
2033 return desc;
2034 }
2035
2036 int
i40e_dev_rx_descriptor_done(void * rx_queue,uint16_t offset)2037 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2038 {
2039 volatile union i40e_rx_desc *rxdp;
2040 struct i40e_rx_queue *rxq = rx_queue;
2041 uint16_t desc;
2042 int ret;
2043
2044 if (unlikely(offset >= rxq->nb_rx_desc)) {
2045 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2046 return 0;
2047 }
2048
2049 desc = rxq->rx_tail + offset;
2050 if (desc >= rxq->nb_rx_desc)
2051 desc -= rxq->nb_rx_desc;
2052
2053 rxdp = &(rxq->rx_ring[desc]);
2054
2055 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2056 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2057 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2058
2059 return ret;
2060 }
2061
2062 int
i40e_dev_rx_descriptor_status(void * rx_queue,uint16_t offset)2063 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2064 {
2065 struct i40e_rx_queue *rxq = rx_queue;
2066 volatile uint64_t *status;
2067 uint64_t mask;
2068 uint32_t desc;
2069
2070 if (unlikely(offset >= rxq->nb_rx_desc))
2071 return -EINVAL;
2072
2073 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2074 return RTE_ETH_RX_DESC_UNAVAIL;
2075
2076 desc = rxq->rx_tail + offset;
2077 if (desc >= rxq->nb_rx_desc)
2078 desc -= rxq->nb_rx_desc;
2079
2080 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2081 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2082 << I40E_RXD_QW1_STATUS_SHIFT);
2083 if (*status & mask)
2084 return RTE_ETH_RX_DESC_DONE;
2085
2086 return RTE_ETH_RX_DESC_AVAIL;
2087 }
2088
2089 int
i40e_dev_tx_descriptor_status(void * tx_queue,uint16_t offset)2090 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2091 {
2092 struct i40e_tx_queue *txq = tx_queue;
2093 volatile uint64_t *status;
2094 uint64_t mask, expect;
2095 uint32_t desc;
2096
2097 if (unlikely(offset >= txq->nb_tx_desc))
2098 return -EINVAL;
2099
2100 desc = txq->tx_tail + offset;
2101 /* go to next desc that has the RS bit */
2102 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2103 txq->tx_rs_thresh;
2104 if (desc >= txq->nb_tx_desc) {
2105 desc -= txq->nb_tx_desc;
2106 if (desc >= txq->nb_tx_desc)
2107 desc -= txq->nb_tx_desc;
2108 }
2109
2110 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2111 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2112 expect = rte_cpu_to_le_64(
2113 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2114 if ((*status & mask) == expect)
2115 return RTE_ETH_TX_DESC_DONE;
2116
2117 return RTE_ETH_TX_DESC_FULL;
2118 }
2119
2120 static int
i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev * dev,struct i40e_tx_queue * txq)2121 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2122 struct i40e_tx_queue *txq)
2123 {
2124 struct i40e_adapter *ad =
2125 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2126
2127 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2128 PMD_DRV_LOG(ERR,
2129 "Failed to do TX queue initialization");
2130 return -EINVAL;
2131 }
2132
2133 if (i40e_dev_first_queue(txq->queue_id,
2134 dev->data->tx_queues,
2135 dev->data->nb_tx_queues)) {
2136 /**
2137 * If it is the first queue to setup,
2138 * set all flags and call
2139 * i40e_set_tx_function.
2140 */
2141 i40e_set_tx_function_flag(dev, txq);
2142 i40e_set_tx_function(dev);
2143 return 0;
2144 }
2145
2146 /* check vector conflict */
2147 if (ad->tx_vec_allowed) {
2148 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2149 i40e_txq_vec_setup(txq)) {
2150 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2151 return -EINVAL;
2152 }
2153 }
2154 /* check simple tx conflict */
2155 if (ad->tx_simple_allowed) {
2156 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2157 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2158 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2159 return -EINVAL;
2160 }
2161 }
2162
2163 return 0;
2164 }
2165
2166 int
i40e_dev_tx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_txconf * tx_conf)2167 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2168 uint16_t queue_idx,
2169 uint16_t nb_desc,
2170 unsigned int socket_id,
2171 const struct rte_eth_txconf *tx_conf)
2172 {
2173 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174 struct i40e_vsi *vsi;
2175 struct i40e_pf *pf = NULL;
2176 struct i40e_vf *vf = NULL;
2177 struct i40e_tx_queue *txq;
2178 const struct rte_memzone *tz;
2179 uint32_t ring_size;
2180 uint16_t tx_rs_thresh, tx_free_thresh;
2181 uint16_t reg_idx, i, base, bsf, tc_mapping;
2182 int q_offset;
2183 uint64_t offloads;
2184
2185 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2186
2187 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2188 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2189 vsi = &vf->vsi;
2190 if (!vsi)
2191 return -EINVAL;
2192 reg_idx = queue_idx;
2193 } else {
2194 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2195 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2196 if (!vsi)
2197 return -EINVAL;
2198 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2199 if (q_offset < 0)
2200 return -EINVAL;
2201 reg_idx = vsi->base_queue + q_offset;
2202 }
2203
2204 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2205 (nb_desc > I40E_MAX_RING_DESC) ||
2206 (nb_desc < I40E_MIN_RING_DESC)) {
2207 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2208 "invalid", nb_desc);
2209 return -EINVAL;
2210 }
2211
2212 /**
2213 * The following two parameters control the setting of the RS bit on
2214 * transmit descriptors. TX descriptors will have their RS bit set
2215 * after txq->tx_rs_thresh descriptors have been used. The TX
2216 * descriptor ring will be cleaned after txq->tx_free_thresh
2217 * descriptors are used or if the number of descriptors required to
2218 * transmit a packet is greater than the number of free TX descriptors.
2219 *
2220 * The following constraints must be satisfied:
2221 * - tx_rs_thresh must be greater than 0.
2222 * - tx_rs_thresh must be less than the size of the ring minus 2.
2223 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2224 * - tx_rs_thresh must be a divisor of the ring size.
2225 * - tx_free_thresh must be greater than 0.
2226 * - tx_free_thresh must be less than the size of the ring minus 3.
2227 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2228 *
2229 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2230 * race condition, hence the maximum threshold constraints. When set
2231 * to zero use default values.
2232 */
2233 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2234 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2235 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2236 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2237 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2238 if (tx_conf->tx_rs_thresh > 0)
2239 tx_rs_thresh = tx_conf->tx_rs_thresh;
2240 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2241 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2242 "exceed nb_desc. (tx_rs_thresh=%u "
2243 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2244 (unsigned int)tx_rs_thresh,
2245 (unsigned int)tx_free_thresh,
2246 (unsigned int)nb_desc,
2247 (int)dev->data->port_id,
2248 (int)queue_idx);
2249 return I40E_ERR_PARAM;
2250 }
2251 if (tx_rs_thresh >= (nb_desc - 2)) {
2252 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2253 "number of TX descriptors minus 2. "
2254 "(tx_rs_thresh=%u port=%d queue=%d)",
2255 (unsigned int)tx_rs_thresh,
2256 (int)dev->data->port_id,
2257 (int)queue_idx);
2258 return I40E_ERR_PARAM;
2259 }
2260 if (tx_free_thresh >= (nb_desc - 3)) {
2261 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2262 "number of TX descriptors minus 3. "
2263 "(tx_free_thresh=%u port=%d queue=%d)",
2264 (unsigned int)tx_free_thresh,
2265 (int)dev->data->port_id,
2266 (int)queue_idx);
2267 return I40E_ERR_PARAM;
2268 }
2269 if (tx_rs_thresh > tx_free_thresh) {
2270 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2271 "equal to tx_free_thresh. (tx_free_thresh=%u"
2272 " tx_rs_thresh=%u port=%d queue=%d)",
2273 (unsigned int)tx_free_thresh,
2274 (unsigned int)tx_rs_thresh,
2275 (int)dev->data->port_id,
2276 (int)queue_idx);
2277 return I40E_ERR_PARAM;
2278 }
2279 if ((nb_desc % tx_rs_thresh) != 0) {
2280 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2281 "number of TX descriptors. (tx_rs_thresh=%u"
2282 " port=%d queue=%d)",
2283 (unsigned int)tx_rs_thresh,
2284 (int)dev->data->port_id,
2285 (int)queue_idx);
2286 return I40E_ERR_PARAM;
2287 }
2288 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2289 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2290 "tx_rs_thresh is greater than 1. "
2291 "(tx_rs_thresh=%u port=%d queue=%d)",
2292 (unsigned int)tx_rs_thresh,
2293 (int)dev->data->port_id,
2294 (int)queue_idx);
2295 return I40E_ERR_PARAM;
2296 }
2297
2298 /* Free memory if needed. */
2299 if (dev->data->tx_queues[queue_idx]) {
2300 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2301 dev->data->tx_queues[queue_idx] = NULL;
2302 }
2303
2304 /* Allocate the TX queue data structure. */
2305 txq = rte_zmalloc_socket("i40e tx queue",
2306 sizeof(struct i40e_tx_queue),
2307 RTE_CACHE_LINE_SIZE,
2308 socket_id);
2309 if (!txq) {
2310 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2311 "tx queue structure");
2312 return -ENOMEM;
2313 }
2314
2315 /* Allocate TX hardware ring descriptors. */
2316 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2317 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2318 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2319 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2320 if (!tz) {
2321 i40e_dev_tx_queue_release(txq);
2322 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2323 return -ENOMEM;
2324 }
2325
2326 txq->nb_tx_desc = nb_desc;
2327 txq->tx_rs_thresh = tx_rs_thresh;
2328 txq->tx_free_thresh = tx_free_thresh;
2329 txq->pthresh = tx_conf->tx_thresh.pthresh;
2330 txq->hthresh = tx_conf->tx_thresh.hthresh;
2331 txq->wthresh = tx_conf->tx_thresh.wthresh;
2332 txq->queue_id = queue_idx;
2333 txq->reg_idx = reg_idx;
2334 txq->port_id = dev->data->port_id;
2335 txq->offloads = offloads;
2336 txq->vsi = vsi;
2337 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2338
2339 txq->tx_ring_phys_addr = tz->iova;
2340 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2341
2342 /* Allocate software ring */
2343 txq->sw_ring =
2344 rte_zmalloc_socket("i40e tx sw ring",
2345 sizeof(struct i40e_tx_entry) * nb_desc,
2346 RTE_CACHE_LINE_SIZE,
2347 socket_id);
2348 if (!txq->sw_ring) {
2349 i40e_dev_tx_queue_release(txq);
2350 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2351 return -ENOMEM;
2352 }
2353
2354 i40e_reset_tx_queue(txq);
2355 txq->q_set = TRUE;
2356
2357 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2358 if (!(vsi->enabled_tc & (1 << i)))
2359 continue;
2360 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2361 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2362 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2363 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2364 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2365
2366 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2367 txq->dcb_tc = i;
2368 }
2369
2370 if (dev->data->dev_started) {
2371 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2372 i40e_dev_tx_queue_release(txq);
2373 return -EINVAL;
2374 }
2375 } else {
2376 /**
2377 * Use a simple TX queue without offloads or
2378 * multi segs if possible
2379 */
2380 i40e_set_tx_function_flag(dev, txq);
2381 }
2382 dev->data->tx_queues[queue_idx] = txq;
2383
2384 return 0;
2385 }
2386
2387 void
i40e_dev_tx_queue_release(void * txq)2388 i40e_dev_tx_queue_release(void *txq)
2389 {
2390 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2391
2392 if (!q) {
2393 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2394 return;
2395 }
2396
2397 i40e_tx_queue_release_mbufs(q);
2398 rte_free(q->sw_ring);
2399 rte_free(q);
2400 }
2401
2402 const struct rte_memzone *
i40e_memzone_reserve(const char * name,uint32_t len,int socket_id)2403 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2404 {
2405 const struct rte_memzone *mz;
2406
2407 mz = rte_memzone_lookup(name);
2408 if (mz)
2409 return mz;
2410
2411 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2412 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2413 return mz;
2414 }
2415
2416 void
i40e_rx_queue_release_mbufs(struct i40e_rx_queue * rxq)2417 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2418 {
2419 uint16_t i;
2420
2421 /* SSE Vector driver has a different way of releasing mbufs. */
2422 if (rxq->rx_using_sse) {
2423 i40e_rx_queue_release_mbufs_vec(rxq);
2424 return;
2425 }
2426
2427 if (!rxq->sw_ring) {
2428 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2429 return;
2430 }
2431
2432 for (i = 0; i < rxq->nb_rx_desc; i++) {
2433 if (rxq->sw_ring[i].mbuf) {
2434 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2435 rxq->sw_ring[i].mbuf = NULL;
2436 }
2437 }
2438 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2439 if (rxq->rx_nb_avail == 0)
2440 return;
2441 for (i = 0; i < rxq->rx_nb_avail; i++) {
2442 struct rte_mbuf *mbuf;
2443
2444 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2445 rte_pktmbuf_free_seg(mbuf);
2446 }
2447 rxq->rx_nb_avail = 0;
2448 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2449 }
2450
2451 void
i40e_reset_rx_queue(struct i40e_rx_queue * rxq)2452 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2453 {
2454 unsigned i;
2455 uint16_t len;
2456
2457 if (!rxq) {
2458 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2459 return;
2460 }
2461
2462 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2463 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2464 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2465 else
2466 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2467 len = rxq->nb_rx_desc;
2468
2469 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2470 ((volatile char *)rxq->rx_ring)[i] = 0;
2471
2472 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2473 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2474 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2475
2476 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2477 rxq->rx_nb_avail = 0;
2478 rxq->rx_next_avail = 0;
2479 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2480 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2481 rxq->rx_tail = 0;
2482 rxq->nb_rx_hold = 0;
2483 rxq->pkt_first_seg = NULL;
2484 rxq->pkt_last_seg = NULL;
2485
2486 rxq->rxrearm_start = 0;
2487 rxq->rxrearm_nb = 0;
2488 }
2489
2490 void
i40e_tx_queue_release_mbufs(struct i40e_tx_queue * txq)2491 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2492 {
2493 struct rte_eth_dev *dev;
2494 uint16_t i;
2495
2496 if (!txq || !txq->sw_ring) {
2497 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2498 return;
2499 }
2500
2501 dev = &rte_eth_devices[txq->port_id];
2502
2503 /**
2504 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2505 * so need to free remains more carefully.
2506 */
2507 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2508 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2509 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2510 if (txq->tx_tail < i) {
2511 for (; i < txq->nb_tx_desc; i++) {
2512 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2513 txq->sw_ring[i].mbuf = NULL;
2514 }
2515 i = 0;
2516 }
2517 for (; i < txq->tx_tail; i++) {
2518 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2519 txq->sw_ring[i].mbuf = NULL;
2520 }
2521 } else {
2522 for (i = 0; i < txq->nb_tx_desc; i++) {
2523 if (txq->sw_ring[i].mbuf) {
2524 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2525 txq->sw_ring[i].mbuf = NULL;
2526 }
2527 }
2528 }
2529 }
2530
2531 static int
i40e_tx_done_cleanup_full(struct i40e_tx_queue * txq,uint32_t free_cnt)2532 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2533 uint32_t free_cnt)
2534 {
2535 struct i40e_tx_entry *swr_ring = txq->sw_ring;
2536 uint16_t i, tx_last, tx_id;
2537 uint16_t nb_tx_free_last;
2538 uint16_t nb_tx_to_clean;
2539 uint32_t pkt_cnt;
2540
2541 /* Start free mbuf from the next of tx_tail */
2542 tx_last = txq->tx_tail;
2543 tx_id = swr_ring[tx_last].next_id;
2544
2545 if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2546 return 0;
2547
2548 nb_tx_to_clean = txq->nb_tx_free;
2549 nb_tx_free_last = txq->nb_tx_free;
2550 if (!free_cnt)
2551 free_cnt = txq->nb_tx_desc;
2552
2553 /* Loop through swr_ring to count the amount of
2554 * freeable mubfs and packets.
2555 */
2556 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2557 for (i = 0; i < nb_tx_to_clean &&
2558 pkt_cnt < free_cnt &&
2559 tx_id != tx_last; i++) {
2560 if (swr_ring[tx_id].mbuf != NULL) {
2561 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2562 swr_ring[tx_id].mbuf = NULL;
2563
2564 /*
2565 * last segment in the packet,
2566 * increment packet count
2567 */
2568 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2569 }
2570
2571 tx_id = swr_ring[tx_id].next_id;
2572 }
2573
2574 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2575 txq->nb_tx_free || tx_id == tx_last)
2576 break;
2577
2578 if (pkt_cnt < free_cnt) {
2579 if (i40e_xmit_cleanup(txq))
2580 break;
2581
2582 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2583 nb_tx_free_last = txq->nb_tx_free;
2584 }
2585 }
2586
2587 return (int)pkt_cnt;
2588 }
2589
2590 static int
i40e_tx_done_cleanup_simple(struct i40e_tx_queue * txq,uint32_t free_cnt)2591 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2592 uint32_t free_cnt)
2593 {
2594 int i, n, cnt;
2595
2596 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2597 free_cnt = txq->nb_tx_desc;
2598
2599 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2600
2601 for (i = 0; i < cnt; i += n) {
2602 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2603 break;
2604
2605 n = i40e_tx_free_bufs(txq);
2606
2607 if (n == 0)
2608 break;
2609 }
2610
2611 return i;
2612 }
2613
2614 static int
i40e_tx_done_cleanup_vec(struct i40e_tx_queue * txq __rte_unused,uint32_t free_cnt __rte_unused)2615 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2616 uint32_t free_cnt __rte_unused)
2617 {
2618 return -ENOTSUP;
2619 }
2620 int
i40e_tx_done_cleanup(void * txq,uint32_t free_cnt)2621 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2622 {
2623 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2624 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2625 struct i40e_adapter *ad =
2626 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2627
2628 if (ad->tx_simple_allowed) {
2629 if (ad->tx_vec_allowed)
2630 return i40e_tx_done_cleanup_vec(q, free_cnt);
2631 else
2632 return i40e_tx_done_cleanup_simple(q, free_cnt);
2633 } else {
2634 return i40e_tx_done_cleanup_full(q, free_cnt);
2635 }
2636 }
2637
2638 void
i40e_reset_tx_queue(struct i40e_tx_queue * txq)2639 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2640 {
2641 struct i40e_tx_entry *txe;
2642 uint16_t i, prev, size;
2643
2644 if (!txq) {
2645 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2646 return;
2647 }
2648
2649 txe = txq->sw_ring;
2650 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2651 for (i = 0; i < size; i++)
2652 ((volatile char *)txq->tx_ring)[i] = 0;
2653
2654 prev = (uint16_t)(txq->nb_tx_desc - 1);
2655 for (i = 0; i < txq->nb_tx_desc; i++) {
2656 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2657
2658 txd->cmd_type_offset_bsz =
2659 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2660 txe[i].mbuf = NULL;
2661 txe[i].last_id = i;
2662 txe[prev].next_id = i;
2663 prev = i;
2664 }
2665
2666 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2667 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2668
2669 txq->tx_tail = 0;
2670 txq->nb_tx_used = 0;
2671
2672 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2673 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2674 }
2675
2676 /* Init the TX queue in hardware */
2677 int
i40e_tx_queue_init(struct i40e_tx_queue * txq)2678 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2679 {
2680 enum i40e_status_code err = I40E_SUCCESS;
2681 struct i40e_vsi *vsi = txq->vsi;
2682 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2683 uint16_t pf_q = txq->reg_idx;
2684 struct i40e_hmc_obj_txq tx_ctx;
2685 uint32_t qtx_ctl;
2686
2687 /* clear the context structure first */
2688 memset(&tx_ctx, 0, sizeof(tx_ctx));
2689 tx_ctx.new_context = 1;
2690 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2691 tx_ctx.qlen = txq->nb_tx_desc;
2692
2693 #ifdef RTE_LIBRTE_IEEE1588
2694 tx_ctx.timesync_ena = 1;
2695 #endif
2696 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2697 if (vsi->type == I40E_VSI_FDIR)
2698 tx_ctx.fd_ena = TRUE;
2699
2700 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2701 if (err != I40E_SUCCESS) {
2702 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2703 return err;
2704 }
2705
2706 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2707 if (err != I40E_SUCCESS) {
2708 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2709 return err;
2710 }
2711
2712 /* Now associate this queue with this PCI function */
2713 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2714 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2715 I40E_QTX_CTL_PF_INDX_MASK);
2716 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2717 I40E_WRITE_FLUSH(hw);
2718
2719 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2720
2721 return err;
2722 }
2723
2724 int
i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue * rxq)2725 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2726 {
2727 struct i40e_rx_entry *rxe = rxq->sw_ring;
2728 uint64_t dma_addr;
2729 uint16_t i;
2730
2731 for (i = 0; i < rxq->nb_rx_desc; i++) {
2732 volatile union i40e_rx_desc *rxd;
2733 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2734
2735 if (unlikely(!mbuf)) {
2736 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2737 return -ENOMEM;
2738 }
2739
2740 rte_mbuf_refcnt_set(mbuf, 1);
2741 mbuf->next = NULL;
2742 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2743 mbuf->nb_segs = 1;
2744 mbuf->port = rxq->port_id;
2745
2746 dma_addr =
2747 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2748
2749 rxd = &rxq->rx_ring[i];
2750 rxd->read.pkt_addr = dma_addr;
2751 rxd->read.hdr_addr = 0;
2752 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2753 rxd->read.rsvd1 = 0;
2754 rxd->read.rsvd2 = 0;
2755 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2756
2757 rxe[i].mbuf = mbuf;
2758 }
2759
2760 return 0;
2761 }
2762
2763 /*
2764 * Calculate the buffer length, and check the jumbo frame
2765 * and maximum packet length.
2766 */
2767 static int
i40e_rx_queue_config(struct i40e_rx_queue * rxq)2768 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2769 {
2770 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2771 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2772 struct rte_eth_dev_data *data = pf->dev_data;
2773 uint16_t buf_size;
2774
2775 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2776 RTE_PKTMBUF_HEADROOM);
2777
2778 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2779 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2780 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2781 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2782 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2783 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2784 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2785 rxq->hs_mode = i40e_header_split_enabled;
2786 break;
2787 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2788 default:
2789 rxq->rx_hdr_len = 0;
2790 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2791 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2792 rxq->hs_mode = i40e_header_split_none;
2793 break;
2794 }
2795
2796 rxq->max_pkt_len =
2797 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2798 rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2799 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2800 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
2801 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2802 PMD_DRV_LOG(ERR, "maximum packet length must "
2803 "be larger than %u and smaller than %u,"
2804 "as jumbo frame is enabled",
2805 (uint32_t)RTE_ETHER_MAX_LEN,
2806 (uint32_t)I40E_FRAME_SIZE_MAX);
2807 return I40E_ERR_CONFIG;
2808 }
2809 } else {
2810 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2811 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
2812 PMD_DRV_LOG(ERR, "maximum packet length must be "
2813 "larger than %u and smaller than %u, "
2814 "as jumbo frame is disabled",
2815 (uint32_t)RTE_ETHER_MIN_LEN,
2816 (uint32_t)RTE_ETHER_MAX_LEN);
2817 return I40E_ERR_CONFIG;
2818 }
2819 }
2820
2821 return 0;
2822 }
2823
2824 /* Init the RX queue in hardware */
2825 int
i40e_rx_queue_init(struct i40e_rx_queue * rxq)2826 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2827 {
2828 int err = I40E_SUCCESS;
2829 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2830 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2831 uint16_t pf_q = rxq->reg_idx;
2832 uint16_t buf_size;
2833 struct i40e_hmc_obj_rxq rx_ctx;
2834
2835 err = i40e_rx_queue_config(rxq);
2836 if (err < 0) {
2837 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2838 return err;
2839 }
2840
2841 /* Clear the context structure first */
2842 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2843 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2844 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2845
2846 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2847 rx_ctx.qlen = rxq->nb_rx_desc;
2848 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2849 rx_ctx.dsize = 1;
2850 #endif
2851 rx_ctx.dtype = rxq->hs_mode;
2852 if (rxq->hs_mode)
2853 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2854 else
2855 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2856 rx_ctx.rxmax = rxq->max_pkt_len;
2857 rx_ctx.tphrdesc_ena = 1;
2858 rx_ctx.tphwdesc_ena = 1;
2859 rx_ctx.tphdata_ena = 1;
2860 rx_ctx.tphhead_ena = 1;
2861 rx_ctx.lrxqthresh = 2;
2862 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2863 rx_ctx.l2tsel = 1;
2864 /* showiv indicates if inner VLAN is stripped inside of tunnel
2865 * packet. When set it to 1, vlan information is stripped from
2866 * the inner header, but the hardware does not put it in the
2867 * descriptor. So set it zero by default.
2868 */
2869 rx_ctx.showiv = 0;
2870 rx_ctx.prefena = 1;
2871
2872 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2873 if (err != I40E_SUCCESS) {
2874 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2875 return err;
2876 }
2877 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2878 if (err != I40E_SUCCESS) {
2879 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2880 return err;
2881 }
2882
2883 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2884
2885 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2886 RTE_PKTMBUF_HEADROOM);
2887
2888 /* Check if scattered RX needs to be used. */
2889 if (rxq->max_pkt_len > buf_size)
2890 dev_data->scattered_rx = 1;
2891
2892 /* Init the RX tail regieter. */
2893 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2894
2895 return 0;
2896 }
2897
2898 void
i40e_dev_clear_queues(struct rte_eth_dev * dev)2899 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2900 {
2901 uint16_t i;
2902
2903 PMD_INIT_FUNC_TRACE();
2904
2905 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2906 if (!dev->data->tx_queues[i])
2907 continue;
2908 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2909 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2910 }
2911
2912 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2913 if (!dev->data->rx_queues[i])
2914 continue;
2915 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2916 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2917 }
2918 }
2919
2920 void
i40e_dev_free_queues(struct rte_eth_dev * dev)2921 i40e_dev_free_queues(struct rte_eth_dev *dev)
2922 {
2923 uint16_t i;
2924
2925 PMD_INIT_FUNC_TRACE();
2926
2927 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2928 if (!dev->data->rx_queues[i])
2929 continue;
2930 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2931 dev->data->rx_queues[i] = NULL;
2932 rte_eth_dma_zone_free(dev, "rx_ring", i);
2933 }
2934
2935 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2936 if (!dev->data->tx_queues[i])
2937 continue;
2938 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2939 dev->data->tx_queues[i] = NULL;
2940 rte_eth_dma_zone_free(dev, "tx_ring", i);
2941 }
2942 }
2943
2944 enum i40e_status_code
i40e_fdir_setup_tx_resources(struct i40e_pf * pf)2945 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2946 {
2947 struct i40e_tx_queue *txq;
2948 const struct rte_memzone *tz = NULL;
2949 struct rte_eth_dev *dev;
2950 uint32_t ring_size;
2951
2952 if (!pf) {
2953 PMD_DRV_LOG(ERR, "PF is not available");
2954 return I40E_ERR_BAD_PTR;
2955 }
2956
2957 dev = pf->adapter->eth_dev;
2958
2959 /* Allocate the TX queue data structure. */
2960 txq = rte_zmalloc_socket("i40e fdir tx queue",
2961 sizeof(struct i40e_tx_queue),
2962 RTE_CACHE_LINE_SIZE,
2963 SOCKET_ID_ANY);
2964 if (!txq) {
2965 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2966 "tx queue structure.");
2967 return I40E_ERR_NO_MEMORY;
2968 }
2969
2970 /* Allocate TX hardware ring descriptors. */
2971 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2972 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2973
2974 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2975 I40E_FDIR_QUEUE_ID, ring_size,
2976 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2977 if (!tz) {
2978 i40e_dev_tx_queue_release(txq);
2979 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2980 return I40E_ERR_NO_MEMORY;
2981 }
2982
2983 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2984 txq->queue_id = I40E_FDIR_QUEUE_ID;
2985 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2986 txq->vsi = pf->fdir.fdir_vsi;
2987
2988 txq->tx_ring_phys_addr = tz->iova;
2989 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2990
2991 /*
2992 * don't need to allocate software ring and reset for the fdir
2993 * program queue just set the queue has been configured.
2994 */
2995 txq->q_set = TRUE;
2996 pf->fdir.txq = txq;
2997 pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
2998
2999 return I40E_SUCCESS;
3000 }
3001
3002 enum i40e_status_code
i40e_fdir_setup_rx_resources(struct i40e_pf * pf)3003 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3004 {
3005 struct i40e_rx_queue *rxq;
3006 const struct rte_memzone *rz = NULL;
3007 uint32_t ring_size;
3008 struct rte_eth_dev *dev;
3009
3010 if (!pf) {
3011 PMD_DRV_LOG(ERR, "PF is not available");
3012 return I40E_ERR_BAD_PTR;
3013 }
3014
3015 dev = pf->adapter->eth_dev;
3016
3017 /* Allocate the RX queue data structure. */
3018 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3019 sizeof(struct i40e_rx_queue),
3020 RTE_CACHE_LINE_SIZE,
3021 SOCKET_ID_ANY);
3022 if (!rxq) {
3023 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3024 "rx queue structure.");
3025 return I40E_ERR_NO_MEMORY;
3026 }
3027
3028 /* Allocate RX hardware ring descriptors. */
3029 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3030 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3031
3032 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3033 I40E_FDIR_QUEUE_ID, ring_size,
3034 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3035 if (!rz) {
3036 i40e_dev_rx_queue_release(rxq);
3037 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3038 return I40E_ERR_NO_MEMORY;
3039 }
3040
3041 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3042 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3043 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3044 rxq->vsi = pf->fdir.fdir_vsi;
3045
3046 rxq->rx_ring_phys_addr = rz->iova;
3047 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3048 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3049
3050 /*
3051 * Don't need to allocate software ring and reset for the fdir
3052 * rx queue, just set the queue has been configured.
3053 */
3054 rxq->q_set = TRUE;
3055 pf->fdir.rxq = rxq;
3056
3057 return I40E_SUCCESS;
3058 }
3059
3060 void
i40e_rxq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_rxq_info * qinfo)3061 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3062 struct rte_eth_rxq_info *qinfo)
3063 {
3064 struct i40e_rx_queue *rxq;
3065
3066 rxq = dev->data->rx_queues[queue_id];
3067
3068 qinfo->mp = rxq->mp;
3069 qinfo->scattered_rx = dev->data->scattered_rx;
3070 qinfo->nb_desc = rxq->nb_rx_desc;
3071
3072 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3073 qinfo->conf.rx_drop_en = rxq->drop_en;
3074 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3075 qinfo->conf.offloads = rxq->offloads;
3076 }
3077
3078 void
i40e_txq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_txq_info * qinfo)3079 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3080 struct rte_eth_txq_info *qinfo)
3081 {
3082 struct i40e_tx_queue *txq;
3083
3084 txq = dev->data->tx_queues[queue_id];
3085
3086 qinfo->nb_desc = txq->nb_tx_desc;
3087
3088 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3089 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3090 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3091
3092 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3093 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3094 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3095 qinfo->conf.offloads = txq->offloads;
3096 }
3097
3098 static eth_rx_burst_t
i40e_get_latest_rx_vec(bool scatter)3099 i40e_get_latest_rx_vec(bool scatter)
3100 {
3101 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3102 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) &&
3103 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3104 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
3105 i40e_recv_pkts_vec_avx2;
3106 #endif
3107 return scatter ? i40e_recv_scattered_pkts_vec :
3108 i40e_recv_pkts_vec;
3109 }
3110
3111 static eth_rx_burst_t
i40e_get_recommend_rx_vec(bool scatter)3112 i40e_get_recommend_rx_vec(bool scatter)
3113 {
3114 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3115 /*
3116 * since AVX frequency can be different to base frequency, limit
3117 * use of AVX2 version to later plaforms, not all those that could
3118 * theoretically run it.
3119 */
3120 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&
3121 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3122 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
3123 i40e_recv_pkts_vec_avx2;
3124 #endif
3125 return scatter ? i40e_recv_scattered_pkts_vec :
3126 i40e_recv_pkts_vec;
3127 }
3128
3129 void __rte_cold
i40e_set_rx_function(struct rte_eth_dev * dev)3130 i40e_set_rx_function(struct rte_eth_dev *dev)
3131 {
3132 struct i40e_adapter *ad =
3133 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3134 uint16_t rx_using_sse, i;
3135 /* In order to allow Vector Rx there are a few configuration
3136 * conditions to be met and Rx Bulk Allocation should be allowed.
3137 */
3138 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3139 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3140 !ad->rx_bulk_alloc_allowed) {
3141 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3142 " Vector Rx preconditions",
3143 dev->data->port_id);
3144
3145 ad->rx_vec_allowed = false;
3146 }
3147 if (ad->rx_vec_allowed) {
3148 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3149 struct i40e_rx_queue *rxq =
3150 dev->data->rx_queues[i];
3151
3152 if (rxq && i40e_rxq_vec_setup(rxq)) {
3153 ad->rx_vec_allowed = false;
3154 break;
3155 }
3156 }
3157 }
3158 }
3159
3160 if (ad->rx_vec_allowed &&
3161 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3162 /* Vec Rx path */
3163 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
3164 dev->data->port_id);
3165 if (ad->use_latest_vec)
3166 dev->rx_pkt_burst =
3167 i40e_get_latest_rx_vec(dev->data->scattered_rx);
3168 else
3169 dev->rx_pkt_burst =
3170 i40e_get_recommend_rx_vec(dev->data->scattered_rx);
3171 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3172 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3173 "satisfied. Rx Burst Bulk Alloc function "
3174 "will be used on port=%d.",
3175 dev->data->port_id);
3176
3177 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3178 } else {
3179 /* Simple Rx Path. */
3180 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3181 dev->data->port_id);
3182 dev->rx_pkt_burst = dev->data->scattered_rx ?
3183 i40e_recv_scattered_pkts :
3184 i40e_recv_pkts;
3185 }
3186
3187 /* Propagate information about RX function choice through all queues. */
3188 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3189 rx_using_sse =
3190 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3191 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3192 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3193 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3194
3195 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3196 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3197
3198 if (rxq)
3199 rxq->rx_using_sse = rx_using_sse;
3200 }
3201 }
3202 }
3203
3204 static const struct {
3205 eth_rx_burst_t pkt_burst;
3206 const char *info;
3207 } i40e_rx_burst_infos[] = {
3208 { i40e_recv_scattered_pkts, "Scalar Scattered" },
3209 { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3210 { i40e_recv_pkts, "Scalar" },
3211 #ifdef RTE_ARCH_X86
3212 { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3213 { i40e_recv_pkts_vec_avx2, "Vector AVX2" },
3214 { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3215 { i40e_recv_pkts_vec, "Vector SSE" },
3216 #elif defined(RTE_ARCH_ARM64)
3217 { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered" },
3218 { i40e_recv_pkts_vec, "Vector Neon" },
3219 #elif defined(RTE_ARCH_PPC_64)
3220 { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered" },
3221 { i40e_recv_pkts_vec, "Vector AltiVec" },
3222 #endif
3223 };
3224
3225 int
i40e_rx_burst_mode_get(struct rte_eth_dev * dev,__rte_unused uint16_t queue_id,struct rte_eth_burst_mode * mode)3226 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3227 struct rte_eth_burst_mode *mode)
3228 {
3229 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3230 int ret = -EINVAL;
3231 unsigned int i;
3232
3233 for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3234 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3235 snprintf(mode->info, sizeof(mode->info), "%s",
3236 i40e_rx_burst_infos[i].info);
3237 ret = 0;
3238 break;
3239 }
3240 }
3241
3242 return ret;
3243 }
3244
3245 void __rte_cold
i40e_set_tx_function_flag(struct rte_eth_dev * dev,struct i40e_tx_queue * txq)3246 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3247 {
3248 struct i40e_adapter *ad =
3249 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3250
3251 /* Use a simple Tx queue if possible (only fast free is allowed) */
3252 ad->tx_simple_allowed =
3253 (txq->offloads ==
3254 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3255 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3256 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3257 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3258
3259 if (ad->tx_vec_allowed)
3260 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3261 txq->queue_id);
3262 else if (ad->tx_simple_allowed)
3263 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3264 txq->queue_id);
3265 else
3266 PMD_INIT_LOG(DEBUG,
3267 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3268 txq->queue_id);
3269 }
3270
3271 static eth_tx_burst_t
i40e_get_latest_tx_vec(void)3272 i40e_get_latest_tx_vec(void)
3273 {
3274 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3275 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) &&
3276 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3277 return i40e_xmit_pkts_vec_avx2;
3278 #endif
3279 return i40e_xmit_pkts_vec;
3280 }
3281
3282 static eth_tx_burst_t
i40e_get_recommend_tx_vec(void)3283 i40e_get_recommend_tx_vec(void)
3284 {
3285 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3286 /*
3287 * since AVX frequency can be different to base frequency, limit
3288 * use of AVX2 version to later plaforms, not all those that could
3289 * theoretically run it.
3290 */
3291 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&
3292 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3293 return i40e_xmit_pkts_vec_avx2;
3294 #endif
3295 return i40e_xmit_pkts_vec;
3296 }
3297
3298 void __rte_cold
i40e_set_tx_function(struct rte_eth_dev * dev)3299 i40e_set_tx_function(struct rte_eth_dev *dev)
3300 {
3301 struct i40e_adapter *ad =
3302 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3303 int i;
3304
3305 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3306 if (ad->tx_vec_allowed) {
3307 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3308 struct i40e_tx_queue *txq =
3309 dev->data->tx_queues[i];
3310
3311 if (txq && i40e_txq_vec_setup(txq)) {
3312 ad->tx_vec_allowed = false;
3313 break;
3314 }
3315 }
3316 }
3317 }
3318
3319 if (ad->tx_simple_allowed) {
3320 if (ad->tx_vec_allowed &&
3321 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3322 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3323 if (ad->use_latest_vec)
3324 dev->tx_pkt_burst =
3325 i40e_get_latest_tx_vec();
3326 else
3327 dev->tx_pkt_burst =
3328 i40e_get_recommend_tx_vec();
3329 } else {
3330 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3331 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3332 }
3333 dev->tx_pkt_prepare = NULL;
3334 } else {
3335 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3336 dev->tx_pkt_burst = i40e_xmit_pkts;
3337 dev->tx_pkt_prepare = i40e_prep_pkts;
3338 }
3339 }
3340
3341 static const struct {
3342 eth_tx_burst_t pkt_burst;
3343 const char *info;
3344 } i40e_tx_burst_infos[] = {
3345 { i40e_xmit_pkts_simple, "Scalar Simple" },
3346 { i40e_xmit_pkts, "Scalar" },
3347 #ifdef RTE_ARCH_X86
3348 { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3349 { i40e_xmit_pkts_vec, "Vector SSE" },
3350 #elif defined(RTE_ARCH_ARM64)
3351 { i40e_xmit_pkts_vec, "Vector Neon" },
3352 #elif defined(RTE_ARCH_PPC_64)
3353 { i40e_xmit_pkts_vec, "Vector AltiVec" },
3354 #endif
3355 };
3356
3357 int
i40e_tx_burst_mode_get(struct rte_eth_dev * dev,__rte_unused uint16_t queue_id,struct rte_eth_burst_mode * mode)3358 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3359 struct rte_eth_burst_mode *mode)
3360 {
3361 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3362 int ret = -EINVAL;
3363 unsigned int i;
3364
3365 for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3366 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3367 snprintf(mode->info, sizeof(mode->info), "%s",
3368 i40e_tx_burst_infos[i].info);
3369 ret = 0;
3370 break;
3371 }
3372 }
3373
3374 return ret;
3375 }
3376
3377 void __rte_cold
i40e_set_default_ptype_table(struct rte_eth_dev * dev)3378 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3379 {
3380 struct i40e_adapter *ad =
3381 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3382 int i;
3383
3384 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3385 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3386 }
3387
3388 void __rte_cold
i40e_set_default_pctype_table(struct rte_eth_dev * dev)3389 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3390 {
3391 struct i40e_adapter *ad =
3392 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3393 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394 int i;
3395
3396 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3397 ad->pctypes_tbl[i] = 0ULL;
3398 ad->flow_types_mask = 0ULL;
3399 ad->pctypes_mask = 0ULL;
3400
3401 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3402 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3403 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3404 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3405 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3406 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3407 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3408 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3409 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3410 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3411 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3412 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3413 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3414 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3415 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3416 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3417 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3418 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3419 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3420 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3421 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3422 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3423
3424 if (hw->mac.type == I40E_MAC_X722 ||
3425 hw->mac.type == I40E_MAC_X722_VF) {
3426 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3427 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3428 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3429 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3430 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3431 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3432 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3433 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3434 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3435 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3436 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3437 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3438 }
3439
3440 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3441 if (ad->pctypes_tbl[i])
3442 ad->flow_types_mask |= (1ULL << i);
3443 ad->pctypes_mask |= ad->pctypes_tbl[i];
3444 }
3445 }
3446
3447 #ifndef RTE_LIBRTE_I40E_INC_VECTOR
3448 int
i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused * dev)3449 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3450 {
3451 return -1;
3452 }
3453
3454 uint16_t
i40e_recv_pkts_vec(void __rte_unused * rx_queue,struct rte_mbuf __rte_unused ** rx_pkts,uint16_t __rte_unused nb_pkts)3455 i40e_recv_pkts_vec(
3456 void __rte_unused *rx_queue,
3457 struct rte_mbuf __rte_unused **rx_pkts,
3458 uint16_t __rte_unused nb_pkts)
3459 {
3460 return 0;
3461 }
3462
3463 uint16_t
i40e_recv_scattered_pkts_vec(void __rte_unused * rx_queue,struct rte_mbuf __rte_unused ** rx_pkts,uint16_t __rte_unused nb_pkts)3464 i40e_recv_scattered_pkts_vec(
3465 void __rte_unused *rx_queue,
3466 struct rte_mbuf __rte_unused **rx_pkts,
3467 uint16_t __rte_unused nb_pkts)
3468 {
3469 return 0;
3470 }
3471
3472 int
i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused * rxq)3473 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3474 {
3475 return -1;
3476 }
3477
3478 int
i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused * txq)3479 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3480 {
3481 return -1;
3482 }
3483
3484 void
i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused * rxq)3485 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3486 {
3487 return;
3488 }
3489
3490 uint16_t
i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,struct rte_mbuf __rte_unused ** tx_pkts,uint16_t __rte_unused nb_pkts)3491 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3492 struct rte_mbuf __rte_unused **tx_pkts,
3493 uint16_t __rte_unused nb_pkts)
3494 {
3495 return 0;
3496 }
3497 #endif /* ifndef RTE_LIBRTE_I40E_INC_VECTOR */
3498
3499 #ifndef CC_AVX2_SUPPORT
3500 uint16_t
i40e_recv_pkts_vec_avx2(void __rte_unused * rx_queue,struct rte_mbuf __rte_unused ** rx_pkts,uint16_t __rte_unused nb_pkts)3501 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3502 struct rte_mbuf __rte_unused **rx_pkts,
3503 uint16_t __rte_unused nb_pkts)
3504 {
3505 return 0;
3506 }
3507
3508 uint16_t
i40e_recv_scattered_pkts_vec_avx2(void __rte_unused * rx_queue,struct rte_mbuf __rte_unused ** rx_pkts,uint16_t __rte_unused nb_pkts)3509 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3510 struct rte_mbuf __rte_unused **rx_pkts,
3511 uint16_t __rte_unused nb_pkts)
3512 {
3513 return 0;
3514 }
3515
3516 uint16_t
i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,struct rte_mbuf __rte_unused ** tx_pkts,uint16_t __rte_unused nb_pkts)3517 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3518 struct rte_mbuf __rte_unused **tx_pkts,
3519 uint16_t __rte_unused nb_pkts)
3520 {
3521 return 0;
3522 }
3523 #endif /* ifndef CC_AVX2_SUPPORT */
3524