1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 #ifndef _I40E_OSDEP_H_
6 #define _I40E_OSDEP_H_
7
8 #include <string.h>
9 #include <stdint.h>
10 #include <stdbool.h>
11 #include <stdio.h>
12 #include <stdarg.h>
13
14 #include <rte_common.h>
15 #include <rte_memcpy.h>
16 #include <rte_byteorder.h>
17 #include <rte_cycles.h>
18 #include <rte_spinlock.h>
19 #include <rte_log.h>
20 #include <rte_io.h>
21
22 #include "../i40e_logs.h"
23 #include "i40e_status.h"
24
25 #define INLINE inline
26 #define STATIC static
27
28 typedef uint8_t u8;
29 typedef int8_t s8;
30 typedef uint16_t u16;
31 typedef uint32_t u32;
32 typedef int32_t s32;
33 typedef uint64_t u64;
34
35 typedef enum i40e_status_code i40e_status;
36 #define __iomem
37 #define hw_dbg(hw, S, A...) do {} while (0)
38 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
39 #define lower_32_bits(n) ((u32)(n))
40 #define low_16_bits(x) ((x) & 0xFFFF)
41 #define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)
42
43 #ifndef ETH_ADDR_LEN
44 #define ETH_ADDR_LEN 6
45 #endif
46
47 #ifndef __le16
48 #define __le16 uint16_t
49 #endif
50 #ifndef __le32
51 #define __le32 uint32_t
52 #endif
53 #ifndef __le64
54 #define __le64 uint64_t
55 #endif
56 #ifndef __be16
57 #define __be16 uint16_t
58 #endif
59 #ifndef __be32
60 #define __be32 uint32_t
61 #endif
62 #ifndef __be64
63 #define __be64 uint64_t
64 #endif
65
66 #define FALSE 0
67 #define TRUE 1
68 #define false 0
69 #define true 1
70
71 /* Avoid macro redefinition warning on Windows */
72 #ifdef RTE_EXEC_ENV_WINDOWS
73 #ifdef min
74 #undef min
75 #endif
76 #ifdef max
77 #undef max
78 #endif
79 #endif
80 #define min(a,b) RTE_MIN(a,b)
81 #define max(a,b) RTE_MAX(a,b)
82
83 #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
84
85 #define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S)
86 #define DEBUGOUT1(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)
87
88 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
89 #define DEBUGOUT2 DEBUGOUT1
90 #define DEBUGOUT3 DEBUGOUT2
91 #define DEBUGOUT6 DEBUGOUT3
92 #define DEBUGOUT7 DEBUGOUT6
93
94 #define i40e_debug(h, m, s, ...) \
95 do { \
96 if (((m) & (h)->debug_mask)) \
97 PMD_DRV_LOG_RAW(DEBUG, "i40e %02x.%x " s, \
98 (h)->bus.device, (h)->bus.func, \
99 ##__VA_ARGS__); \
100 } while (0)
101
102 /* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl()
103 * are required for reading/writing below registers, as reading/writing it
104 * directly may not function correctly if the device is under heavy small
105 * packet traffic. Note that those interfaces are available from FVL5 and not
106 * suitable before the AdminQ is ready during initialization.
107 *
108 * I40E_PFQF_CTL_0
109 * I40E_PFQF_HENA
110 * I40E_PFQF_FDALLOC
111 * I40E_PFQF_HREGION
112 * I40E_PFLAN_QALLOC
113 * I40E_VPQF_CTL
114 * I40E_VFQF_HENA
115 * I40E_VFQF_HREGION
116 * I40E_VSIQF_CTL
117 * I40E_VSILAN_QBASE
118 * I40E_VSILAN_QTABLE
119 * I40E_VSIQF_TCREGION
120 * I40E_PFQF_HKEY
121 * I40E_VFQF_HKEY
122 * I40E_PRTQF_CTL_0
123 * I40E_GLFCOE_RCTL
124 * I40E_GLFCOE_RSOF
125 * I40E_GLQF_CTL
126 * I40E_GLQF_SWAP
127 * I40E_GLQF_HASH_MSK
128 * I40E_GLQF_HASH_INSET
129 * I40E_GLQF_HSYM
130 * I40E_GLQF_FC_MSK
131 * I40E_GLQF_FC_INSET
132 * I40E_GLQF_FD_MSK
133 * I40E_PRTQF_FD_INSET
134 * I40E_PRTQF_FD_FLXINSET
135 * I40E_PRTQF_FD_MSK
136 */
137
138 #define I40E_PCI_REG(reg) rte_read32(reg)
139 #define I40E_PCI_REG_ADDR(a, reg) \
140 ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
i40e_read_addr(volatile void * addr)141 static inline uint32_t i40e_read_addr(volatile void *addr)
142 {
143 return rte_le_to_cpu_32(I40E_PCI_REG(addr));
144 }
145
146 #define I40E_PCI_REG64(reg) rte_read64(reg)
147 #define I40E_PCI_REG64_ADDR(a, reg) \
148 ((volatile uint64_t *)((char *)(a)->hw_addr + (reg)))
i40e_read64_addr(volatile void * addr)149 static inline uint64_t i40e_read64_addr(volatile void *addr)
150 {
151 return rte_le_to_cpu_64(I40E_PCI_REG64(addr));
152 }
153
154 #define I40E_PCI_REG_WRITE(reg, value) \
155 rte_write32((rte_cpu_to_le_32(value)), reg)
156 #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \
157 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
158
159 #define I40E_PCI_REG_WC_WRITE(reg, value) \
160 rte_write32_wc((rte_cpu_to_le_32(value)), reg)
161 #define I40E_PCI_REG_WC_WRITE_RELAXED(reg, value) \
162 rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
163
164 #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)
165
166 #define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg)))
167 #define I40E_WRITE_REG(hw, reg, value) \
168 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value))
169
170 #define I40E_READ_REG64(hw, reg) i40e_read64_addr(I40E_PCI_REG64_ADDR((hw), (reg)))
171
172 #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg)))
173 #define wr32(a, reg, value) \
174 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value))
175 #define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)))
176
177 #define ARRAY_SIZE(arr) RTE_DIM(arr)
178
179 /* memory allocation tracking */
180 struct i40e_dma_mem {
181 void *va;
182 u64 pa;
183 u32 size;
184 const void *zone;
185 } __rte_packed;
186
187 #define i40e_allocate_dma_mem(h, m, unused, s, a) \
188 i40e_allocate_dma_mem_d(h, m, s, a)
189 #define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m)
190
191 struct i40e_virt_mem {
192 void *va;
193 u32 size;
194 } __rte_packed;
195
196 #define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s)
197 #define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m)
198
199 #define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
200 #define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
201 #define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
202 #define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
203 #define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
204 #define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
205
206 #define cpu_to_le16(o) rte_cpu_to_le_16(o)
207 #define cpu_to_le32(s) rte_cpu_to_le_32(s)
208 #define cpu_to_le64(h) rte_cpu_to_le_64(h)
209 #define le16_to_cpu(a) rte_le_to_cpu_16(a)
210 #define le32_to_cpu(c) rte_le_to_cpu_32(c)
211 #define le64_to_cpu(k) rte_le_to_cpu_64(k)
212
213 /* SW spinlock */
214 struct i40e_spinlock {
215 rte_spinlock_t spinlock;
216 };
217
218 #define i40e_init_spinlock(_sp) i40e_init_spinlock_d(_sp)
219 #define i40e_acquire_spinlock(_sp) i40e_acquire_spinlock_d(_sp)
220 #define i40e_release_spinlock(_sp) i40e_release_spinlock_d(_sp)
221 #define i40e_destroy_spinlock(_sp) i40e_destroy_spinlock_d(_sp)
222
223 #define I40E_NTOHS(a) rte_be_to_cpu_16(a)
224 #define I40E_NTOHL(a) rte_be_to_cpu_32(a)
225 #define I40E_HTONS(a) rte_cpu_to_be_16(a)
226 #define I40E_HTONL(a) rte_cpu_to_be_32(a)
227
228 #define i40e_memset(a, b, c, d) memset((a), (b), (c))
229 #define i40e_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
230
231 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
232 #define DELAY(x) rte_delay_us_sleep(x)
233 #define i40e_usec_delay(x) DELAY(x)
234 #define i40e_msec_delay(x) DELAY(1000 * (x))
235 #define udelay(x) DELAY(x)
236 #define msleep(x) DELAY(1000*(x))
237 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
238
239 #endif /* _I40E_OSDEP_H_ */
240