1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_INTR_H_ 6 #define _HNS3_INTR_H_ 7 8 #include <stdint.h> 9 10 #include "hns3_ethdev.h" 11 12 #define HNS3_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF 13 #define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF 14 #define HNS3_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF 15 #define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF 16 #define HNS3_PPP_PF_ERR_INT_EN 0x0003 17 #define HNS3_PPP_PF_ERR_INT_EN_MASK 0x0003 18 #define HNS3_PPP_MPF_ECC_ERR_INT2_EN 0x003F 19 #define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F 20 #define HNS3_PPP_MPF_ECC_ERR_INT3_EN 0x003F 21 #define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F 22 23 #define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF 24 #define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF 25 26 #define HNS3_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000 27 #define HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000 28 #define HNS3_IMP_ITCM4_ECC_ERR_INT_EN 0x300 29 #define HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300 30 #define HNS3_IMP_RD_POISON_ERR_INT_EN 0x0100 31 #define HNS3_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100 32 33 #define HNS3_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF 34 #define HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF 35 36 #define HNS3_TQP_ECC_ERR_INT_EN 0x0FFF 37 #define HNS3_TQP_ECC_ERR_INT_EN_MASK 0x0FFF 38 39 #define HNS3_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000 40 #define HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000 41 42 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0) 43 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0) 44 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0) 45 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0) 46 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF 47 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF 48 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN2 0xB 49 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB 50 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0) 51 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16) 52 #define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0) 53 #define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0) 54 55 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0) 56 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) 57 #define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0) 58 #define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) 59 #define HNS3_SSU_BIT32_ECC_ERR_INT_EN 0x0101 60 #define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101 61 #define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0) 62 #define HNS3_SSU_COMMON_INT_EN_MASK GENMASK(9, 0) 63 #define HNS3_SSU_PORT_BASED_ERR_INT_EN 0x0BFF 64 #define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000 65 #define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0) 66 #define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0) 67 68 #define HNS3_IGU_ERR_INT_ENABLE 0x0000066F 69 #define HNS3_IGU_ERR_INT_DISABLE 0x00000660 70 #define HNS3_IGU_ERR_INT_EN_MASK 0x000F 71 #define HNS3_IGU_TNL_ERR_INT_EN 0x0002AABF 72 #define HNS3_IGU_TNL_ERR_INT_EN_MASK 0x003F 73 74 #define HNS3_NCSI_ERR_INT_EN 0x3 75 76 #define HNS3_TM_SCH_ECC_ERR_INT_EN 0x3 77 #define HNS3_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF 78 79 #define HNS3_RESET_PROCESS_MS 200 80 81 struct hns3_hw_blk { 82 const char *name; 83 int (*enable_err_intr)(struct hns3_adapter *hns, bool en); 84 }; 85 86 struct hns3_hw_error { 87 uint32_t int_msk; 88 const char *msg; 89 enum hns3_reset_level reset_level; 90 }; 91 92 struct hns3_hw_error_desc { 93 uint8_t desc_offset; 94 uint8_t data_offset; 95 const char *msg; 96 const struct hns3_hw_error *hw_err; 97 }; 98 99 int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state); 100 void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels); 101 void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels); 102 103 void hns3_intr_unregister(const struct rte_intr_handle *hdl, 104 rte_intr_callback_fn cb_fn, void *cb_arg); 105 void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable); 106 int hns3_reset_init(struct hns3_hw *hw); 107 void hns3_wait_callback(void *param); 108 void hns3_schedule_reset(struct hns3_adapter *hns); 109 void hns3_schedule_delayed_reset(struct hns3_adapter *hns); 110 int hns3_reset_req_hw_reset(struct hns3_adapter *hns); 111 int hns3_reset_process(struct hns3_adapter *hns, 112 enum hns3_reset_level reset_level); 113 void hns3_reset_abort(struct hns3_adapter *hns); 114 115 #endif /* _HNS3_INTR_H_ */ 116