1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
3 */
4
5 #include <rte_bus_pci.h>
6 #include <rte_common.h>
7 #include <rte_cycles.h>
8 #include <rte_vxlan.h>
9 #include <rte_ethdev_driver.h>
10 #include <rte_io.h>
11 #include <rte_net.h>
12 #include <rte_malloc.h>
13 #if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT)
14 #include <rte_cpuflags.h>
15 #endif
16
17 #include "hns3_ethdev.h"
18 #include "hns3_rxtx.h"
19 #include "hns3_regs.h"
20 #include "hns3_logs.h"
21
22 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
23 #define HNS3_RX_RING_PREFETCTH_MASK 3
24
25 static void
hns3_rx_queue_release_mbufs(struct hns3_rx_queue * rxq)26 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
27 {
28 uint16_t i;
29
30 /* Note: Fake rx queue will not enter here */
31 if (rxq->sw_ring == NULL)
32 return;
33
34 if (rxq->rx_rearm_nb == 0) {
35 for (i = 0; i < rxq->nb_rx_desc; i++) {
36 if (rxq->sw_ring[i].mbuf != NULL) {
37 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
38 rxq->sw_ring[i].mbuf = NULL;
39 }
40 }
41 } else {
42 for (i = rxq->next_to_use;
43 i != rxq->rx_rearm_start;
44 i = (i + 1) % rxq->nb_rx_desc) {
45 if (rxq->sw_ring[i].mbuf != NULL) {
46 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
47 rxq->sw_ring[i].mbuf = NULL;
48 }
49 }
50 }
51
52 for (i = 0; i < rxq->bulk_mbuf_num; i++)
53 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
54 rxq->bulk_mbuf_num = 0;
55
56 if (rxq->pkt_first_seg) {
57 rte_pktmbuf_free(rxq->pkt_first_seg);
58 rxq->pkt_first_seg = NULL;
59 }
60 }
61
62 static void
hns3_tx_queue_release_mbufs(struct hns3_tx_queue * txq)63 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
64 {
65 uint16_t i;
66
67 /* Note: Fake tx queue will not enter here */
68 if (txq->sw_ring) {
69 for (i = 0; i < txq->nb_tx_desc; i++) {
70 if (txq->sw_ring[i].mbuf) {
71 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
72 txq->sw_ring[i].mbuf = NULL;
73 }
74 }
75 }
76 }
77
78 static void
hns3_rx_queue_release(void * queue)79 hns3_rx_queue_release(void *queue)
80 {
81 struct hns3_rx_queue *rxq = queue;
82 if (rxq) {
83 hns3_rx_queue_release_mbufs(rxq);
84 if (rxq->mz)
85 rte_memzone_free(rxq->mz);
86 if (rxq->sw_ring)
87 rte_free(rxq->sw_ring);
88 rte_free(rxq);
89 }
90 }
91
92 static void
hns3_tx_queue_release(void * queue)93 hns3_tx_queue_release(void *queue)
94 {
95 struct hns3_tx_queue *txq = queue;
96 if (txq) {
97 hns3_tx_queue_release_mbufs(txq);
98 if (txq->mz)
99 rte_memzone_free(txq->mz);
100 if (txq->sw_ring)
101 rte_free(txq->sw_ring);
102 if (txq->free)
103 rte_free(txq->free);
104 rte_free(txq);
105 }
106 }
107
108 void
hns3_dev_rx_queue_release(void * queue)109 hns3_dev_rx_queue_release(void *queue)
110 {
111 struct hns3_rx_queue *rxq = queue;
112 struct hns3_adapter *hns;
113
114 if (rxq == NULL)
115 return;
116
117 hns = rxq->hns;
118 rte_spinlock_lock(&hns->hw.lock);
119 hns3_rx_queue_release(queue);
120 rte_spinlock_unlock(&hns->hw.lock);
121 }
122
123 void
hns3_dev_tx_queue_release(void * queue)124 hns3_dev_tx_queue_release(void *queue)
125 {
126 struct hns3_tx_queue *txq = queue;
127 struct hns3_adapter *hns;
128
129 if (txq == NULL)
130 return;
131
132 hns = txq->hns;
133 rte_spinlock_lock(&hns->hw.lock);
134 hns3_tx_queue_release(queue);
135 rte_spinlock_unlock(&hns->hw.lock);
136 }
137
138 static void
hns3_fake_rx_queue_release(struct hns3_rx_queue * queue)139 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
140 {
141 struct hns3_rx_queue *rxq = queue;
142 struct hns3_adapter *hns;
143 struct hns3_hw *hw;
144 uint16_t idx;
145
146 if (rxq == NULL)
147 return;
148
149 hns = rxq->hns;
150 hw = &hns->hw;
151 idx = rxq->queue_id;
152 if (hw->fkq_data.rx_queues[idx]) {
153 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
154 hw->fkq_data.rx_queues[idx] = NULL;
155 }
156
157 /* free fake rx queue arrays */
158 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
159 hw->fkq_data.nb_fake_rx_queues = 0;
160 rte_free(hw->fkq_data.rx_queues);
161 hw->fkq_data.rx_queues = NULL;
162 }
163 }
164
165 static void
hns3_fake_tx_queue_release(struct hns3_tx_queue * queue)166 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
167 {
168 struct hns3_tx_queue *txq = queue;
169 struct hns3_adapter *hns;
170 struct hns3_hw *hw;
171 uint16_t idx;
172
173 if (txq == NULL)
174 return;
175
176 hns = txq->hns;
177 hw = &hns->hw;
178 idx = txq->queue_id;
179 if (hw->fkq_data.tx_queues[idx]) {
180 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
181 hw->fkq_data.tx_queues[idx] = NULL;
182 }
183
184 /* free fake tx queue arrays */
185 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
186 hw->fkq_data.nb_fake_tx_queues = 0;
187 rte_free(hw->fkq_data.tx_queues);
188 hw->fkq_data.tx_queues = NULL;
189 }
190 }
191
192 static void
hns3_free_rx_queues(struct rte_eth_dev * dev)193 hns3_free_rx_queues(struct rte_eth_dev *dev)
194 {
195 struct hns3_adapter *hns = dev->data->dev_private;
196 struct hns3_fake_queue_data *fkq_data;
197 struct hns3_hw *hw = &hns->hw;
198 uint16_t nb_rx_q;
199 uint16_t i;
200
201 nb_rx_q = hw->data->nb_rx_queues;
202 for (i = 0; i < nb_rx_q; i++) {
203 if (dev->data->rx_queues[i]) {
204 hns3_rx_queue_release(dev->data->rx_queues[i]);
205 dev->data->rx_queues[i] = NULL;
206 }
207 }
208
209 /* Free fake Rx queues */
210 fkq_data = &hw->fkq_data;
211 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
212 if (fkq_data->rx_queues[i])
213 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
214 }
215 }
216
217 static void
hns3_free_tx_queues(struct rte_eth_dev * dev)218 hns3_free_tx_queues(struct rte_eth_dev *dev)
219 {
220 struct hns3_adapter *hns = dev->data->dev_private;
221 struct hns3_fake_queue_data *fkq_data;
222 struct hns3_hw *hw = &hns->hw;
223 uint16_t nb_tx_q;
224 uint16_t i;
225
226 nb_tx_q = hw->data->nb_tx_queues;
227 for (i = 0; i < nb_tx_q; i++) {
228 if (dev->data->tx_queues[i]) {
229 hns3_tx_queue_release(dev->data->tx_queues[i]);
230 dev->data->tx_queues[i] = NULL;
231 }
232 }
233
234 /* Free fake Tx queues */
235 fkq_data = &hw->fkq_data;
236 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
237 if (fkq_data->tx_queues[i])
238 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
239 }
240 }
241
242 void
hns3_free_all_queues(struct rte_eth_dev * dev)243 hns3_free_all_queues(struct rte_eth_dev *dev)
244 {
245 hns3_free_rx_queues(dev);
246 hns3_free_tx_queues(dev);
247 }
248
249 static int
hns3_alloc_rx_queue_mbufs(struct hns3_hw * hw,struct hns3_rx_queue * rxq)250 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
251 {
252 struct rte_mbuf *mbuf;
253 uint64_t dma_addr;
254 uint16_t i;
255
256 for (i = 0; i < rxq->nb_rx_desc; i++) {
257 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
258 if (unlikely(mbuf == NULL)) {
259 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!",
260 i);
261 hns3_rx_queue_release_mbufs(rxq);
262 return -ENOMEM;
263 }
264
265 rte_mbuf_refcnt_set(mbuf, 1);
266 mbuf->next = NULL;
267 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
268 mbuf->nb_segs = 1;
269 mbuf->port = rxq->port_id;
270
271 rxq->sw_ring[i].mbuf = mbuf;
272 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
273 rxq->rx_ring[i].addr = dma_addr;
274 rxq->rx_ring[i].rx.bd_base_info = 0;
275 }
276
277 return 0;
278 }
279
280 static int
hns3_buf_size2type(uint32_t buf_size)281 hns3_buf_size2type(uint32_t buf_size)
282 {
283 int bd_size_type;
284
285 switch (buf_size) {
286 case 512:
287 bd_size_type = HNS3_BD_SIZE_512_TYPE;
288 break;
289 case 1024:
290 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
291 break;
292 case 4096:
293 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
294 break;
295 default:
296 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
297 }
298
299 return bd_size_type;
300 }
301
302 static void
hns3_init_rx_queue_hw(struct hns3_rx_queue * rxq)303 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
304 {
305 uint32_t rx_buf_len = rxq->rx_buf_len;
306 uint64_t dma_addr = rxq->rx_ring_phys_addr;
307
308 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
309 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
310 (uint32_t)((dma_addr >> 31) >> 1));
311
312 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
313 hns3_buf_size2type(rx_buf_len));
314 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
315 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
316 }
317
318 static void
hns3_init_tx_queue_hw(struct hns3_tx_queue * txq)319 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
320 {
321 uint64_t dma_addr = txq->tx_ring_phys_addr;
322
323 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
324 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
325 (uint32_t)((dma_addr >> 31) >> 1));
326
327 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
328 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
329 }
330
331 void
hns3_update_all_queues_pvid_proc_en(struct hns3_hw * hw)332 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
333 {
334 uint16_t nb_rx_q = hw->data->nb_rx_queues;
335 uint16_t nb_tx_q = hw->data->nb_tx_queues;
336 struct hns3_rx_queue *rxq;
337 struct hns3_tx_queue *txq;
338 bool pvid_en;
339 int i;
340
341 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
342 for (i = 0; i < hw->cfg_max_queues; i++) {
343 if (i < nb_rx_q) {
344 rxq = hw->data->rx_queues[i];
345 if (rxq != NULL)
346 rxq->pvid_sw_discard_en = pvid_en;
347 }
348 if (i < nb_tx_q) {
349 txq = hw->data->tx_queues[i];
350 if (txq != NULL)
351 txq->pvid_sw_shift_en = pvid_en;
352 }
353 }
354 }
355
356 static void
hns3_stop_unused_queue(void * tqp_base,enum hns3_ring_type queue_type)357 hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type)
358 {
359 uint32_t reg_offset;
360 uint32_t reg;
361
362 reg_offset = queue_type == HNS3_RING_TYPE_TX ?
363 HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG;
364 reg = hns3_read_reg(tqp_base, reg_offset);
365 reg &= ~BIT(HNS3_RING_EN_B);
366 hns3_write_reg(tqp_base, reg_offset, reg);
367 }
368
369 void
hns3_enable_all_queues(struct hns3_hw * hw,bool en)370 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
371 {
372 uint16_t nb_rx_q = hw->data->nb_rx_queues;
373 uint16_t nb_tx_q = hw->data->nb_tx_queues;
374 struct hns3_rx_queue *rxq;
375 struct hns3_tx_queue *txq;
376 uint32_t rcb_reg;
377 void *tqp_base;
378 int i;
379
380 for (i = 0; i < hw->cfg_max_queues; i++) {
381 if (hns3_dev_indep_txrx_supported(hw)) {
382 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
383 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;
384
385 tqp_base = (void *)((char *)hw->io_base +
386 hns3_get_tqp_reg_offset(i));
387 /*
388 * If queue struct is not initialized, it means the
389 * related HW ring has not been initialized yet.
390 * So, these queues should be disabled before enable
391 * the tqps to avoid a HW exception since the queues
392 * are enabled by default.
393 */
394 if (rxq == NULL)
395 hns3_stop_unused_queue(tqp_base,
396 HNS3_RING_TYPE_RX);
397 if (txq == NULL)
398 hns3_stop_unused_queue(tqp_base,
399 HNS3_RING_TYPE_TX);
400 } else {
401 rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
402 hw->fkq_data.rx_queues[i - nb_rx_q];
403
404 tqp_base = rxq->io_base;
405 }
406 /*
407 * This is the master switch that used to control the enabling
408 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
409 * the same register
410 */
411 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
412 if (en)
413 rcb_reg |= BIT(HNS3_RING_EN_B);
414 else
415 rcb_reg &= ~BIT(HNS3_RING_EN_B);
416 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
417 }
418 }
419
420 static void
hns3_enable_txq(struct hns3_tx_queue * txq,bool en)421 hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
422 {
423 struct hns3_hw *hw = &txq->hns->hw;
424 uint32_t reg;
425
426 if (hns3_dev_indep_txrx_supported(hw)) {
427 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
428 if (en)
429 reg |= BIT(HNS3_RING_EN_B);
430 else
431 reg &= ~BIT(HNS3_RING_EN_B);
432 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
433 }
434 txq->enabled = en;
435 }
436
437 static void
hns3_enable_rxq(struct hns3_rx_queue * rxq,bool en)438 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
439 {
440 struct hns3_hw *hw = &rxq->hns->hw;
441 uint32_t reg;
442
443 if (hns3_dev_indep_txrx_supported(hw)) {
444 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
445 if (en)
446 reg |= BIT(HNS3_RING_EN_B);
447 else
448 reg &= ~BIT(HNS3_RING_EN_B);
449 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
450 }
451 rxq->enabled = en;
452 }
453
454 int
hns3_start_all_txqs(struct rte_eth_dev * dev)455 hns3_start_all_txqs(struct rte_eth_dev *dev)
456 {
457 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
458 struct hns3_tx_queue *txq;
459 uint16_t i, j;
460
461 for (i = 0; i < dev->data->nb_tx_queues; i++) {
462 txq = hw->data->tx_queues[i];
463 if (!txq) {
464 hns3_err(hw, "Tx queue %u not available or setup.", i);
465 goto start_txqs_fail;
466 }
467 /*
468 * Tx queue is enabled by default. Therefore, the Tx queues
469 * needs to be disabled when deferred_start is set. There is
470 * another master switch used to control the enabling of a pair
471 * of Tx and Rx queues. And the master switch is disabled by
472 * default.
473 */
474 if (txq->tx_deferred_start)
475 hns3_enable_txq(txq, false);
476 else
477 hns3_enable_txq(txq, true);
478 }
479 return 0;
480
481 start_txqs_fail:
482 for (j = 0; j < i; j++) {
483 txq = hw->data->tx_queues[j];
484 hns3_enable_txq(txq, false);
485 }
486 return -EINVAL;
487 }
488
489 int
hns3_start_all_rxqs(struct rte_eth_dev * dev)490 hns3_start_all_rxqs(struct rte_eth_dev *dev)
491 {
492 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
493 struct hns3_rx_queue *rxq;
494 uint16_t i, j;
495
496 for (i = 0; i < dev->data->nb_rx_queues; i++) {
497 rxq = hw->data->rx_queues[i];
498 if (!rxq) {
499 hns3_err(hw, "Rx queue %u not available or setup.", i);
500 goto start_rxqs_fail;
501 }
502 /*
503 * Rx queue is enabled by default. Therefore, the Rx queues
504 * needs to be disabled when deferred_start is set. There is
505 * another master switch used to control the enabling of a pair
506 * of Tx and Rx queues. And the master switch is disabled by
507 * default.
508 */
509 if (rxq->rx_deferred_start)
510 hns3_enable_rxq(rxq, false);
511 else
512 hns3_enable_rxq(rxq, true);
513 }
514 return 0;
515
516 start_rxqs_fail:
517 for (j = 0; j < i; j++) {
518 rxq = hw->data->rx_queues[j];
519 hns3_enable_rxq(rxq, false);
520 }
521 return -EINVAL;
522 }
523
524 void
hns3_restore_tqp_enable_state(struct hns3_hw * hw)525 hns3_restore_tqp_enable_state(struct hns3_hw *hw)
526 {
527 struct hns3_rx_queue *rxq;
528 struct hns3_tx_queue *txq;
529 uint16_t i;
530
531 for (i = 0; i < hw->data->nb_rx_queues; i++) {
532 rxq = hw->data->rx_queues[i];
533 if (rxq != NULL)
534 hns3_enable_rxq(rxq, rxq->enabled);
535 }
536
537 for (i = 0; i < hw->data->nb_tx_queues; i++) {
538 txq = hw->data->tx_queues[i];
539 if (txq != NULL)
540 hns3_enable_txq(txq, txq->enabled);
541 }
542 }
543
544 void
hns3_stop_all_txqs(struct rte_eth_dev * dev)545 hns3_stop_all_txqs(struct rte_eth_dev *dev)
546 {
547 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
548 struct hns3_tx_queue *txq;
549 uint16_t i;
550
551 for (i = 0; i < dev->data->nb_tx_queues; i++) {
552 txq = hw->data->tx_queues[i];
553 if (!txq)
554 continue;
555 hns3_enable_txq(txq, false);
556 }
557 }
558
559 static int
hns3_tqp_enable(struct hns3_hw * hw,uint16_t queue_id,bool enable)560 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
561 {
562 struct hns3_cfg_com_tqp_queue_cmd *req;
563 struct hns3_cmd_desc desc;
564 int ret;
565
566 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
567
568 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
569 req->tqp_id = rte_cpu_to_le_16(queue_id);
570 req->stream_id = 0;
571 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
572
573 ret = hns3_cmd_send(hw, &desc, 1);
574 if (ret)
575 hns3_err(hw, "TQP enable fail, ret = %d", ret);
576
577 return ret;
578 }
579
580 static int
hns3_send_reset_tqp_cmd(struct hns3_hw * hw,uint16_t queue_id,bool enable)581 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
582 {
583 struct hns3_reset_tqp_queue_cmd *req;
584 struct hns3_cmd_desc desc;
585 int ret;
586
587 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
588
589 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
590 req->tqp_id = rte_cpu_to_le_16(queue_id);
591 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
592 ret = hns3_cmd_send(hw, &desc, 1);
593 if (ret)
594 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
595 "ret = %d", queue_id, ret);
596
597 return ret;
598 }
599
600 static int
hns3_get_tqp_reset_status(struct hns3_hw * hw,uint16_t queue_id,uint8_t * reset_status)601 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
602 uint8_t *reset_status)
603 {
604 struct hns3_reset_tqp_queue_cmd *req;
605 struct hns3_cmd_desc desc;
606 int ret;
607
608 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
609
610 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
611 req->tqp_id = rte_cpu_to_le_16(queue_id);
612
613 ret = hns3_cmd_send(hw, &desc, 1);
614 if (ret) {
615 hns3_err(hw, "get tqp reset status error, queue_id = %u, "
616 "ret = %d.", queue_id, ret);
617 return ret;
618 }
619 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
620 return ret;
621 }
622
623 static int
hns3pf_reset_tqp(struct hns3_hw * hw,uint16_t queue_id)624 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
625 {
626 #define HNS3_TQP_RESET_TRY_MS 200
627 uint8_t reset_status;
628 uint64_t end;
629 int ret;
630
631 ret = hns3_tqp_enable(hw, queue_id, false);
632 if (ret)
633 return ret;
634
635 /*
636 * In current version VF is not supported when PF is driven by DPDK
637 * driver, all task queue pairs are mapped to PF function, so PF's queue
638 * id is equals to the global queue id in PF range.
639 */
640 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
641 if (ret) {
642 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
643 return ret;
644 }
645 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
646 do {
647 /* Wait for tqp hw reset */
648 rte_delay_ms(HNS3_POLL_RESPONE_MS);
649 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
650 if (ret)
651 goto tqp_reset_fail;
652
653 if (reset_status)
654 break;
655 } while (get_timeofday_ms() < end);
656
657 if (!reset_status) {
658 ret = -ETIMEDOUT;
659 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
660 queue_id, ret);
661 goto tqp_reset_fail;
662 }
663
664 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
665 if (ret)
666 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
667
668 return ret;
669
670 tqp_reset_fail:
671 hns3_send_reset_tqp_cmd(hw, queue_id, false);
672 return ret;
673 }
674
675 static int
hns3vf_reset_tqp(struct hns3_hw * hw,uint16_t queue_id)676 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
677 {
678 uint8_t msg_data[2];
679 int ret;
680
681 /* Disable VF's queue before send queue reset msg to PF */
682 ret = hns3_tqp_enable(hw, queue_id, false);
683 if (ret)
684 return ret;
685
686 memcpy(msg_data, &queue_id, sizeof(uint16_t));
687
688 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
689 sizeof(msg_data), true, NULL, 0);
690 if (ret)
691 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
692 queue_id, ret);
693 return ret;
694 }
695
696 static int
hns3_reset_tqp(struct hns3_adapter * hns,uint16_t queue_id)697 hns3_reset_tqp(struct hns3_adapter *hns, uint16_t queue_id)
698 {
699 struct hns3_hw *hw = &hns->hw;
700
701 if (hns->is_vf)
702 return hns3vf_reset_tqp(hw, queue_id);
703 else
704 return hns3pf_reset_tqp(hw, queue_id);
705 }
706
707 int
hns3_reset_all_tqps(struct hns3_adapter * hns)708 hns3_reset_all_tqps(struct hns3_adapter *hns)
709 {
710 struct hns3_hw *hw = &hns->hw;
711 int ret, i;
712
713 for (i = 0; i < hw->cfg_max_queues; i++) {
714 ret = hns3_reset_tqp(hns, i);
715 if (ret) {
716 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
717 return ret;
718 }
719 }
720 return 0;
721 }
722
723 static int
hns3_send_reset_queue_cmd(struct hns3_hw * hw,uint16_t queue_id,enum hns3_ring_type queue_type,bool enable)724 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
725 enum hns3_ring_type queue_type, bool enable)
726 {
727 struct hns3_reset_tqp_queue_cmd *req;
728 struct hns3_cmd_desc desc;
729 int queue_direction;
730 int ret;
731
732 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);
733
734 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
735 req->tqp_id = rte_cpu_to_le_16(queue_id);
736 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
737 req->queue_direction = rte_cpu_to_le_16(queue_direction);
738 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
739
740 ret = hns3_cmd_send(hw, &desc, 1);
741 if (ret)
742 hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
743 "queue_type = %s, ret = %d.", queue_id,
744 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
745 return ret;
746 }
747
748 static int
hns3_get_queue_reset_status(struct hns3_hw * hw,uint16_t queue_id,enum hns3_ring_type queue_type,uint8_t * reset_status)749 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
750 enum hns3_ring_type queue_type,
751 uint8_t *reset_status)
752 {
753 struct hns3_reset_tqp_queue_cmd *req;
754 struct hns3_cmd_desc desc;
755 int queue_direction;
756 int ret;
757
758 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);
759
760 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
761 req->tqp_id = rte_cpu_to_le_16(queue_id);
762 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
763 req->queue_direction = rte_cpu_to_le_16(queue_direction);
764
765 ret = hns3_cmd_send(hw, &desc, 1);
766 if (ret) {
767 hns3_err(hw, "get queue reset status error, queue_id = %u "
768 "queue_type = %s, ret = %d.", queue_id,
769 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
770 return ret;
771 }
772
773 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
774 return ret;
775 }
776
777 static int
hns3_reset_queue(struct hns3_hw * hw,uint16_t queue_id,enum hns3_ring_type queue_type)778 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
779 enum hns3_ring_type queue_type)
780 {
781 #define HNS3_QUEUE_RESET_TRY_MS 200
782 struct hns3_tx_queue *txq;
783 struct hns3_rx_queue *rxq;
784 uint32_t reset_wait_times;
785 uint32_t max_wait_times;
786 uint8_t reset_status;
787 int ret;
788
789 if (queue_type == HNS3_RING_TYPE_TX) {
790 txq = hw->data->tx_queues[queue_id];
791 hns3_enable_txq(txq, false);
792 } else {
793 rxq = hw->data->rx_queues[queue_id];
794 hns3_enable_rxq(rxq, false);
795 }
796
797 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
798 if (ret) {
799 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
800 return ret;
801 }
802
803 reset_wait_times = 0;
804 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
805 while (reset_wait_times < max_wait_times) {
806 /* Wait for queue hw reset */
807 rte_delay_ms(HNS3_POLL_RESPONE_MS);
808 ret = hns3_get_queue_reset_status(hw, queue_id,
809 queue_type, &reset_status);
810 if (ret)
811 goto queue_reset_fail;
812
813 if (reset_status)
814 break;
815 reset_wait_times++;
816 }
817
818 if (!reset_status) {
819 hns3_err(hw, "reset queue timeout, queue_id = %u, "
820 "queue_type = %s", queue_id,
821 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
822 ret = -ETIMEDOUT;
823 goto queue_reset_fail;
824 }
825
826 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
827 if (ret)
828 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);
829
830 return ret;
831
832 queue_reset_fail:
833 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
834 return ret;
835 }
836
837
838 void
hns3_set_queue_intr_gl(struct hns3_hw * hw,uint16_t queue_id,uint8_t gl_idx,uint16_t gl_value)839 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
840 uint8_t gl_idx, uint16_t gl_value)
841 {
842 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
843 HNS3_TQP_INTR_GL1_REG,
844 HNS3_TQP_INTR_GL2_REG};
845 uint32_t addr, value;
846
847 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
848 return;
849
850 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
851 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
852 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
853 else
854 value = HNS3_GL_USEC_TO_REG(gl_value);
855
856 hns3_write_dev(hw, addr, value);
857 }
858
859 void
hns3_set_queue_intr_rl(struct hns3_hw * hw,uint16_t queue_id,uint16_t rl_value)860 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
861 {
862 uint32_t addr, value;
863
864 if (rl_value > HNS3_TQP_INTR_RL_MAX)
865 return;
866
867 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
868 value = HNS3_RL_USEC_TO_REG(rl_value);
869 if (value > 0)
870 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
871
872 hns3_write_dev(hw, addr, value);
873 }
874
875 void
hns3_set_queue_intr_ql(struct hns3_hw * hw,uint16_t queue_id,uint16_t ql_value)876 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
877 {
878 uint32_t addr;
879
880 /*
881 * int_ql_max == 0 means the hardware does not support QL,
882 * QL regs config is not permitted if QL is not supported,
883 * here just return.
884 */
885 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)
886 return;
887
888 addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
889 hns3_write_dev(hw, addr, ql_value);
890
891 addr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
892 hns3_write_dev(hw, addr, ql_value);
893 }
894
895 static void
hns3_queue_intr_enable(struct hns3_hw * hw,uint16_t queue_id,bool en)896 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
897 {
898 uint32_t addr, value;
899
900 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
901 value = en ? 1 : 0;
902
903 hns3_write_dev(hw, addr, value);
904 }
905
906 /*
907 * Enable all rx queue interrupt when in interrupt rx mode.
908 * This api was called before enable queue rx&tx (in normal start or reset
909 * recover scenes), used to fix hardware rx queue interrupt enable was clear
910 * when FLR.
911 */
912 void
hns3_dev_all_rx_queue_intr_enable(struct hns3_hw * hw,bool en)913 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
914 {
915 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
916 uint16_t nb_rx_q = hw->data->nb_rx_queues;
917 int i;
918
919 if (dev->data->dev_conf.intr_conf.rxq == 0)
920 return;
921
922 for (i = 0; i < nb_rx_q; i++)
923 hns3_queue_intr_enable(hw, i, en);
924 }
925
926 int
hns3_dev_rx_queue_intr_enable(struct rte_eth_dev * dev,uint16_t queue_id)927 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
928 {
929 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
930 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
931 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
932
933 if (dev->data->dev_conf.intr_conf.rxq == 0)
934 return -ENOTSUP;
935
936 hns3_queue_intr_enable(hw, queue_id, true);
937
938 return rte_intr_ack(intr_handle);
939 }
940
941 int
hns3_dev_rx_queue_intr_disable(struct rte_eth_dev * dev,uint16_t queue_id)942 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
943 {
944 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
945
946 if (dev->data->dev_conf.intr_conf.rxq == 0)
947 return -ENOTSUP;
948
949 hns3_queue_intr_enable(hw, queue_id, false);
950
951 return 0;
952 }
953
954 static int
hns3_init_rxq(struct hns3_adapter * hns,uint16_t idx)955 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
956 {
957 struct hns3_hw *hw = &hns->hw;
958 struct hns3_rx_queue *rxq;
959 int ret;
960
961 PMD_INIT_FUNC_TRACE();
962
963 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
964 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
965 if (ret) {
966 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
967 idx, ret);
968 return ret;
969 }
970
971 rxq->next_to_use = 0;
972 rxq->rx_rearm_start = 0;
973 rxq->rx_free_hold = 0;
974 rxq->rx_rearm_nb = 0;
975 rxq->pkt_first_seg = NULL;
976 rxq->pkt_last_seg = NULL;
977 hns3_init_rx_queue_hw(rxq);
978 hns3_rxq_vec_setup(rxq);
979
980 return 0;
981 }
982
983 static void
hns3_init_fake_rxq(struct hns3_adapter * hns,uint16_t idx)984 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
985 {
986 struct hns3_hw *hw = &hns->hw;
987 struct hns3_rx_queue *rxq;
988
989 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
990 rxq->next_to_use = 0;
991 rxq->rx_free_hold = 0;
992 rxq->rx_rearm_start = 0;
993 rxq->rx_rearm_nb = 0;
994 hns3_init_rx_queue_hw(rxq);
995 }
996
997 static void
hns3_init_txq(struct hns3_tx_queue * txq)998 hns3_init_txq(struct hns3_tx_queue *txq)
999 {
1000 struct hns3_desc *desc;
1001 int i;
1002
1003 /* Clear tx bd */
1004 desc = txq->tx_ring;
1005 for (i = 0; i < txq->nb_tx_desc; i++) {
1006 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1007 desc++;
1008 }
1009
1010 txq->next_to_use = 0;
1011 txq->next_to_clean = 0;
1012 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1013 hns3_init_tx_queue_hw(txq);
1014 }
1015
1016 static void
hns3_init_tx_ring_tc(struct hns3_adapter * hns)1017 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
1018 {
1019 struct hns3_hw *hw = &hns->hw;
1020 struct hns3_tx_queue *txq;
1021 int i, num;
1022
1023 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1024 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
1025 int j;
1026
1027 if (!tc_queue->enable)
1028 continue;
1029
1030 for (j = 0; j < tc_queue->tqp_count; j++) {
1031 num = tc_queue->tqp_offset + j;
1032 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
1033 if (txq == NULL)
1034 continue;
1035
1036 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
1037 }
1038 }
1039 }
1040
1041 static int
hns3_init_rx_queues(struct hns3_adapter * hns)1042 hns3_init_rx_queues(struct hns3_adapter *hns)
1043 {
1044 struct hns3_hw *hw = &hns->hw;
1045 struct hns3_rx_queue *rxq;
1046 uint16_t i, j;
1047 int ret;
1048
1049 /* Initialize RSS for queues */
1050 ret = hns3_config_rss(hns);
1051 if (ret) {
1052 hns3_err(hw, "failed to configure rss, ret = %d.", ret);
1053 return ret;
1054 }
1055
1056 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1057 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
1058 if (!rxq) {
1059 hns3_err(hw, "Rx queue %u not available or setup.", i);
1060 goto out;
1061 }
1062
1063 if (rxq->rx_deferred_start)
1064 continue;
1065
1066 ret = hns3_init_rxq(hns, i);
1067 if (ret) {
1068 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
1069 ret);
1070 goto out;
1071 }
1072 }
1073
1074 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
1075 hns3_init_fake_rxq(hns, i);
1076
1077 return 0;
1078
1079 out:
1080 for (j = 0; j < i; j++) {
1081 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
1082 hns3_rx_queue_release_mbufs(rxq);
1083 }
1084
1085 return ret;
1086 }
1087
1088 static int
hns3_init_tx_queues(struct hns3_adapter * hns)1089 hns3_init_tx_queues(struct hns3_adapter *hns)
1090 {
1091 struct hns3_hw *hw = &hns->hw;
1092 struct hns3_tx_queue *txq;
1093 uint16_t i;
1094
1095 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1096 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
1097 if (!txq) {
1098 hns3_err(hw, "Tx queue %u not available or setup.", i);
1099 return -EINVAL;
1100 }
1101
1102 if (txq->tx_deferred_start)
1103 continue;
1104 hns3_init_txq(txq);
1105 }
1106
1107 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
1108 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
1109 hns3_init_txq(txq);
1110 }
1111 hns3_init_tx_ring_tc(hns);
1112
1113 return 0;
1114 }
1115
1116 /*
1117 * Init all queues.
1118 * Note: just init and setup queues, and don't enable tqps.
1119 */
1120 int
hns3_init_queues(struct hns3_adapter * hns,bool reset_queue)1121 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
1122 {
1123 struct hns3_hw *hw = &hns->hw;
1124 int ret;
1125
1126 if (reset_queue) {
1127 ret = hns3_reset_all_tqps(hns);
1128 if (ret) {
1129 hns3_err(hw, "failed to reset all queues, ret = %d.",
1130 ret);
1131 return ret;
1132 }
1133 }
1134
1135 ret = hns3_init_rx_queues(hns);
1136 if (ret) {
1137 hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
1138 return ret;
1139 }
1140
1141 ret = hns3_init_tx_queues(hns);
1142 if (ret) {
1143 hns3_dev_release_mbufs(hns);
1144 hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
1145 }
1146
1147 return ret;
1148 }
1149
1150 void
hns3_start_tqps(struct hns3_hw * hw)1151 hns3_start_tqps(struct hns3_hw *hw)
1152 {
1153 struct hns3_tx_queue *txq;
1154 struct hns3_rx_queue *rxq;
1155 uint16_t i;
1156
1157 hns3_enable_all_queues(hw, true);
1158
1159 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1160 txq = hw->data->tx_queues[i];
1161 if (txq->enabled)
1162 hw->data->tx_queue_state[i] =
1163 RTE_ETH_QUEUE_STATE_STARTED;
1164 }
1165
1166 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1167 rxq = hw->data->rx_queues[i];
1168 if (rxq->enabled)
1169 hw->data->rx_queue_state[i] =
1170 RTE_ETH_QUEUE_STATE_STARTED;
1171 }
1172 }
1173
1174 void
hns3_stop_tqps(struct hns3_hw * hw)1175 hns3_stop_tqps(struct hns3_hw *hw)
1176 {
1177 uint16_t i;
1178
1179 hns3_enable_all_queues(hw, false);
1180
1181 for (i = 0; i < hw->data->nb_tx_queues; i++)
1182 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1183
1184 for (i = 0; i < hw->data->nb_rx_queues; i++)
1185 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1186 }
1187
1188 /*
1189 * Iterate over all Rx Queue, and call the callback() function for each Rx
1190 * queue.
1191 *
1192 * @param[in] dev
1193 * The target eth dev.
1194 * @param[in] callback
1195 * The function to call for each queue.
1196 * if callback function return nonzero will stop iterate and return it's value
1197 * @param[in] arg
1198 * The arguments to provide the callback function with.
1199 *
1200 * @return
1201 * 0 on success, otherwise with errno set.
1202 */
1203 int
hns3_rxq_iterate(struct rte_eth_dev * dev,int (* callback)(struct hns3_rx_queue *,void *),void * arg)1204 hns3_rxq_iterate(struct rte_eth_dev *dev,
1205 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
1206 {
1207 uint32_t i;
1208 int ret;
1209
1210 if (dev->data->rx_queues == NULL)
1211 return -EINVAL;
1212
1213 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1214 ret = callback(dev->data->rx_queues[i], arg);
1215 if (ret != 0)
1216 return ret;
1217 }
1218
1219 return 0;
1220 }
1221
1222 static void*
hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev * dev,struct hns3_queue_info * q_info)1223 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
1224 struct hns3_queue_info *q_info)
1225 {
1226 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227 const struct rte_memzone *rx_mz;
1228 struct hns3_rx_queue *rxq;
1229 unsigned int rx_desc;
1230
1231 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
1232 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1233 if (rxq == NULL) {
1234 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!",
1235 q_info->idx);
1236 return NULL;
1237 }
1238
1239 /* Allocate rx ring hardware descriptors. */
1240 rxq->queue_id = q_info->idx;
1241 rxq->nb_rx_desc = q_info->nb_desc;
1242
1243 /*
1244 * Allocate a litter more memory because rx vector functions
1245 * don't check boundaries each time.
1246 */
1247 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1248 sizeof(struct hns3_desc);
1249 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1250 rx_desc, HNS3_RING_BASE_ALIGN,
1251 q_info->socket_id);
1252 if (rx_mz == NULL) {
1253 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!",
1254 q_info->idx);
1255 hns3_rx_queue_release(rxq);
1256 return NULL;
1257 }
1258 rxq->mz = rx_mz;
1259 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
1260 rxq->rx_ring_phys_addr = rx_mz->iova;
1261
1262 hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx,
1263 rxq->rx_ring_phys_addr);
1264
1265 return rxq;
1266 }
1267
1268 static int
hns3_fake_rx_queue_setup(struct rte_eth_dev * dev,uint16_t idx,uint16_t nb_desc,unsigned int socket_id)1269 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1270 uint16_t nb_desc, unsigned int socket_id)
1271 {
1272 struct hns3_adapter *hns = dev->data->dev_private;
1273 struct hns3_hw *hw = &hns->hw;
1274 struct hns3_queue_info q_info;
1275 struct hns3_rx_queue *rxq;
1276 uint16_t nb_rx_q;
1277
1278 if (hw->fkq_data.rx_queues[idx]) {
1279 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
1280 hw->fkq_data.rx_queues[idx] = NULL;
1281 }
1282
1283 q_info.idx = idx;
1284 q_info.socket_id = socket_id;
1285 q_info.nb_desc = nb_desc;
1286 q_info.type = "hns3 fake RX queue";
1287 q_info.ring_name = "rx_fake_ring";
1288 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1289 if (rxq == NULL) {
1290 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx);
1291 return -ENOMEM;
1292 }
1293
1294 /* Don't need alloc sw_ring, because upper applications don't use it */
1295 rxq->sw_ring = NULL;
1296
1297 rxq->hns = hns;
1298 rxq->rx_deferred_start = false;
1299 rxq->port_id = dev->data->port_id;
1300 rxq->configured = true;
1301 nb_rx_q = dev->data->nb_rx_queues;
1302 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1303 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
1304 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1305
1306 rte_spinlock_lock(&hw->lock);
1307 hw->fkq_data.rx_queues[idx] = rxq;
1308 rte_spinlock_unlock(&hw->lock);
1309
1310 return 0;
1311 }
1312
1313 static void*
hns3_alloc_txq_and_dma_zone(struct rte_eth_dev * dev,struct hns3_queue_info * q_info)1314 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1315 struct hns3_queue_info *q_info)
1316 {
1317 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318 const struct rte_memzone *tx_mz;
1319 struct hns3_tx_queue *txq;
1320 struct hns3_desc *desc;
1321 unsigned int tx_desc;
1322 int i;
1323
1324 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1325 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1326 if (txq == NULL) {
1327 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!",
1328 q_info->idx);
1329 return NULL;
1330 }
1331
1332 /* Allocate tx ring hardware descriptors. */
1333 txq->queue_id = q_info->idx;
1334 txq->nb_tx_desc = q_info->nb_desc;
1335 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1336 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1337 tx_desc, HNS3_RING_BASE_ALIGN,
1338 q_info->socket_id);
1339 if (tx_mz == NULL) {
1340 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!",
1341 q_info->idx);
1342 hns3_tx_queue_release(txq);
1343 return NULL;
1344 }
1345 txq->mz = tx_mz;
1346 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1347 txq->tx_ring_phys_addr = tx_mz->iova;
1348
1349 hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx,
1350 txq->tx_ring_phys_addr);
1351
1352 /* Clear tx bd */
1353 desc = txq->tx_ring;
1354 for (i = 0; i < txq->nb_tx_desc; i++) {
1355 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1356 desc++;
1357 }
1358
1359 return txq;
1360 }
1361
1362 static int
hns3_fake_tx_queue_setup(struct rte_eth_dev * dev,uint16_t idx,uint16_t nb_desc,unsigned int socket_id)1363 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1364 uint16_t nb_desc, unsigned int socket_id)
1365 {
1366 struct hns3_adapter *hns = dev->data->dev_private;
1367 struct hns3_hw *hw = &hns->hw;
1368 struct hns3_queue_info q_info;
1369 struct hns3_tx_queue *txq;
1370 uint16_t nb_tx_q;
1371
1372 if (hw->fkq_data.tx_queues[idx] != NULL) {
1373 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1374 hw->fkq_data.tx_queues[idx] = NULL;
1375 }
1376
1377 q_info.idx = idx;
1378 q_info.socket_id = socket_id;
1379 q_info.nb_desc = nb_desc;
1380 q_info.type = "hns3 fake TX queue";
1381 q_info.ring_name = "tx_fake_ring";
1382 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1383 if (txq == NULL) {
1384 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx);
1385 return -ENOMEM;
1386 }
1387
1388 /* Don't need alloc sw_ring, because upper applications don't use it */
1389 txq->sw_ring = NULL;
1390 txq->free = NULL;
1391
1392 txq->hns = hns;
1393 txq->tx_deferred_start = false;
1394 txq->port_id = dev->data->port_id;
1395 txq->configured = true;
1396 nb_tx_q = dev->data->nb_tx_queues;
1397 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1398 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1399
1400 rte_spinlock_lock(&hw->lock);
1401 hw->fkq_data.tx_queues[idx] = txq;
1402 rte_spinlock_unlock(&hw->lock);
1403
1404 return 0;
1405 }
1406
1407 static int
hns3_fake_rx_queue_config(struct hns3_hw * hw,uint16_t nb_queues)1408 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1409 {
1410 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1411 void **rxq;
1412 uint16_t i;
1413
1414 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1415 /* first time configuration */
1416 uint32_t size;
1417 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1418 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1419 RTE_CACHE_LINE_SIZE);
1420 if (hw->fkq_data.rx_queues == NULL) {
1421 hw->fkq_data.nb_fake_rx_queues = 0;
1422 return -ENOMEM;
1423 }
1424 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1425 /* re-configure */
1426 rxq = hw->fkq_data.rx_queues;
1427 for (i = nb_queues; i < old_nb_queues; i++)
1428 hns3_dev_rx_queue_release(rxq[i]);
1429
1430 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1431 RTE_CACHE_LINE_SIZE);
1432 if (rxq == NULL)
1433 return -ENOMEM;
1434 if (nb_queues > old_nb_queues) {
1435 uint16_t new_qs = nb_queues - old_nb_queues;
1436 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1437 }
1438
1439 hw->fkq_data.rx_queues = rxq;
1440 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1441 rxq = hw->fkq_data.rx_queues;
1442 for (i = nb_queues; i < old_nb_queues; i++)
1443 hns3_dev_rx_queue_release(rxq[i]);
1444
1445 rte_free(hw->fkq_data.rx_queues);
1446 hw->fkq_data.rx_queues = NULL;
1447 }
1448
1449 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1450
1451 return 0;
1452 }
1453
1454 static int
hns3_fake_tx_queue_config(struct hns3_hw * hw,uint16_t nb_queues)1455 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1456 {
1457 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1458 void **txq;
1459 uint16_t i;
1460
1461 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1462 /* first time configuration */
1463 uint32_t size;
1464 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1465 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1466 RTE_CACHE_LINE_SIZE);
1467 if (hw->fkq_data.tx_queues == NULL) {
1468 hw->fkq_data.nb_fake_tx_queues = 0;
1469 return -ENOMEM;
1470 }
1471 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1472 /* re-configure */
1473 txq = hw->fkq_data.tx_queues;
1474 for (i = nb_queues; i < old_nb_queues; i++)
1475 hns3_dev_tx_queue_release(txq[i]);
1476 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1477 RTE_CACHE_LINE_SIZE);
1478 if (txq == NULL)
1479 return -ENOMEM;
1480 if (nb_queues > old_nb_queues) {
1481 uint16_t new_qs = nb_queues - old_nb_queues;
1482 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1483 }
1484
1485 hw->fkq_data.tx_queues = txq;
1486 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1487 txq = hw->fkq_data.tx_queues;
1488 for (i = nb_queues; i < old_nb_queues; i++)
1489 hns3_dev_tx_queue_release(txq[i]);
1490
1491 rte_free(hw->fkq_data.tx_queues);
1492 hw->fkq_data.tx_queues = NULL;
1493 }
1494 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1495
1496 return 0;
1497 }
1498
1499 int
hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev * dev,uint16_t nb_rx_q,uint16_t nb_tx_q)1500 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1501 uint16_t nb_tx_q)
1502 {
1503 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504 uint16_t rx_need_add_nb_q;
1505 uint16_t tx_need_add_nb_q;
1506 uint16_t port_id;
1507 uint16_t q;
1508 int ret;
1509
1510 /* Setup new number of fake RX/TX queues and reconfigure device. */
1511 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1512 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1513 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1514 if (ret) {
1515 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1516 return ret;
1517 }
1518
1519 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1520 if (ret) {
1521 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1522 goto cfg_fake_tx_q_fail;
1523 }
1524
1525 /* Allocate and set up fake RX queue per Ethernet port. */
1526 port_id = hw->data->port_id;
1527 for (q = 0; q < rx_need_add_nb_q; q++) {
1528 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1529 rte_eth_dev_socket_id(port_id));
1530 if (ret)
1531 goto setup_fake_rx_q_fail;
1532 }
1533
1534 /* Allocate and set up fake TX queue per Ethernet port. */
1535 for (q = 0; q < tx_need_add_nb_q; q++) {
1536 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1537 rte_eth_dev_socket_id(port_id));
1538 if (ret)
1539 goto setup_fake_tx_q_fail;
1540 }
1541
1542 return 0;
1543
1544 setup_fake_tx_q_fail:
1545 setup_fake_rx_q_fail:
1546 (void)hns3_fake_tx_queue_config(hw, 0);
1547 cfg_fake_tx_q_fail:
1548 (void)hns3_fake_rx_queue_config(hw, 0);
1549
1550 return ret;
1551 }
1552
1553 void
hns3_dev_release_mbufs(struct hns3_adapter * hns)1554 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1555 {
1556 struct rte_eth_dev_data *dev_data = hns->hw.data;
1557 struct hns3_rx_queue *rxq;
1558 struct hns3_tx_queue *txq;
1559 int i;
1560
1561 if (dev_data->rx_queues)
1562 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1563 rxq = dev_data->rx_queues[i];
1564 if (rxq == NULL)
1565 continue;
1566 hns3_rx_queue_release_mbufs(rxq);
1567 }
1568
1569 if (dev_data->tx_queues)
1570 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1571 txq = dev_data->tx_queues[i];
1572 if (txq == NULL)
1573 continue;
1574 hns3_tx_queue_release_mbufs(txq);
1575 }
1576 }
1577
1578 static int
hns3_rx_buf_len_calc(struct rte_mempool * mp,uint16_t * rx_buf_len)1579 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1580 {
1581 uint16_t vld_buf_size;
1582 uint16_t num_hw_specs;
1583 uint16_t i;
1584
1585 /*
1586 * hns3 network engine only support to set 4 typical specification, and
1587 * different buffer size will affect the max packet_len and the max
1588 * number of segmentation when hw gro is turned on in receive side. The
1589 * relationship between them is as follows:
1590 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1591 * ---------------------|-------------------|----------------
1592 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1593 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1594 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1595 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1596 */
1597 static const uint16_t hw_rx_buf_size[] = {
1598 HNS3_4K_BD_BUF_SIZE,
1599 HNS3_2K_BD_BUF_SIZE,
1600 HNS3_1K_BD_BUF_SIZE,
1601 HNS3_512_BD_BUF_SIZE
1602 };
1603
1604 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1605 RTE_PKTMBUF_HEADROOM);
1606 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1607 return -EINVAL;
1608
1609 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1610 for (i = 0; i < num_hw_specs; i++) {
1611 if (vld_buf_size >= hw_rx_buf_size[i]) {
1612 *rx_buf_len = hw_rx_buf_size[i];
1613 break;
1614 }
1615 }
1616 return 0;
1617 }
1618
1619 static int
hns3_rxq_conf_runtime_check(struct hns3_hw * hw,uint16_t buf_size,uint16_t nb_desc)1620 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
1621 uint16_t nb_desc)
1622 {
1623 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1624 struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode;
1625 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
1626 uint16_t min_vec_bds;
1627
1628 /*
1629 * HNS3 hardware network engine set scattered as default. If the driver
1630 * is not work in scattered mode and the pkts greater than buf_size
1631 * but smaller than max_rx_pkt_len will be distributed to multiple BDs.
1632 * Driver cannot handle this situation.
1633 */
1634 if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) {
1635 hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater "
1636 "than rx_buf_len if scattered is off.");
1637 return -EINVAL;
1638 }
1639
1640 if (pkt_burst == hns3_recv_pkts_vec) {
1641 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
1642 HNS3_DEFAULT_RX_BURST;
1643 if (nb_desc < min_vec_bds ||
1644 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
1645 hns3_err(hw, "if Rx burst mode is vector, "
1646 "number of descriptor is required to be "
1647 "bigger than min vector bds:%u, and could be "
1648 "divided by rxq rearm thresh:%u.",
1649 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
1650 return -EINVAL;
1651 }
1652 }
1653 return 0;
1654 }
1655
1656 static int
hns3_rx_queue_conf_check(struct hns3_hw * hw,const struct rte_eth_rxconf * conf,struct rte_mempool * mp,uint16_t nb_desc,uint16_t * buf_size)1657 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1658 struct rte_mempool *mp, uint16_t nb_desc,
1659 uint16_t *buf_size)
1660 {
1661 int ret;
1662
1663 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1664 nb_desc % HNS3_ALIGN_RING_DESC) {
1665 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1666 nb_desc);
1667 return -EINVAL;
1668 }
1669
1670 if (conf->rx_drop_en == 0)
1671 hns3_warn(hw, "if no descriptors available, packets are always "
1672 "dropped and rx_drop_en (1) is fixed on");
1673
1674 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1675 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1676 "minimal data room size (%u).",
1677 rte_pktmbuf_data_room_size(mp),
1678 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1679 return -EINVAL;
1680 }
1681
1682 if (hw->data->dev_started) {
1683 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
1684 if (ret) {
1685 hns3_err(hw, "Rx queue runtime setup fail.");
1686 return ret;
1687 }
1688 }
1689
1690 return 0;
1691 }
1692
1693 uint32_t
hns3_get_tqp_reg_offset(uint16_t queue_id)1694 hns3_get_tqp_reg_offset(uint16_t queue_id)
1695 {
1696 uint32_t reg_offset;
1697
1698 /* Need an extend offset to config queue > 1024 */
1699 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
1700 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
1701 else
1702 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
1703 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
1704 HNS3_TQP_REG_SIZE;
1705
1706 return reg_offset;
1707 }
1708
1709 int
hns3_rx_queue_setup(struct rte_eth_dev * dev,uint16_t idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_rxconf * conf,struct rte_mempool * mp)1710 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1711 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1712 struct rte_mempool *mp)
1713 {
1714 struct hns3_adapter *hns = dev->data->dev_private;
1715 struct hns3_hw *hw = &hns->hw;
1716 struct hns3_queue_info q_info;
1717 struct hns3_rx_queue *rxq;
1718 uint16_t rx_buf_size;
1719 int rx_entry_len;
1720 int ret;
1721
1722 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1723 if (ret)
1724 return ret;
1725
1726 if (dev->data->rx_queues[idx]) {
1727 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1728 dev->data->rx_queues[idx] = NULL;
1729 }
1730
1731 q_info.idx = idx;
1732 q_info.socket_id = socket_id;
1733 q_info.nb_desc = nb_desc;
1734 q_info.type = "hns3 RX queue";
1735 q_info.ring_name = "rx_ring";
1736
1737 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1738 if (rxq == NULL) {
1739 hns3_err(hw,
1740 "Failed to alloc mem and reserve DMA mem for rx ring!");
1741 return -ENOMEM;
1742 }
1743
1744 rxq->hns = hns;
1745 rxq->ptype_tbl = &hns->ptype_tbl;
1746 rxq->mb_pool = mp;
1747 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1748 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1749
1750 rxq->rx_deferred_start = conf->rx_deferred_start;
1751 if (rxq->rx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
1752 hns3_warn(hw, "deferred start is not supported.");
1753 rxq->rx_deferred_start = false;
1754 }
1755
1756 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1757 sizeof(struct hns3_entry);
1758 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1759 RTE_CACHE_LINE_SIZE, socket_id);
1760 if (rxq->sw_ring == NULL) {
1761 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1762 hns3_rx_queue_release(rxq);
1763 return -ENOMEM;
1764 }
1765
1766 rxq->next_to_use = 0;
1767 rxq->rx_free_hold = 0;
1768 rxq->rx_rearm_start = 0;
1769 rxq->rx_rearm_nb = 0;
1770 rxq->pkt_first_seg = NULL;
1771 rxq->pkt_last_seg = NULL;
1772 rxq->port_id = dev->data->port_id;
1773 /*
1774 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1775 * the pvid_sw_discard_en in the queue struct should not be changed,
1776 * because PVID-related operations do not need to be processed by PMD
1777 * driver. For hns3 VF device, whether it needs to process PVID depends
1778 * on the configuration of PF kernel mode netdevice driver. And the
1779 * related PF configuration is delivered through the mailbox and finally
1780 * reflectd in port_base_vlan_cfg.
1781 */
1782 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1783 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1784 HNS3_PORT_BASE_VLAN_ENABLE;
1785 else
1786 rxq->pvid_sw_discard_en = false;
1787 rxq->configured = true;
1788 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1789 idx * HNS3_TQP_REG_SIZE);
1790 rxq->io_base = (void *)((char *)hw->io_base +
1791 hns3_get_tqp_reg_offset(idx));
1792 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1793 HNS3_RING_RX_HEAD_REG);
1794 rxq->rx_buf_len = rx_buf_size;
1795 rxq->l2_errors = 0;
1796 rxq->pkt_len_errors = 0;
1797 rxq->l3_csum_errors = 0;
1798 rxq->l4_csum_errors = 0;
1799 rxq->ol3_csum_errors = 0;
1800 rxq->ol4_csum_errors = 0;
1801
1802 /* CRC len set here is used for amending packet length */
1803 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1804 rxq->crc_len = RTE_ETHER_CRC_LEN;
1805 else
1806 rxq->crc_len = 0;
1807
1808 rxq->bulk_mbuf_num = 0;
1809
1810 rte_spinlock_lock(&hw->lock);
1811 dev->data->rx_queues[idx] = rxq;
1812 rte_spinlock_unlock(&hw->lock);
1813
1814 return 0;
1815 }
1816
1817 void
hns3_rx_scattered_reset(struct rte_eth_dev * dev)1818 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1819 {
1820 struct hns3_adapter *hns = dev->data->dev_private;
1821 struct hns3_hw *hw = &hns->hw;
1822
1823 hw->rx_buf_len = 0;
1824 dev->data->scattered_rx = false;
1825 }
1826
1827 void
hns3_rx_scattered_calc(struct rte_eth_dev * dev)1828 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1829 {
1830 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1831 struct hns3_adapter *hns = dev->data->dev_private;
1832 struct hns3_hw *hw = &hns->hw;
1833 struct hns3_rx_queue *rxq;
1834 uint32_t queue_id;
1835
1836 if (dev->data->rx_queues == NULL)
1837 return;
1838
1839 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1840 rxq = dev->data->rx_queues[queue_id];
1841 if (hw->rx_buf_len == 0)
1842 hw->rx_buf_len = rxq->rx_buf_len;
1843 else
1844 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1845 rxq->rx_buf_len);
1846 }
1847
1848 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
1849 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
1850 dev->data->scattered_rx = true;
1851 }
1852
1853 const uint32_t *
hns3_dev_supported_ptypes_get(struct rte_eth_dev * dev)1854 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1855 {
1856 static const uint32_t ptypes[] = {
1857 RTE_PTYPE_L2_ETHER,
1858 RTE_PTYPE_L2_ETHER_VLAN,
1859 RTE_PTYPE_L2_ETHER_QINQ,
1860 RTE_PTYPE_L2_ETHER_LLDP,
1861 RTE_PTYPE_L2_ETHER_ARP,
1862 RTE_PTYPE_L3_IPV4,
1863 RTE_PTYPE_L3_IPV4_EXT,
1864 RTE_PTYPE_L3_IPV6,
1865 RTE_PTYPE_L3_IPV6_EXT,
1866 RTE_PTYPE_L4_IGMP,
1867 RTE_PTYPE_L4_ICMP,
1868 RTE_PTYPE_L4_SCTP,
1869 RTE_PTYPE_L4_TCP,
1870 RTE_PTYPE_L4_UDP,
1871 RTE_PTYPE_TUNNEL_GRE,
1872 RTE_PTYPE_INNER_L2_ETHER,
1873 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1874 RTE_PTYPE_INNER_L2_ETHER_QINQ,
1875 RTE_PTYPE_INNER_L3_IPV4,
1876 RTE_PTYPE_INNER_L3_IPV6,
1877 RTE_PTYPE_INNER_L3_IPV4_EXT,
1878 RTE_PTYPE_INNER_L3_IPV6_EXT,
1879 RTE_PTYPE_INNER_L4_UDP,
1880 RTE_PTYPE_INNER_L4_TCP,
1881 RTE_PTYPE_INNER_L4_SCTP,
1882 RTE_PTYPE_INNER_L4_ICMP,
1883 RTE_PTYPE_TUNNEL_VXLAN,
1884 RTE_PTYPE_TUNNEL_NVGRE,
1885 RTE_PTYPE_UNKNOWN
1886 };
1887
1888 if (dev->rx_pkt_burst == hns3_recv_pkts ||
1889 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
1890 dev->rx_pkt_burst == hns3_recv_pkts_vec ||
1891 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
1892 return ptypes;
1893
1894 return NULL;
1895 }
1896
1897 static void
hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table * tbl)1898 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
1899 {
1900 tbl->l2l3table[0][0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
1901 tbl->l2l3table[0][1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
1902 tbl->l2l3table[0][2] = RTE_PTYPE_L2_ETHER_ARP;
1903 tbl->l2l3table[0][3] = RTE_PTYPE_L2_ETHER;
1904 tbl->l2l3table[0][4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
1905 tbl->l2l3table[0][5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
1906 tbl->l2l3table[0][6] = RTE_PTYPE_L2_ETHER_LLDP;
1907 tbl->l2l3table[0][15] = RTE_PTYPE_L2_ETHER;
1908
1909 tbl->l2l3table[1][0] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4;
1910 tbl->l2l3table[1][1] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6;
1911 tbl->l2l3table[1][2] = RTE_PTYPE_L2_ETHER_ARP;
1912 tbl->l2l3table[1][3] = RTE_PTYPE_L2_ETHER_VLAN;
1913 tbl->l2l3table[1][4] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4_EXT;
1914 tbl->l2l3table[1][5] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6_EXT;
1915 tbl->l2l3table[1][6] = RTE_PTYPE_L2_ETHER_LLDP;
1916 tbl->l2l3table[1][15] = RTE_PTYPE_L2_ETHER_VLAN;
1917
1918 tbl->l2l3table[2][0] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4;
1919 tbl->l2l3table[2][1] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6;
1920 tbl->l2l3table[2][2] = RTE_PTYPE_L2_ETHER_ARP;
1921 tbl->l2l3table[2][3] = RTE_PTYPE_L2_ETHER_QINQ;
1922 tbl->l2l3table[2][4] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4_EXT;
1923 tbl->l2l3table[2][5] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6_EXT;
1924 tbl->l2l3table[2][6] = RTE_PTYPE_L2_ETHER_LLDP;
1925 tbl->l2l3table[2][15] = RTE_PTYPE_L2_ETHER_QINQ;
1926
1927 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
1928 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
1929 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
1930 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
1931 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
1932 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
1933 }
1934
1935 static void
hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table * tbl)1936 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
1937 {
1938 tbl->inner_l2table[0] = RTE_PTYPE_INNER_L2_ETHER;
1939 tbl->inner_l2table[1] = RTE_PTYPE_INNER_L2_ETHER_VLAN;
1940 tbl->inner_l2table[2] = RTE_PTYPE_INNER_L2_ETHER_QINQ;
1941
1942 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L3_IPV4;
1943 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L3_IPV6;
1944 /* There is not a ptype for inner ARP/RARP */
1945 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN;
1946 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN;
1947 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L3_IPV4_EXT;
1948 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L3_IPV6_EXT;
1949
1950 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
1951 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
1952 /* There is not a ptype for inner GRE */
1953 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN;
1954 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
1955 /* There is not a ptype for inner IGMP */
1956 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN;
1957 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
1958
1959 tbl->ol2table[0] = RTE_PTYPE_L2_ETHER;
1960 tbl->ol2table[1] = RTE_PTYPE_L2_ETHER_VLAN;
1961 tbl->ol2table[2] = RTE_PTYPE_L2_ETHER_QINQ;
1962
1963 tbl->ol3table[0] = RTE_PTYPE_L3_IPV4;
1964 tbl->ol3table[1] = RTE_PTYPE_L3_IPV6;
1965 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN;
1966 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN;
1967 tbl->ol3table[4] = RTE_PTYPE_L3_IPV4_EXT;
1968 tbl->ol3table[5] = RTE_PTYPE_L3_IPV6_EXT;
1969
1970 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN;
1971 tbl->ol4table[1] = RTE_PTYPE_TUNNEL_VXLAN;
1972 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
1973 }
1974
1975 void
hns3_init_rx_ptype_tble(struct rte_eth_dev * dev)1976 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
1977 {
1978 struct hns3_adapter *hns = dev->data->dev_private;
1979 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
1980
1981 memset(tbl, 0, sizeof(*tbl));
1982
1983 hns3_init_non_tunnel_ptype_tbl(tbl);
1984 hns3_init_tunnel_ptype_tbl(tbl);
1985 }
1986
1987 static inline void
hns3_rxd_to_vlan_tci(struct hns3_rx_queue * rxq,struct rte_mbuf * mb,uint32_t l234_info,const struct hns3_desc * rxd)1988 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
1989 uint32_t l234_info, const struct hns3_desc *rxd)
1990 {
1991 #define HNS3_STRP_STATUS_NUM 0x4
1992
1993 #define HNS3_NO_STRP_VLAN_VLD 0x0
1994 #define HNS3_INNER_STRP_VLAN_VLD 0x1
1995 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
1996 uint32_t strip_status;
1997 uint32_t report_mode;
1998
1999 /*
2000 * Since HW limitation, the vlan tag will always be inserted into RX
2001 * descriptor when strip the tag from packet, driver needs to determine
2002 * reporting which tag to mbuf according to the PVID configuration
2003 * and vlan striped status.
2004 */
2005 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
2006 {
2007 HNS3_NO_STRP_VLAN_VLD,
2008 HNS3_OUTER_STRP_VLAN_VLD,
2009 HNS3_INNER_STRP_VLAN_VLD,
2010 HNS3_OUTER_STRP_VLAN_VLD
2011 },
2012 {
2013 HNS3_NO_STRP_VLAN_VLD,
2014 HNS3_NO_STRP_VLAN_VLD,
2015 HNS3_NO_STRP_VLAN_VLD,
2016 HNS3_INNER_STRP_VLAN_VLD
2017 }
2018 };
2019 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
2020 HNS3_RXD_STRP_TAGP_S);
2021 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
2022 switch (report_mode) {
2023 case HNS3_NO_STRP_VLAN_VLD:
2024 mb->vlan_tci = 0;
2025 return;
2026 case HNS3_INNER_STRP_VLAN_VLD:
2027 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2028 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
2029 return;
2030 case HNS3_OUTER_STRP_VLAN_VLD:
2031 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2032 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
2033 return;
2034 default:
2035 mb->vlan_tci = 0;
2036 return;
2037 }
2038 }
2039
2040 static inline void
recalculate_data_len(struct rte_mbuf * first_seg,struct rte_mbuf * last_seg,struct rte_mbuf * rxm,struct hns3_rx_queue * rxq,uint16_t data_len)2041 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
2042 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
2043 uint16_t data_len)
2044 {
2045 uint8_t crc_len = rxq->crc_len;
2046
2047 if (data_len <= crc_len) {
2048 rte_pktmbuf_free_seg(rxm);
2049 first_seg->nb_segs--;
2050 last_seg->data_len = (uint16_t)(last_seg->data_len -
2051 (crc_len - data_len));
2052 last_seg->next = NULL;
2053 } else
2054 rxm->data_len = (uint16_t)(data_len - crc_len);
2055 }
2056
2057 static inline struct rte_mbuf *
hns3_rx_alloc_buffer(struct hns3_rx_queue * rxq)2058 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
2059 {
2060 int ret;
2061
2062 if (likely(rxq->bulk_mbuf_num > 0))
2063 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2064
2065 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
2066 HNS3_BULK_ALLOC_MBUF_NUM);
2067 if (likely(ret == 0)) {
2068 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
2069 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2070 } else
2071 return rte_mbuf_raw_alloc(rxq->mb_pool);
2072 }
2073
2074 uint16_t
hns3_recv_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)2075 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2076 {
2077 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2078 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2079 struct hns3_rx_queue *rxq; /* RX queue */
2080 struct hns3_entry *sw_ring;
2081 struct hns3_entry *rxe;
2082 struct hns3_desc rxd;
2083 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2084 struct rte_mbuf *rxm;
2085 uint32_t bd_base_info;
2086 uint32_t cksum_err;
2087 uint32_t l234_info;
2088 uint32_t ol_info;
2089 uint64_t dma_addr;
2090 uint16_t nb_rx_bd;
2091 uint16_t nb_rx;
2092 uint16_t rx_id;
2093 int ret;
2094
2095 nb_rx = 0;
2096 nb_rx_bd = 0;
2097 rxq = rx_queue;
2098 rx_ring = rxq->rx_ring;
2099 sw_ring = rxq->sw_ring;
2100 rx_id = rxq->next_to_use;
2101
2102 while (nb_rx < nb_pkts) {
2103 rxdp = &rx_ring[rx_id];
2104 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2105 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2106 break;
2107
2108 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2109 (1u << HNS3_RXD_VLD_B)];
2110
2111 nmb = hns3_rx_alloc_buffer(rxq);
2112 if (unlikely(nmb == NULL)) {
2113 uint16_t port_id;
2114
2115 port_id = rxq->port_id;
2116 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
2117 break;
2118 }
2119
2120 nb_rx_bd++;
2121 rxe = &sw_ring[rx_id];
2122 rx_id++;
2123 if (unlikely(rx_id == rxq->nb_rx_desc))
2124 rx_id = 0;
2125
2126 rte_prefetch0(sw_ring[rx_id].mbuf);
2127 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2128 rte_prefetch0(&rx_ring[rx_id]);
2129 rte_prefetch0(&sw_ring[rx_id]);
2130 }
2131
2132 rxm = rxe->mbuf;
2133 rxe->mbuf = nmb;
2134
2135 dma_addr = rte_mbuf_data_iova_default(nmb);
2136 rxdp->addr = rte_cpu_to_le_64(dma_addr);
2137 rxdp->rx.bd_base_info = 0;
2138
2139 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2140 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
2141 rxq->crc_len;
2142 rxm->data_len = rxm->pkt_len;
2143 rxm->port = rxq->port_id;
2144 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2145 rxm->ol_flags = PKT_RX_RSS_HASH;
2146 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2147 rxm->hash.fdir.hi =
2148 rte_le_to_cpu_16(rxd.rx.fd_id);
2149 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2150 }
2151 rxm->nb_segs = 1;
2152 rxm->next = NULL;
2153
2154 /* Load remained descriptor data and extract necessary fields */
2155 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2156 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2157 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info,
2158 l234_info, &cksum_err);
2159 if (unlikely(ret))
2160 goto pkt_err;
2161
2162 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
2163
2164 if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2165 hns3_rx_set_cksum_flag(rxm, rxm->packet_type,
2166 cksum_err);
2167 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
2168
2169 rx_pkts[nb_rx++] = rxm;
2170 continue;
2171 pkt_err:
2172 rte_pktmbuf_free(rxm);
2173 }
2174
2175 rxq->next_to_use = rx_id;
2176 rxq->rx_free_hold += nb_rx_bd;
2177 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2178 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2179 rxq->rx_free_hold = 0;
2180 }
2181
2182 return nb_rx;
2183 }
2184
2185 uint16_t
hns3_recv_scattered_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)2186 hns3_recv_scattered_pkts(void *rx_queue,
2187 struct rte_mbuf **rx_pkts,
2188 uint16_t nb_pkts)
2189 {
2190 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2191 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2192 struct hns3_rx_queue *rxq; /* RX queue */
2193 struct hns3_entry *sw_ring;
2194 struct hns3_entry *rxe;
2195 struct rte_mbuf *first_seg;
2196 struct rte_mbuf *last_seg;
2197 struct hns3_desc rxd;
2198 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2199 struct rte_mbuf *rxm;
2200 struct rte_eth_dev *dev;
2201 uint32_t bd_base_info;
2202 uint32_t cksum_err;
2203 uint32_t l234_info;
2204 uint32_t gro_size;
2205 uint32_t ol_info;
2206 uint64_t dma_addr;
2207 uint16_t nb_rx_bd;
2208 uint16_t nb_rx;
2209 uint16_t rx_id;
2210 int ret;
2211
2212 nb_rx = 0;
2213 nb_rx_bd = 0;
2214 rxq = rx_queue;
2215
2216 rx_id = rxq->next_to_use;
2217 rx_ring = rxq->rx_ring;
2218 sw_ring = rxq->sw_ring;
2219 first_seg = rxq->pkt_first_seg;
2220 last_seg = rxq->pkt_last_seg;
2221
2222 while (nb_rx < nb_pkts) {
2223 rxdp = &rx_ring[rx_id];
2224 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2225 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2226 break;
2227
2228 /*
2229 * The interactive process between software and hardware of
2230 * receiving a new packet in hns3 network engine:
2231 * 1. Hardware network engine firstly writes the packet content
2232 * to the memory pointed by the 'addr' field of the Rx Buffer
2233 * Descriptor, secondly fills the result of parsing the
2234 * packet include the valid field into the Rx Buffer
2235 * Descriptor in one write operation.
2236 * 2. Driver reads the Rx BD's valid field in the loop to check
2237 * whether it's valid, if valid then assign a new address to
2238 * the addr field, clear the valid field, get the other
2239 * information of the packet by parsing Rx BD's other fields,
2240 * finally write back the number of Rx BDs processed by the
2241 * driver to the HNS3_RING_RX_HEAD_REG register to inform
2242 * hardware.
2243 * In the above process, the ordering is very important. We must
2244 * make sure that CPU read Rx BD's other fields only after the
2245 * Rx BD is valid.
2246 *
2247 * There are two type of re-ordering: compiler re-ordering and
2248 * CPU re-ordering under the ARMv8 architecture.
2249 * 1. we use volatile to deal with compiler re-ordering, so you
2250 * can see that rx_ring/rxdp defined with volatile.
2251 * 2. we commonly use memory barrier to deal with CPU
2252 * re-ordering, but the cost is high.
2253 *
2254 * In order to solve the high cost of using memory barrier, we
2255 * use the data dependency order under the ARMv8 architecture,
2256 * for example:
2257 * instr01: load A
2258 * instr02: load B <- A
2259 * the instr02 will always execute after instr01.
2260 *
2261 * To construct the data dependency ordering, we use the
2262 * following assignment:
2263 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2264 * (1u<<HNS3_RXD_VLD_B)]
2265 * Using gcc compiler under the ARMv8 architecture, the related
2266 * assembly code example as follows:
2267 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
2268 * instr01: ldr w26, [x22, #28] --read bd_base_info
2269 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
2270 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
2271 * 0x10) - 0x10
2272 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
2273 * instr05: ldp x2, x3, [x0]
2274 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
2275 * instr07: ldp x4, x5, [x0, #16]
2276 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
2277 * the instr05~08 depend on x0's value, x0 depent on w26's
2278 * value, the w26 is the bd_base_info, this form the data
2279 * dependency ordering.
2280 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
2281 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
2282 * assignment is correct.
2283 *
2284 * So we use the data dependency ordering instead of memory
2285 * barrier to improve receive performance.
2286 */
2287 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2288 (1u << HNS3_RXD_VLD_B)];
2289
2290 nmb = hns3_rx_alloc_buffer(rxq);
2291 if (unlikely(nmb == NULL)) {
2292 dev = &rte_eth_devices[rxq->port_id];
2293 dev->data->rx_mbuf_alloc_failed++;
2294 break;
2295 }
2296
2297 nb_rx_bd++;
2298 rxe = &sw_ring[rx_id];
2299 rx_id++;
2300 if (unlikely(rx_id == rxq->nb_rx_desc))
2301 rx_id = 0;
2302
2303 rte_prefetch0(sw_ring[rx_id].mbuf);
2304 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2305 rte_prefetch0(&rx_ring[rx_id]);
2306 rte_prefetch0(&sw_ring[rx_id]);
2307 }
2308
2309 rxm = rxe->mbuf;
2310 rxe->mbuf = nmb;
2311
2312 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2313 rxdp->rx.bd_base_info = 0;
2314 rxdp->addr = dma_addr;
2315
2316 if (first_seg == NULL) {
2317 first_seg = rxm;
2318 first_seg->nb_segs = 1;
2319 } else {
2320 first_seg->nb_segs++;
2321 last_seg->next = rxm;
2322 }
2323
2324 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2325 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
2326
2327 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2328 last_seg = rxm;
2329 rxm->next = NULL;
2330 continue;
2331 }
2332
2333 /*
2334 * The last buffer of the received packet. packet len from
2335 * buffer description may contains CRC len, packet len should
2336 * subtract it, same as data len.
2337 */
2338 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
2339
2340 /*
2341 * This is the last buffer of the received packet. If the CRC
2342 * is not stripped by the hardware:
2343 * - Subtract the CRC length from the total packet length.
2344 * - If the last buffer only contains the whole CRC or a part
2345 * of it, free the mbuf associated to the last buffer. If part
2346 * of the CRC is also contained in the previous mbuf, subtract
2347 * the length of that CRC part from the data length of the
2348 * previous mbuf.
2349 */
2350 rxm->next = NULL;
2351 if (unlikely(rxq->crc_len > 0)) {
2352 first_seg->pkt_len -= rxq->crc_len;
2353 recalculate_data_len(first_seg, last_seg, rxm, rxq,
2354 rxm->data_len);
2355 }
2356
2357 first_seg->port = rxq->port_id;
2358 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2359 first_seg->ol_flags = PKT_RX_RSS_HASH;
2360 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2361 first_seg->hash.fdir.hi =
2362 rte_le_to_cpu_16(rxd.rx.fd_id);
2363 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2364 }
2365
2366 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
2367 HNS3_RXD_GRO_SIZE_S);
2368 if (gro_size != 0) {
2369 first_seg->ol_flags |= PKT_RX_LRO;
2370 first_seg->tso_segsz = gro_size;
2371 }
2372
2373 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2374 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2375 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
2376 l234_info, &cksum_err);
2377 if (unlikely(ret))
2378 goto pkt_err;
2379
2380 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
2381 l234_info, ol_info);
2382
2383 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
2384 hns3_rx_set_cksum_flag(first_seg,
2385 first_seg->packet_type,
2386 cksum_err);
2387 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
2388
2389 rx_pkts[nb_rx++] = first_seg;
2390 first_seg = NULL;
2391 continue;
2392 pkt_err:
2393 rte_pktmbuf_free(first_seg);
2394 first_seg = NULL;
2395 }
2396
2397 rxq->next_to_use = rx_id;
2398 rxq->pkt_first_seg = first_seg;
2399 rxq->pkt_last_seg = last_seg;
2400
2401 rxq->rx_free_hold += nb_rx_bd;
2402 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2403 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2404 rxq->rx_free_hold = 0;
2405 }
2406
2407 return nb_rx;
2408 }
2409
2410 void __rte_weak
hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue * rxq)2411 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2412 {
2413 }
2414
2415 int __rte_weak
hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev * dev)2416 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2417 {
2418 return -ENOTSUP;
2419 }
2420
2421 uint16_t __rte_weak
hns3_recv_pkts_vec(__rte_unused void * tx_queue,__rte_unused struct rte_mbuf ** rx_pkts,__rte_unused uint16_t nb_pkts)2422 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2423 __rte_unused struct rte_mbuf **rx_pkts,
2424 __rte_unused uint16_t nb_pkts)
2425 {
2426 return 0;
2427 }
2428
2429 uint16_t __rte_weak
hns3_recv_pkts_vec_sve(__rte_unused void * tx_queue,__rte_unused struct rte_mbuf ** rx_pkts,__rte_unused uint16_t nb_pkts)2430 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
2431 __rte_unused struct rte_mbuf **rx_pkts,
2432 __rte_unused uint16_t nb_pkts)
2433 {
2434 return 0;
2435 }
2436
2437 int
hns3_rx_burst_mode_get(struct rte_eth_dev * dev,__rte_unused uint16_t queue_id,struct rte_eth_burst_mode * mode)2438 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2439 struct rte_eth_burst_mode *mode)
2440 {
2441 static const struct {
2442 eth_rx_burst_t pkt_burst;
2443 const char *info;
2444 } burst_infos[] = {
2445 { hns3_recv_pkts, "Scalar" },
2446 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2447 { hns3_recv_pkts_vec, "Vector Neon" },
2448 { hns3_recv_pkts_vec_sve, "Vector Sve" },
2449 };
2450
2451 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2452 int ret = -EINVAL;
2453 unsigned int i;
2454
2455 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2456 if (pkt_burst == burst_infos[i].pkt_burst) {
2457 snprintf(mode->info, sizeof(mode->info), "%s",
2458 burst_infos[i].info);
2459 ret = 0;
2460 break;
2461 }
2462 }
2463
2464 return ret;
2465 }
2466
2467 static bool
hns3_check_sve_support(void)2468 hns3_check_sve_support(void)
2469 {
2470 #if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT)
2471 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
2472 return true;
2473 #endif
2474 return false;
2475 }
2476
2477 static eth_rx_burst_t
hns3_get_rx_function(struct rte_eth_dev * dev)2478 hns3_get_rx_function(struct rte_eth_dev *dev)
2479 {
2480 struct hns3_adapter *hns = dev->data->dev_private;
2481 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2482
2483 if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0)
2484 return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve :
2485 hns3_recv_pkts_vec;
2486
2487 if (hns->rx_simple_allowed && !dev->data->scattered_rx &&
2488 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0)
2489 return hns3_recv_pkts;
2490
2491 return hns3_recv_scattered_pkts;
2492 }
2493
2494 static int
hns3_tx_queue_conf_check(struct hns3_hw * hw,const struct rte_eth_txconf * conf,uint16_t nb_desc,uint16_t * tx_rs_thresh,uint16_t * tx_free_thresh,uint16_t idx)2495 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2496 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2497 uint16_t *tx_free_thresh, uint16_t idx)
2498 {
2499 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2500 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2501
2502 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2503 nb_desc % HNS3_ALIGN_RING_DESC) {
2504 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2505 nb_desc);
2506 return -EINVAL;
2507 }
2508
2509 rs_thresh = (conf->tx_rs_thresh > 0) ?
2510 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2511 free_thresh = (conf->tx_free_thresh > 0) ?
2512 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2513 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2514 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2515 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2516 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc "
2517 "(%u) of tx descriptors for port=%u queue=%u check "
2518 "fail!",
2519 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2520 idx);
2521 return -EINVAL;
2522 }
2523
2524 if (conf->tx_free_thresh == 0) {
2525 /* Fast free Tx memory buffer to improve cache hit rate */
2526 fast_free_thresh = nb_desc - rs_thresh;
2527 if (fast_free_thresh >=
2528 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2529 free_thresh = fast_free_thresh -
2530 HNS3_TX_FAST_FREE_AHEAD;
2531 }
2532
2533 *tx_rs_thresh = rs_thresh;
2534 *tx_free_thresh = free_thresh;
2535 return 0;
2536 }
2537
2538 int
hns3_tx_queue_setup(struct rte_eth_dev * dev,uint16_t idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_txconf * conf)2539 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2540 unsigned int socket_id, const struct rte_eth_txconf *conf)
2541 {
2542 struct hns3_adapter *hns = dev->data->dev_private;
2543 uint16_t tx_rs_thresh, tx_free_thresh;
2544 struct hns3_hw *hw = &hns->hw;
2545 struct hns3_queue_info q_info;
2546 struct hns3_tx_queue *txq;
2547 int tx_entry_len;
2548 int ret;
2549
2550 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2551 &tx_rs_thresh, &tx_free_thresh, idx);
2552 if (ret)
2553 return ret;
2554
2555 if (dev->data->tx_queues[idx] != NULL) {
2556 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2557 dev->data->tx_queues[idx] = NULL;
2558 }
2559
2560 q_info.idx = idx;
2561 q_info.socket_id = socket_id;
2562 q_info.nb_desc = nb_desc;
2563 q_info.type = "hns3 TX queue";
2564 q_info.ring_name = "tx_ring";
2565 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
2566 if (txq == NULL) {
2567 hns3_err(hw,
2568 "Failed to alloc mem and reserve DMA mem for tx ring!");
2569 return -ENOMEM;
2570 }
2571
2572 txq->tx_deferred_start = conf->tx_deferred_start;
2573 if (txq->tx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
2574 hns3_warn(hw, "deferred start is not supported.");
2575 txq->tx_deferred_start = false;
2576 }
2577
2578 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
2579 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
2580 RTE_CACHE_LINE_SIZE, socket_id);
2581 if (txq->sw_ring == NULL) {
2582 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
2583 hns3_tx_queue_release(txq);
2584 return -ENOMEM;
2585 }
2586
2587 txq->hns = hns;
2588 txq->next_to_use = 0;
2589 txq->next_to_clean = 0;
2590 txq->tx_bd_ready = txq->nb_tx_desc - 1;
2591 txq->tx_free_thresh = tx_free_thresh;
2592 txq->tx_rs_thresh = tx_rs_thresh;
2593 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
2594 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
2595 RTE_CACHE_LINE_SIZE, socket_id);
2596 if (!txq->free) {
2597 hns3_err(hw, "failed to allocate tx mbuf free array!");
2598 hns3_tx_queue_release(txq);
2599 return -ENOMEM;
2600 }
2601
2602 txq->port_id = dev->data->port_id;
2603 /*
2604 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
2605 * the pvid_sw_shift_en in the queue struct should not be changed,
2606 * because PVID-related operations do not need to be processed by PMD
2607 * driver. For hns3 VF device, whether it needs to process PVID depends
2608 * on the configuration of PF kernel mode netdev driver. And the
2609 * related PF configuration is delivered through the mailbox and finally
2610 * reflectd in port_base_vlan_cfg.
2611 */
2612 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
2613 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
2614 HNS3_PORT_BASE_VLAN_ENABLE;
2615 else
2616 txq->pvid_sw_shift_en = false;
2617 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
2618 txq->configured = true;
2619 txq->io_base = (void *)((char *)hw->io_base +
2620 hns3_get_tqp_reg_offset(idx));
2621 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
2622 HNS3_RING_TX_TAIL_REG);
2623 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
2624 txq->tso_mode = hw->tso_mode;
2625 txq->over_length_pkt_cnt = 0;
2626 txq->exceed_limit_bd_pkt_cnt = 0;
2627 txq->exceed_limit_bd_reassem_fail = 0;
2628 txq->unsupported_tunnel_pkt_cnt = 0;
2629 txq->queue_full_cnt = 0;
2630 txq->pkt_padding_fail_cnt = 0;
2631 rte_spinlock_lock(&hw->lock);
2632 dev->data->tx_queues[idx] = txq;
2633 rte_spinlock_unlock(&hw->lock);
2634
2635 return 0;
2636 }
2637
2638 static void
hns3_tx_free_useless_buffer(struct hns3_tx_queue * txq)2639 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
2640 {
2641 uint16_t tx_next_clean = txq->next_to_clean;
2642 uint16_t tx_next_use = txq->next_to_use;
2643 uint16_t tx_bd_ready = txq->tx_bd_ready;
2644 uint16_t tx_bd_max = txq->nb_tx_desc;
2645 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
2646 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
2647 struct rte_mbuf *mbuf;
2648
2649 while ((!(desc->tx.tp_fe_sc_vld_ra_ri &
2650 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) &&
2651 tx_next_use != tx_next_clean) {
2652 mbuf = tx_bak_pkt->mbuf;
2653 if (mbuf) {
2654 rte_pktmbuf_free_seg(mbuf);
2655 tx_bak_pkt->mbuf = NULL;
2656 }
2657
2658 desc++;
2659 tx_bak_pkt++;
2660 tx_next_clean++;
2661 tx_bd_ready++;
2662
2663 if (tx_next_clean >= tx_bd_max) {
2664 tx_next_clean = 0;
2665 desc = txq->tx_ring;
2666 tx_bak_pkt = txq->sw_ring;
2667 }
2668 }
2669
2670 txq->next_to_clean = tx_next_clean;
2671 txq->tx_bd_ready = tx_bd_ready;
2672 }
2673
2674 int
hns3_config_gro(struct hns3_hw * hw,bool en)2675 hns3_config_gro(struct hns3_hw *hw, bool en)
2676 {
2677 struct hns3_cfg_gro_status_cmd *req;
2678 struct hns3_cmd_desc desc;
2679 int ret;
2680
2681 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
2682 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
2683
2684 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
2685
2686 ret = hns3_cmd_send(hw, &desc, 1);
2687 if (ret)
2688 hns3_err(hw, "%s hardware GRO failed, ret = %d",
2689 en ? "enable" : "disable", ret);
2690
2691 return ret;
2692 }
2693
2694 int
hns3_restore_gro_conf(struct hns3_hw * hw)2695 hns3_restore_gro_conf(struct hns3_hw *hw)
2696 {
2697 uint64_t offloads;
2698 bool gro_en;
2699 int ret;
2700
2701 offloads = hw->data->dev_conf.rxmode.offloads;
2702 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2703 ret = hns3_config_gro(hw, gro_en);
2704 if (ret)
2705 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
2706 gro_en ? "enabled" : "disabled", ret);
2707
2708 return ret;
2709 }
2710
2711 static inline bool
hns3_pkt_is_tso(struct rte_mbuf * m)2712 hns3_pkt_is_tso(struct rte_mbuf *m)
2713 {
2714 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
2715 }
2716
2717 static void
hns3_set_tso(struct hns3_desc * desc,uint32_t paylen,struct rte_mbuf * rxm)2718 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm)
2719 {
2720 if (!hns3_pkt_is_tso(rxm))
2721 return;
2722
2723 if (paylen <= rxm->tso_segsz)
2724 return;
2725
2726 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
2727 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
2728 }
2729
2730 static inline void
hns3_fill_per_desc(struct hns3_desc * desc,struct rte_mbuf * rxm)2731 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
2732 {
2733 desc->addr = rte_mbuf_data_iova(rxm);
2734 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
2735 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
2736 }
2737
2738 static void
hns3_fill_first_desc(struct hns3_tx_queue * txq,struct hns3_desc * desc,struct rte_mbuf * rxm)2739 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
2740 struct rte_mbuf *rxm)
2741 {
2742 uint64_t ol_flags = rxm->ol_flags;
2743 uint32_t hdr_len;
2744 uint32_t paylen;
2745
2746 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
2747 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2748 rxm->outer_l2_len + rxm->outer_l3_len : 0;
2749 paylen = rxm->pkt_len - hdr_len;
2750 desc->tx.paylen = rte_cpu_to_le_32(paylen);
2751 hns3_set_tso(desc, paylen, rxm);
2752
2753 /*
2754 * Currently, hardware doesn't support more than two layers VLAN offload
2755 * in Tx direction based on hns3 network engine. So when the number of
2756 * VLANs in the packets represented by rxm plus the number of VLAN
2757 * offload by hardware such as PVID etc, exceeds two, the packets will
2758 * be discarded or the original VLAN of the packets will be overwitted
2759 * by hardware. When the PF PVID is enabled by calling the API function
2760 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
2761 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
2762 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
2763 * be added to the position close to the IP header when PVID is enabled.
2764 */
2765 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |
2766 PKT_TX_QINQ_PKT)) {
2767 desc->tx.ol_type_vlan_len_msec |=
2768 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
2769 if (ol_flags & PKT_TX_QINQ_PKT)
2770 desc->tx.outer_vlan_tag =
2771 rte_cpu_to_le_16(rxm->vlan_tci_outer);
2772 else
2773 desc->tx.outer_vlan_tag =
2774 rte_cpu_to_le_16(rxm->vlan_tci);
2775 }
2776
2777 if (ol_flags & PKT_TX_QINQ_PKT ||
2778 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {
2779 desc->tx.type_cs_vlan_tso_len |=
2780 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
2781 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
2782 }
2783 }
2784
2785 static inline int
hns3_tx_alloc_mbufs(struct rte_mempool * mb_pool,uint16_t nb_new_buf,struct rte_mbuf ** alloc_mbuf)2786 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
2787 struct rte_mbuf **alloc_mbuf)
2788 {
2789 #define MAX_NON_TSO_BD_PER_PKT 18
2790 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
2791 uint16_t i;
2792
2793 /* Allocate enough mbufs */
2794 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
2795 return -ENOMEM;
2796
2797 for (i = 0; i < nb_new_buf - 1; i++)
2798 pkt_segs[i]->next = pkt_segs[i + 1];
2799
2800 pkt_segs[nb_new_buf - 1]->next = NULL;
2801 pkt_segs[0]->nb_segs = nb_new_buf;
2802 *alloc_mbuf = pkt_segs[0];
2803
2804 return 0;
2805 }
2806
2807 static inline void
hns3_pktmbuf_copy_hdr(struct rte_mbuf * new_pkt,struct rte_mbuf * old_pkt)2808 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
2809 {
2810 new_pkt->ol_flags = old_pkt->ol_flags;
2811 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
2812 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
2813 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
2814 new_pkt->l2_len = old_pkt->l2_len;
2815 new_pkt->l3_len = old_pkt->l3_len;
2816 new_pkt->l4_len = old_pkt->l4_len;
2817 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
2818 new_pkt->vlan_tci = old_pkt->vlan_tci;
2819 }
2820
2821 static int
hns3_reassemble_tx_pkts(struct rte_mbuf * tx_pkt,struct rte_mbuf ** new_pkt,uint8_t max_non_tso_bd_num)2822 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt,
2823 uint8_t max_non_tso_bd_num)
2824 {
2825 struct rte_mempool *mb_pool;
2826 struct rte_mbuf *new_mbuf;
2827 struct rte_mbuf *temp_new;
2828 struct rte_mbuf *temp;
2829 uint16_t last_buf_len;
2830 uint16_t nb_new_buf;
2831 uint16_t buf_size;
2832 uint16_t buf_len;
2833 uint16_t len_s;
2834 uint16_t len_d;
2835 uint16_t len;
2836 int ret;
2837 char *s;
2838 char *d;
2839
2840 mb_pool = tx_pkt->pool;
2841 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
2842 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
2843 if (nb_new_buf > max_non_tso_bd_num)
2844 return -EINVAL;
2845
2846 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
2847 if (last_buf_len == 0)
2848 last_buf_len = buf_size;
2849
2850 /* Allocate enough mbufs */
2851 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
2852 if (ret)
2853 return ret;
2854
2855 /* Copy the original packet content to the new mbufs */
2856 temp = tx_pkt;
2857 s = rte_pktmbuf_mtod(temp, char *);
2858 len_s = rte_pktmbuf_data_len(temp);
2859 temp_new = new_mbuf;
2860 while (temp != NULL && temp_new != NULL) {
2861 d = rte_pktmbuf_mtod(temp_new, char *);
2862 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
2863 len_d = buf_len;
2864
2865 while (len_d) {
2866 len = RTE_MIN(len_s, len_d);
2867 memcpy(d, s, len);
2868 s = s + len;
2869 d = d + len;
2870 len_d = len_d - len;
2871 len_s = len_s - len;
2872
2873 if (len_s == 0) {
2874 temp = temp->next;
2875 if (temp == NULL)
2876 break;
2877 s = rte_pktmbuf_mtod(temp, char *);
2878 len_s = rte_pktmbuf_data_len(temp);
2879 }
2880 }
2881
2882 temp_new->data_len = buf_len;
2883 temp_new = temp_new->next;
2884 }
2885 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
2886
2887 /* free original mbufs */
2888 rte_pktmbuf_free(tx_pkt);
2889
2890 *new_pkt = new_mbuf;
2891
2892 return 0;
2893 }
2894
2895 static void
hns3_parse_outer_params(struct rte_mbuf * m,uint32_t * ol_type_vlan_len_msec)2896 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec)
2897 {
2898 uint32_t tmp = *ol_type_vlan_len_msec;
2899 uint64_t ol_flags = m->ol_flags;
2900
2901 /* (outer) IP header type */
2902 if (ol_flags & PKT_TX_OUTER_IPV4) {
2903 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2904 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
2905 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
2906 else
2907 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
2908 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM);
2909 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
2910 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2911 HNS3_OL3T_IPV6);
2912 }
2913 /* OL3 header size, defined in 4 bytes */
2914 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2915 m->outer_l3_len >> HNS3_L3_LEN_UNIT);
2916 *ol_type_vlan_len_msec = tmp;
2917 }
2918
2919 static int
hns3_parse_inner_params(struct rte_mbuf * m,uint32_t * ol_type_vlan_len_msec,uint32_t * type_cs_vlan_tso_len)2920 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec,
2921 uint32_t *type_cs_vlan_tso_len)
2922 {
2923 #define HNS3_NVGRE_HLEN 8
2924 uint32_t tmp_outer = *ol_type_vlan_len_msec;
2925 uint32_t tmp_inner = *type_cs_vlan_tso_len;
2926 uint64_t ol_flags = m->ol_flags;
2927 uint16_t inner_l2_len;
2928
2929 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2930 case PKT_TX_TUNNEL_VXLAN_GPE:
2931 case PKT_TX_TUNNEL_GENEVE:
2932 case PKT_TX_TUNNEL_VXLAN:
2933 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */
2934 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
2935 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP);
2936 /*
2937 * The inner l2 length of mbuf is the sum of outer l4 length,
2938 * tunneling header length and inner l2 length for a tunnel
2939 * packect. But in hns3 tx descriptor, the tunneling header
2940 * length is contained in the field of outer L4 length.
2941 * Therefore, driver need to calculate the outer L4 length and
2942 * inner L2 length.
2943 */
2944 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
2945 HNS3_TXD_L4LEN_S,
2946 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2947 HNS3_L4_LEN_UNIT);
2948
2949 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN;
2950 break;
2951 case PKT_TX_TUNNEL_GRE:
2952 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
2953 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE);
2954 /*
2955 * For NVGRE tunnel packect, the outer L4 is empty. So only
2956 * fill the NVGRE header length to the outer L4 field.
2957 */
2958 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
2959 HNS3_TXD_L4LEN_S,
2960 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT);
2961
2962 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN;
2963 break;
2964 default:
2965 /* For non UDP / GRE tunneling, drop the tunnel packet */
2966 return -EINVAL;
2967 }
2968
2969 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2970 inner_l2_len >> HNS3_L2_LEN_UNIT);
2971 /* OL2 header size, defined in 2 bytes */
2972 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2973 m->outer_l2_len >> HNS3_L2_LEN_UNIT);
2974
2975 *type_cs_vlan_tso_len = tmp_inner;
2976 *ol_type_vlan_len_msec = tmp_outer;
2977
2978 return 0;
2979 }
2980
2981 static int
hns3_parse_tunneling_params(struct hns3_tx_queue * txq,struct rte_mbuf * m,uint16_t tx_desc_id)2982 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m,
2983 uint16_t tx_desc_id)
2984 {
2985 struct hns3_desc *tx_ring = txq->tx_ring;
2986 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2987 uint32_t tmp_outer = 0;
2988 uint32_t tmp_inner = 0;
2989 int ret;
2990
2991 /*
2992 * The tunnel header is contained in the inner L2 header field of the
2993 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So,
2994 * there is a need that switching between them. To avoid multiple
2995 * calculations, the length of the L2 header include the outer and
2996 * inner, will be filled during the parsing of tunnel packects.
2997 */
2998 if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) {
2999 /*
3000 * For non tunnel type the tunnel type id is 0, so no need to
3001 * assign a value to it. Only the inner(normal) L2 header length
3002 * is assigned.
3003 */
3004 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M,
3005 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT);
3006 } else {
3007 /*
3008 * If outer csum is not offload, the outer length may be filled
3009 * with 0. And the length of the outer header is added to the
3010 * inner l2_len. It would lead a cksum error. So driver has to
3011 * calculate the header length.
3012 */
3013 if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
3014 m->outer_l2_len == 0)) {
3015 struct rte_net_hdr_lens hdr_len;
3016 (void)rte_net_get_ptype(m, &hdr_len,
3017 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK);
3018 m->outer_l3_len = hdr_len.l3_len;
3019 m->outer_l2_len = hdr_len.l2_len;
3020 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len;
3021 }
3022 hns3_parse_outer_params(m, &tmp_outer);
3023 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner);
3024 if (ret)
3025 return -EINVAL;
3026 }
3027
3028 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer);
3029 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner);
3030
3031 return 0;
3032 }
3033
3034 static void
hns3_parse_l3_cksum_params(struct rte_mbuf * m,uint32_t * type_cs_vlan_tso_len)3035 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3036 {
3037 uint64_t ol_flags = m->ol_flags;
3038 uint32_t l3_type;
3039 uint32_t tmp;
3040
3041 tmp = *type_cs_vlan_tso_len;
3042 if (ol_flags & PKT_TX_IPV4)
3043 l3_type = HNS3_L3T_IPV4;
3044 else if (ol_flags & PKT_TX_IPV6)
3045 l3_type = HNS3_L3T_IPV6;
3046 else
3047 l3_type = HNS3_L3T_NONE;
3048
3049 /* inner(/normal) L3 header size, defined in 4 bytes */
3050 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3051 m->l3_len >> HNS3_L3_LEN_UNIT);
3052
3053 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type);
3054
3055 /* Enable L3 checksum offloads */
3056 if (ol_flags & PKT_TX_IP_CKSUM)
3057 tmp |= BIT(HNS3_TXD_L3CS_B);
3058 *type_cs_vlan_tso_len = tmp;
3059 }
3060
3061 static void
hns3_parse_l4_cksum_params(struct rte_mbuf * m,uint32_t * type_cs_vlan_tso_len)3062 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3063 {
3064 uint64_t ol_flags = m->ol_flags;
3065 uint32_t tmp;
3066 /* Enable L4 checksum offloads */
3067 switch (ol_flags & (PKT_TX_L4_MASK | PKT_TX_TCP_SEG)) {
3068 case PKT_TX_TCP_CKSUM:
3069 case PKT_TX_TCP_SEG:
3070 tmp = *type_cs_vlan_tso_len;
3071 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3072 HNS3_L4T_TCP);
3073 break;
3074 case PKT_TX_UDP_CKSUM:
3075 tmp = *type_cs_vlan_tso_len;
3076 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3077 HNS3_L4T_UDP);
3078 break;
3079 case PKT_TX_SCTP_CKSUM:
3080 tmp = *type_cs_vlan_tso_len;
3081 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3082 HNS3_L4T_SCTP);
3083 break;
3084 default:
3085 return;
3086 }
3087 tmp |= BIT(HNS3_TXD_L4CS_B);
3088 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3089 m->l4_len >> HNS3_L4_LEN_UNIT);
3090 *type_cs_vlan_tso_len = tmp;
3091 }
3092
3093 static void
hns3_txd_enable_checksum(struct hns3_tx_queue * txq,struct rte_mbuf * m,uint16_t tx_desc_id)3094 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3095 uint16_t tx_desc_id)
3096 {
3097 struct hns3_desc *tx_ring = txq->tx_ring;
3098 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3099 uint32_t value = 0;
3100
3101 hns3_parse_l3_cksum_params(m, &value);
3102 hns3_parse_l4_cksum_params(m, &value);
3103
3104 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
3105 }
3106
3107 static bool
hns3_pkt_need_linearized(struct rte_mbuf * tx_pkts,uint32_t bd_num,uint32_t max_non_tso_bd_num)3108 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num,
3109 uint32_t max_non_tso_bd_num)
3110 {
3111 struct rte_mbuf *m_first = tx_pkts;
3112 struct rte_mbuf *m_last = tx_pkts;
3113 uint32_t tot_len = 0;
3114 uint32_t hdr_len;
3115 uint32_t i;
3116
3117 /*
3118 * Hardware requires that the sum of the data length of every 8
3119 * consecutive buffers is greater than MSS in hns3 network engine.
3120 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
3121 * frags greater than gso header len + mss, and the remaining 7
3122 * consecutive frags greater than MSS except the last 7 frags.
3123 */
3124 if (bd_num <= max_non_tso_bd_num)
3125 return false;
3126
3127 for (i = 0; m_last && i < max_non_tso_bd_num - 1;
3128 i++, m_last = m_last->next)
3129 tot_len += m_last->data_len;
3130
3131 if (!m_last)
3132 return true;
3133
3134 /* ensure the first 8 frags is greater than mss + header */
3135 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
3136 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
3137 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
3138 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
3139 return true;
3140
3141 /*
3142 * ensure the sum of the data length of every 7 consecutive buffer
3143 * is greater than mss except the last one.
3144 */
3145 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) {
3146 tot_len -= m_first->data_len;
3147 tot_len += m_last->data_len;
3148
3149 if (tot_len < tx_pkts->tso_segsz)
3150 return true;
3151
3152 m_first = m_first->next;
3153 m_last = m_last->next;
3154 }
3155
3156 return false;
3157 }
3158
3159 static void
hns3_outer_header_cksum_prepare(struct rte_mbuf * m)3160 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
3161 {
3162 uint64_t ol_flags = m->ol_flags;
3163 uint32_t paylen, hdr_len, l4_proto;
3164
3165 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
3166 return;
3167
3168 if (ol_flags & PKT_TX_OUTER_IPV4) {
3169 struct rte_ipv4_hdr *ipv4_hdr;
3170 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
3171 m->outer_l2_len);
3172 l4_proto = ipv4_hdr->next_proto_id;
3173 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
3174 ipv4_hdr->hdr_checksum = 0;
3175 } else {
3176 struct rte_ipv6_hdr *ipv6_hdr;
3177 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
3178 m->outer_l2_len);
3179 l4_proto = ipv6_hdr->proto;
3180 }
3181 /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */
3182 if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) {
3183 struct rte_udp_hdr *udp_hdr;
3184 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3185 hdr_len += m->outer_l2_len + m->outer_l3_len;
3186 paylen = m->pkt_len - hdr_len;
3187 if (paylen <= m->tso_segsz)
3188 return;
3189 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3190 m->outer_l2_len +
3191 m->outer_l3_len);
3192 udp_hdr->dgram_cksum = 0;
3193 }
3194 }
3195
3196 static int
hns3_check_tso_pkt_valid(struct rte_mbuf * m)3197 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
3198 {
3199 uint32_t tmp_data_len_sum = 0;
3200 uint16_t nb_buf = m->nb_segs;
3201 uint32_t paylen, hdr_len;
3202 struct rte_mbuf *m_seg;
3203 int i;
3204
3205 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
3206 return -EINVAL;
3207
3208 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3209 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
3210 m->outer_l2_len + m->outer_l3_len : 0;
3211 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
3212 return -EINVAL;
3213
3214 paylen = m->pkt_len - hdr_len;
3215 if (paylen > HNS3_MAX_BD_PAYLEN)
3216 return -EINVAL;
3217
3218 /*
3219 * The TSO header (include outer and inner L2, L3 and L4 header)
3220 * should be provided by three descriptors in maximum in hns3 network
3221 * engine.
3222 */
3223 m_seg = m;
3224 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
3225 i++, m_seg = m_seg->next) {
3226 tmp_data_len_sum += m_seg->data_len;
3227 }
3228
3229 if (hdr_len > tmp_data_len_sum)
3230 return -EINVAL;
3231
3232 return 0;
3233 }
3234
3235 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3236 static inline int
hns3_vld_vlan_chk(struct hns3_tx_queue * txq,struct rte_mbuf * m)3237 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
3238 {
3239 struct rte_ether_hdr *eh;
3240 struct rte_vlan_hdr *vh;
3241
3242 if (!txq->pvid_sw_shift_en)
3243 return 0;
3244
3245 /*
3246 * Due to hardware limitations, we only support two-layer VLAN hardware
3247 * offload in Tx direction based on hns3 network engine, so when PVID is
3248 * enabled, QinQ insert is no longer supported.
3249 * And when PVID is enabled, in the following two cases:
3250 * i) packets with more than two VLAN tags.
3251 * ii) packets with one VLAN tag while the hardware VLAN insert is
3252 * enabled.
3253 * The packets will be regarded as abnormal packets and discarded by
3254 * hardware in Tx direction. For debugging purposes, a validation check
3255 * for these types of packets is added to the '.tx_pkt_prepare' ops
3256 * implementation function named hns3_prep_pkts to inform users that
3257 * these packets will be discarded.
3258 */
3259 if (m->ol_flags & PKT_TX_QINQ_PKT)
3260 return -EINVAL;
3261
3262 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
3263 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
3264 if (m->ol_flags & PKT_TX_VLAN_PKT)
3265 return -EINVAL;
3266
3267 /* Ensure the incoming packet is not a QinQ packet */
3268 vh = (struct rte_vlan_hdr *)(eh + 1);
3269 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
3270 return -EINVAL;
3271 }
3272
3273 return 0;
3274 }
3275 #endif
3276
3277 static int
hns3_prep_pkt_proc(struct hns3_tx_queue * tx_queue,struct rte_mbuf * m)3278 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3279 {
3280 int ret;
3281
3282 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3283 ret = rte_validate_tx_offload(m);
3284 if (ret != 0) {
3285 rte_errno = -ret;
3286 return ret;
3287 }
3288
3289 ret = hns3_vld_vlan_chk(tx_queue, m);
3290 if (ret != 0) {
3291 rte_errno = EINVAL;
3292 return ret;
3293 }
3294 #endif
3295 if (hns3_pkt_is_tso(m)) {
3296 if (hns3_pkt_need_linearized(m, m->nb_segs,
3297 tx_queue->max_non_tso_bd_num) ||
3298 hns3_check_tso_pkt_valid(m)) {
3299 rte_errno = EINVAL;
3300 return -EINVAL;
3301 }
3302
3303 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) {
3304 /*
3305 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means
3306 * hardware support recalculate the TCP pseudo header
3307 * checksum of packets that need TSO, so network driver
3308 * software not need to recalculate it.
3309 */
3310 hns3_outer_header_cksum_prepare(m);
3311 return 0;
3312 }
3313 }
3314
3315 ret = rte_net_intel_cksum_prepare(m);
3316 if (ret != 0) {
3317 rte_errno = -ret;
3318 return ret;
3319 }
3320
3321 hns3_outer_header_cksum_prepare(m);
3322
3323 return 0;
3324 }
3325
3326 uint16_t
hns3_prep_pkts(__rte_unused void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)3327 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3328 uint16_t nb_pkts)
3329 {
3330 struct rte_mbuf *m;
3331 uint16_t i;
3332
3333 for (i = 0; i < nb_pkts; i++) {
3334 m = tx_pkts[i];
3335 if (hns3_prep_pkt_proc(tx_queue, m))
3336 return i;
3337 }
3338
3339 return i;
3340 }
3341
3342 static int
hns3_parse_cksum(struct hns3_tx_queue * txq,uint16_t tx_desc_id,struct rte_mbuf * m)3343 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3344 struct rte_mbuf *m)
3345 {
3346 struct hns3_desc *tx_ring = txq->tx_ring;
3347 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3348
3349 /* Enable checksum offloading */
3350 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) {
3351 /* Fill in tunneling parameters if necessary */
3352 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) {
3353 txq->unsupported_tunnel_pkt_cnt++;
3354 return -EINVAL;
3355 }
3356
3357 hns3_txd_enable_checksum(txq, m, tx_desc_id);
3358 } else {
3359 /* clear the control bit */
3360 desc->tx.type_cs_vlan_tso_len = 0;
3361 desc->tx.ol_type_vlan_len_msec = 0;
3362 }
3363
3364 return 0;
3365 }
3366
3367 static int
hns3_check_non_tso_pkt(uint16_t nb_buf,struct rte_mbuf ** m_seg,struct rte_mbuf * tx_pkt,struct hns3_tx_queue * txq)3368 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
3369 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
3370 {
3371 uint8_t max_non_tso_bd_num;
3372 struct rte_mbuf *new_pkt;
3373 int ret;
3374
3375 if (hns3_pkt_is_tso(*m_seg))
3376 return 0;
3377
3378 /*
3379 * If packet length is greater than HNS3_MAX_FRAME_LEN
3380 * driver support, the packet will be ignored.
3381 */
3382 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
3383 txq->over_length_pkt_cnt++;
3384 return -EINVAL;
3385 }
3386
3387 max_non_tso_bd_num = txq->max_non_tso_bd_num;
3388 if (unlikely(nb_buf > max_non_tso_bd_num)) {
3389 txq->exceed_limit_bd_pkt_cnt++;
3390 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt,
3391 max_non_tso_bd_num);
3392 if (ret) {
3393 txq->exceed_limit_bd_reassem_fail++;
3394 return ret;
3395 }
3396 *m_seg = new_pkt;
3397 }
3398
3399 return 0;
3400 }
3401
3402 static inline void
hns3_tx_free_buffer_simple(struct hns3_tx_queue * txq)3403 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
3404 {
3405 struct hns3_entry *tx_entry;
3406 struct hns3_desc *desc;
3407 uint16_t tx_next_clean;
3408 int i;
3409
3410 while (1) {
3411 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
3412 break;
3413
3414 /*
3415 * All mbufs can be released only when the VLD bits of all
3416 * descriptors in a batch are cleared.
3417 */
3418 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
3419 txq->nb_tx_desc;
3420 desc = &txq->tx_ring[tx_next_clean];
3421 for (i = 0; i < txq->tx_rs_thresh; i++) {
3422 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
3423 BIT(HNS3_TXD_VLD_B))
3424 return;
3425 desc--;
3426 }
3427
3428 tx_entry = &txq->sw_ring[txq->next_to_clean];
3429
3430 for (i = 0; i < txq->tx_rs_thresh; i++)
3431 rte_prefetch0((tx_entry + i)->mbuf);
3432 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
3433 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
3434 tx_entry->mbuf = NULL;
3435 }
3436
3437 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
3438 txq->tx_bd_ready += txq->tx_rs_thresh;
3439 }
3440 }
3441
3442 static inline void
hns3_tx_backup_1mbuf(struct hns3_entry * tx_entry,struct rte_mbuf ** pkts)3443 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3444 {
3445 tx_entry->mbuf = pkts[0];
3446 }
3447
3448 static inline void
hns3_tx_backup_4mbuf(struct hns3_entry * tx_entry,struct rte_mbuf ** pkts)3449 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3450 {
3451 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
3452 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
3453 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
3454 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
3455 }
3456
3457 static inline void
hns3_tx_setup_4bd(struct hns3_desc * txdp,struct rte_mbuf ** pkts)3458 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3459 {
3460 #define PER_LOOP_NUM 4
3461 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3462 uint64_t dma_addr;
3463 uint32_t i;
3464
3465 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
3466 dma_addr = rte_mbuf_data_iova(*pkts);
3467 txdp->addr = rte_cpu_to_le_64(dma_addr);
3468 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3469 txdp->tx.paylen = 0;
3470 txdp->tx.type_cs_vlan_tso_len = 0;
3471 txdp->tx.ol_type_vlan_len_msec = 0;
3472 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3473 }
3474 }
3475
3476 static inline void
hns3_tx_setup_1bd(struct hns3_desc * txdp,struct rte_mbuf ** pkts)3477 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3478 {
3479 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3480 uint64_t dma_addr;
3481
3482 dma_addr = rte_mbuf_data_iova(*pkts);
3483 txdp->addr = rte_cpu_to_le_64(dma_addr);
3484 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3485 txdp->tx.paylen = 0;
3486 txdp->tx.type_cs_vlan_tso_len = 0;
3487 txdp->tx.ol_type_vlan_len_msec = 0;
3488 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3489 }
3490
3491 static inline void
hns3_tx_fill_hw_ring(struct hns3_tx_queue * txq,struct rte_mbuf ** pkts,uint16_t nb_pkts)3492 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
3493 struct rte_mbuf **pkts,
3494 uint16_t nb_pkts)
3495 {
3496 #define PER_LOOP_NUM 4
3497 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
3498 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
3499 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
3500 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
3501 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
3502 uint32_t i;
3503
3504 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
3505 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
3506 hns3_tx_setup_4bd(txdp + i, pkts + i);
3507 }
3508 if (unlikely(leftover > 0)) {
3509 for (i = 0; i < leftover; i++) {
3510 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
3511 pkts + mainpart + i);
3512 hns3_tx_setup_1bd(txdp + mainpart + i,
3513 pkts + mainpart + i);
3514 }
3515 }
3516 }
3517
3518 uint16_t
hns3_xmit_pkts_simple(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)3519 hns3_xmit_pkts_simple(void *tx_queue,
3520 struct rte_mbuf **tx_pkts,
3521 uint16_t nb_pkts)
3522 {
3523 struct hns3_tx_queue *txq = tx_queue;
3524 uint16_t nb_tx = 0;
3525
3526 hns3_tx_free_buffer_simple(txq);
3527
3528 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
3529 if (unlikely(nb_pkts == 0)) {
3530 if (txq->tx_bd_ready == 0)
3531 txq->queue_full_cnt++;
3532 return 0;
3533 }
3534
3535 txq->tx_bd_ready -= nb_pkts;
3536 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
3537 nb_tx = txq->nb_tx_desc - txq->next_to_use;
3538 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
3539 txq->next_to_use = 0;
3540 }
3541
3542 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
3543 txq->next_to_use += nb_pkts - nb_tx;
3544
3545 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
3546
3547 return nb_pkts;
3548 }
3549
3550 uint16_t
hns3_xmit_pkts(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)3551 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
3552 {
3553 struct hns3_tx_queue *txq = tx_queue;
3554 struct hns3_entry *tx_bak_pkt;
3555 struct hns3_desc *tx_ring;
3556 struct rte_mbuf *tx_pkt;
3557 struct rte_mbuf *m_seg;
3558 struct hns3_desc *desc;
3559 uint32_t nb_hold = 0;
3560 uint16_t tx_next_use;
3561 uint16_t tx_pkt_num;
3562 uint16_t tx_bd_max;
3563 uint16_t nb_buf;
3564 uint16_t nb_tx;
3565 uint16_t i;
3566
3567 /* free useless buffer */
3568 hns3_tx_free_useless_buffer(txq);
3569
3570 tx_next_use = txq->next_to_use;
3571 tx_bd_max = txq->nb_tx_desc;
3572 tx_pkt_num = nb_pkts;
3573 tx_ring = txq->tx_ring;
3574
3575 /* send packets */
3576 tx_bak_pkt = &txq->sw_ring[tx_next_use];
3577 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
3578 tx_pkt = *tx_pkts++;
3579
3580 nb_buf = tx_pkt->nb_segs;
3581
3582 if (nb_buf > txq->tx_bd_ready) {
3583 txq->queue_full_cnt++;
3584 if (nb_tx == 0)
3585 return 0;
3586
3587 goto end_of_tx;
3588 }
3589
3590 /*
3591 * If packet length is less than minimum packet length supported
3592 * by hardware in Tx direction, driver need to pad it to avoid
3593 * error.
3594 */
3595 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
3596 txq->min_tx_pkt_len)) {
3597 uint16_t add_len;
3598 char *appended;
3599
3600 add_len = txq->min_tx_pkt_len -
3601 rte_pktmbuf_pkt_len(tx_pkt);
3602 appended = rte_pktmbuf_append(tx_pkt, add_len);
3603 if (appended == NULL) {
3604 txq->pkt_padding_fail_cnt++;
3605 break;
3606 }
3607
3608 memset(appended, 0, add_len);
3609 }
3610
3611 m_seg = tx_pkt;
3612
3613 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
3614 goto end_of_tx;
3615
3616 if (hns3_parse_cksum(txq, tx_next_use, m_seg))
3617 goto end_of_tx;
3618
3619 i = 0;
3620 desc = &tx_ring[tx_next_use];
3621
3622 /*
3623 * If the packet is divided into multiple Tx Buffer Descriptors,
3624 * only need to fill vlan, paylen and tso into the first Tx
3625 * Buffer Descriptor.
3626 */
3627 hns3_fill_first_desc(txq, desc, m_seg);
3628
3629 do {
3630 desc = &tx_ring[tx_next_use];
3631 /*
3632 * Fill valid bits, DMA address and data length for each
3633 * Tx Buffer Descriptor.
3634 */
3635 hns3_fill_per_desc(desc, m_seg);
3636 tx_bak_pkt->mbuf = m_seg;
3637 m_seg = m_seg->next;
3638 tx_next_use++;
3639 tx_bak_pkt++;
3640 if (tx_next_use >= tx_bd_max) {
3641 tx_next_use = 0;
3642 tx_bak_pkt = txq->sw_ring;
3643 }
3644
3645 i++;
3646 } while (m_seg != NULL);
3647
3648 /* Add end flag for the last Tx Buffer Descriptor */
3649 desc->tx.tp_fe_sc_vld_ra_ri |=
3650 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
3651
3652 nb_hold += i;
3653 txq->next_to_use = tx_next_use;
3654 txq->tx_bd_ready -= i;
3655 }
3656
3657 end_of_tx:
3658
3659 if (likely(nb_tx))
3660 hns3_write_reg_opt(txq->io_tail_reg, nb_hold);
3661
3662 return nb_tx;
3663 }
3664
3665 int __rte_weak
hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev * dev)3666 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
3667 {
3668 return -ENOTSUP;
3669 }
3670
3671 uint16_t __rte_weak
hns3_xmit_pkts_vec(__rte_unused void * tx_queue,__rte_unused struct rte_mbuf ** tx_pkts,__rte_unused uint16_t nb_pkts)3672 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
3673 __rte_unused struct rte_mbuf **tx_pkts,
3674 __rte_unused uint16_t nb_pkts)
3675 {
3676 return 0;
3677 }
3678
3679 uint16_t __rte_weak
hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,struct rte_mbuf __rte_unused ** tx_pkts,uint16_t __rte_unused nb_pkts)3680 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,
3681 struct rte_mbuf __rte_unused **tx_pkts,
3682 uint16_t __rte_unused nb_pkts)
3683 {
3684 return 0;
3685 }
3686
3687 int
hns3_tx_burst_mode_get(struct rte_eth_dev * dev,__rte_unused uint16_t queue_id,struct rte_eth_burst_mode * mode)3688 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3689 struct rte_eth_burst_mode *mode)
3690 {
3691 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3692 const char *info = NULL;
3693
3694 if (pkt_burst == hns3_xmit_pkts_simple)
3695 info = "Scalar Simple";
3696 else if (pkt_burst == hns3_xmit_pkts)
3697 info = "Scalar";
3698 else if (pkt_burst == hns3_xmit_pkts_vec)
3699 info = "Vector Neon";
3700 else if (pkt_burst == hns3_xmit_pkts_vec_sve)
3701 info = "Vector Sve";
3702
3703 if (info == NULL)
3704 return -EINVAL;
3705
3706 snprintf(mode->info, sizeof(mode->info), "%s", info);
3707
3708 return 0;
3709 }
3710
3711 static eth_tx_burst_t
hns3_get_tx_function(struct rte_eth_dev * dev,eth_tx_prep_t * prep)3712 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
3713 {
3714 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
3715 struct hns3_adapter *hns = dev->data->dev_private;
3716
3717 if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) {
3718 *prep = NULL;
3719 return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve :
3720 hns3_xmit_pkts_vec;
3721 }
3722
3723 if (hns->tx_simple_allowed &&
3724 offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) {
3725 *prep = NULL;
3726 return hns3_xmit_pkts_simple;
3727 }
3728
3729 *prep = hns3_prep_pkts;
3730 return hns3_xmit_pkts;
3731 }
3732
3733 static uint16_t
hns3_dummy_rxtx_burst(void * dpdk_txq __rte_unused,struct rte_mbuf ** pkts __rte_unused,uint16_t pkts_n __rte_unused)3734 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
3735 struct rte_mbuf **pkts __rte_unused,
3736 uint16_t pkts_n __rte_unused)
3737 {
3738 return 0;
3739 }
3740
hns3_set_rxtx_function(struct rte_eth_dev * eth_dev)3741 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
3742 {
3743 struct hns3_adapter *hns = eth_dev->data->dev_private;
3744 eth_tx_prep_t prep = NULL;
3745
3746 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
3747 rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
3748 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
3749 eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep);
3750 eth_dev->tx_pkt_prepare = prep;
3751 } else {
3752 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
3753 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
3754 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
3755 }
3756 }
3757
3758 void
hns3_rxq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_rxq_info * qinfo)3759 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3760 struct rte_eth_rxq_info *qinfo)
3761 {
3762 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
3763
3764 qinfo->mp = rxq->mb_pool;
3765 qinfo->nb_desc = rxq->nb_rx_desc;
3766 qinfo->scattered_rx = dev->data->scattered_rx;
3767 /* Report the HW Rx buffer length to user */
3768 qinfo->rx_buf_size = rxq->rx_buf_len;
3769
3770 /*
3771 * If there are no available Rx buffer descriptors, incoming packets
3772 * are always dropped by hardware based on hns3 network engine.
3773 */
3774 qinfo->conf.rx_drop_en = 1;
3775 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
3776 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3777 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3778 }
3779
3780 void
hns3_txq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_txq_info * qinfo)3781 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3782 struct rte_eth_txq_info *qinfo)
3783 {
3784 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
3785
3786 qinfo->nb_desc = txq->nb_tx_desc;
3787 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
3788 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3789 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3790 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3791 }
3792
3793 int
hns3_dev_rx_queue_start(struct rte_eth_dev * dev,uint16_t rx_queue_id)3794 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3795 {
3796 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3797 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3798 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3799 int ret;
3800
3801 if (!hns3_dev_indep_txrx_supported(hw))
3802 return -ENOTSUP;
3803
3804 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX);
3805 if (ret) {
3806 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.",
3807 rx_queue_id, ret);
3808 return ret;
3809 }
3810
3811 ret = hns3_init_rxq(hns, rx_queue_id);
3812 if (ret) {
3813 hns3_err(hw, "fail to init Rx queue %u, ret = %d.",
3814 rx_queue_id, ret);
3815 return ret;
3816 }
3817
3818 hns3_enable_rxq(rxq, true);
3819 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3820
3821 return ret;
3822 }
3823
3824 static void
hns3_reset_sw_rxq(struct hns3_rx_queue * rxq)3825 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq)
3826 {
3827 rxq->next_to_use = 0;
3828 rxq->rx_rearm_start = 0;
3829 rxq->rx_free_hold = 0;
3830 rxq->rx_rearm_nb = 0;
3831 rxq->pkt_first_seg = NULL;
3832 rxq->pkt_last_seg = NULL;
3833 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc));
3834 hns3_rxq_vec_setup(rxq);
3835 }
3836
3837 int
hns3_dev_rx_queue_stop(struct rte_eth_dev * dev,uint16_t rx_queue_id)3838 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3839 {
3840 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3841 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3842
3843 if (!hns3_dev_indep_txrx_supported(hw))
3844 return -ENOTSUP;
3845
3846 hns3_enable_rxq(rxq, false);
3847
3848 hns3_rx_queue_release_mbufs(rxq);
3849
3850 hns3_reset_sw_rxq(rxq);
3851 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3852
3853 return 0;
3854 }
3855
3856 int
hns3_dev_tx_queue_start(struct rte_eth_dev * dev,uint16_t tx_queue_id)3857 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3858 {
3859 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3860 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3861 int ret;
3862
3863 if (!hns3_dev_indep_txrx_supported(hw))
3864 return -ENOTSUP;
3865
3866 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX);
3867 if (ret) {
3868 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.",
3869 tx_queue_id, ret);
3870 return ret;
3871 }
3872
3873 hns3_init_txq(txq);
3874 hns3_enable_txq(txq, true);
3875 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3876
3877 return ret;
3878 }
3879
3880 int
hns3_dev_tx_queue_stop(struct rte_eth_dev * dev,uint16_t tx_queue_id)3881 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3882 {
3883 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3884 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3885
3886 if (!hns3_dev_indep_txrx_supported(hw))
3887 return -ENOTSUP;
3888
3889 hns3_enable_txq(txq, false);
3890 hns3_tx_queue_release_mbufs(txq);
3891 /*
3892 * All the mbufs in sw_ring are released and all the pointers in sw_ring
3893 * are set to NULL. If this queue is still called by upper layer,
3894 * residual SW status of this txq may cause these pointers in sw_ring
3895 * which have been set to NULL to be released again. To avoid it,
3896 * reinit the txq.
3897 */
3898 hns3_init_txq(txq);
3899 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3900
3901 return 0;
3902 }
3903
3904 uint32_t
hns3_rx_queue_count(struct rte_eth_dev * dev,uint16_t rx_queue_id)3905 hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3906 {
3907 /*
3908 * Number of BDs that have been processed by the driver
3909 * but have not been notified to the hardware.
3910 */
3911 uint32_t driver_hold_bd_num;
3912 struct hns3_rx_queue *rxq;
3913 uint32_t fbd_num;
3914
3915 rxq = dev->data->rx_queues[rx_queue_id];
3916 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG);
3917 if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
3918 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
3919 driver_hold_bd_num = rxq->rx_rearm_nb;
3920 else
3921 driver_hold_bd_num = rxq->rx_free_hold;
3922
3923 if (fbd_num <= driver_hold_bd_num)
3924 return 0;
3925 else
3926 return fbd_num - driver_hold_bd_num;
3927 }
3928