1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18 #include "MCTargetDesc/MipsABIInfo.h" 19 #include "MCTargetDesc/MipsBaseInfo.h" 20 #include "MCTargetDesc/MipsMCTargetDesc.h" 21 #include "Mips.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/ISDOpcodes.h" 24 #include "llvm/CodeGen/MachineMemOperand.h" 25 #include "llvm/CodeGen/SelectionDAG.h" 26 #include "llvm/CodeGen/SelectionDAGNodes.h" 27 #include "llvm/CodeGen/TargetLowering.h" 28 #include "llvm/CodeGen/ValueTypes.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/InlineAsm.h" 31 #include "llvm/IR/Type.h" 32 #include "llvm/Support/MachineValueType.h" 33 #include "llvm/Target/TargetMachine.h" 34 #include <algorithm> 35 #include <cassert> 36 #include <deque> 37 #include <string> 38 #include <utility> 39 #include <vector> 40 41 namespace llvm { 42 43 class Argument; 44 class CCState; 45 class CCValAssign; 46 class FastISel; 47 class FunctionLoweringInfo; 48 class MachineBasicBlock; 49 class MachineFrameInfo; 50 class MachineInstr; 51 class MipsCCState; 52 class MipsFunctionInfo; 53 class MipsSubtarget; 54 class MipsTargetMachine; 55 class TargetLibraryInfo; 56 class TargetRegisterClass; 57 58 namespace MipsISD { 59 60 enum NodeType : unsigned { 61 // Start the numbering from where ISD NodeType finishes. 62 FIRST_NUMBER = ISD::BUILTIN_OP_END, 63 64 // Jump and link (call) 65 JmpLink, 66 67 // Tail call 68 TailCall, 69 70 // Get the Highest (63-48) 16 bits from a 64-bit immediate 71 Highest, 72 73 // Get the Higher (47-32) 16 bits from a 64-bit immediate 74 Higher, 75 76 // Get the High 16 bits from a 32/64-bit immediate 77 // No relation with Mips Hi register 78 Hi, 79 80 // Get the Lower 16 bits from a 32/64-bit immediate 81 // No relation with Mips Lo register 82 Lo, 83 84 // Get the High 16 bits from a 32 bit immediate for accessing the GOT. 85 GotHi, 86 87 // Get the High 16 bits from a 32-bit immediate for accessing TLS. 88 TlsHi, 89 90 // Handle gp_rel (small data/bss sections) relocation. 91 GPRel, 92 93 // Thread Pointer 94 ThreadPointer, 95 96 // Vector Floating Point Multiply and Subtract 97 FMS, 98 99 // Floating Point Branch Conditional 100 FPBrcond, 101 102 // Floating Point Compare 103 FPCmp, 104 105 // Floating point select 106 FSELECT, 107 108 // Node used to generate an MTC1 i32 to f64 instruction 109 MTC1_D64, 110 111 // Floating Point Conditional Moves 112 CMovFP_T, 113 CMovFP_F, 114 115 // FP-to-int truncation node. 116 TruncIntFP, 117 118 // Return 119 Ret, 120 121 // Interrupt, exception, error trap Return 122 ERet, 123 124 // Software Exception Return. 125 EH_RETURN, 126 127 // Node used to extract integer from accumulator. 128 MFHI, 129 MFLO, 130 131 // Node used to insert integers to accumulator. 132 MTLOHI, 133 134 // Mult nodes. 135 Mult, 136 Multu, 137 138 // MAdd/Sub nodes 139 MAdd, 140 MAddu, 141 MSub, 142 MSubu, 143 144 // DivRem(u) 145 DivRem, 146 DivRemU, 147 DivRem16, 148 DivRemU16, 149 150 BuildPairF64, 151 ExtractElementF64, 152 153 Wrapper, 154 155 DynAlloc, 156 157 Sync, 158 159 Ext, 160 Ins, 161 CIns, 162 163 // EXTR.W instrinsic nodes. 164 EXTP, 165 EXTPDP, 166 EXTR_S_H, 167 EXTR_W, 168 EXTR_R_W, 169 EXTR_RS_W, 170 SHILO, 171 MTHLIP, 172 173 // DPA.W intrinsic nodes. 174 MULSAQ_S_W_PH, 175 MAQ_S_W_PHL, 176 MAQ_S_W_PHR, 177 MAQ_SA_W_PHL, 178 MAQ_SA_W_PHR, 179 DPAU_H_QBL, 180 DPAU_H_QBR, 181 DPSU_H_QBL, 182 DPSU_H_QBR, 183 DPAQ_S_W_PH, 184 DPSQ_S_W_PH, 185 DPAQ_SA_L_W, 186 DPSQ_SA_L_W, 187 DPA_W_PH, 188 DPS_W_PH, 189 DPAQX_S_W_PH, 190 DPAQX_SA_W_PH, 191 DPAX_W_PH, 192 DPSX_W_PH, 193 DPSQX_S_W_PH, 194 DPSQX_SA_W_PH, 195 MULSA_W_PH, 196 197 MULT, 198 MULTU, 199 MADD_DSP, 200 MADDU_DSP, 201 MSUB_DSP, 202 MSUBU_DSP, 203 204 // DSP shift nodes. 205 SHLL_DSP, 206 SHRA_DSP, 207 SHRL_DSP, 208 209 // DSP setcc and select_cc nodes. 210 SETCC_DSP, 211 SELECT_CC_DSP, 212 213 // Vector comparisons. 214 // These take a vector and return a boolean. 215 VALL_ZERO, 216 VANY_ZERO, 217 VALL_NONZERO, 218 VANY_NONZERO, 219 220 // These take a vector and return a vector bitmask. 221 VCEQ, 222 VCLE_S, 223 VCLE_U, 224 VCLT_S, 225 VCLT_U, 226 227 // Vector Shuffle with mask as an operand 228 VSHF, // Generic shuffle 229 SHF, // 4-element set shuffle. 230 ILVEV, // Interleave even elements 231 ILVOD, // Interleave odd elements 232 ILVL, // Interleave left elements 233 ILVR, // Interleave right elements 234 PCKEV, // Pack even elements 235 PCKOD, // Pack odd elements 236 237 // Vector Lane Copy 238 INSVE, // Copy element from one vector to another 239 240 // Combined (XOR (OR $a, $b), -1) 241 VNOR, 242 243 // Extended vector element extraction 244 VEXTRACT_SEXT_ELT, 245 VEXTRACT_ZEXT_ELT, 246 247 // Load/Store Left/Right nodes. 248 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 249 LWR, 250 SWL, 251 SWR, 252 LDL, 253 LDR, 254 SDL, 255 SDR 256 }; 257 258 } // ene namespace MipsISD 259 260 //===--------------------------------------------------------------------===// 261 // TargetLowering Implementation 262 //===--------------------------------------------------------------------===// 263 264 class MipsTargetLowering : public TargetLowering { 265 bool isMicroMips; 266 267 public: 268 explicit MipsTargetLowering(const MipsTargetMachine &TM, 269 const MipsSubtarget &STI); 270 271 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 272 const MipsSubtarget &STI); 273 274 /// createFastISel - This method returns a target specific FastISel object, 275 /// or null if the target does not support "fast" ISel. 276 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 277 const TargetLibraryInfo *libInfo) const override; 278 getScalarShiftAmountTy(const DataLayout &,EVT)279 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 280 return MVT::i32; 281 } 282 283 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, 284 ISD::NodeType) const override; 285 286 bool isCheapToSpeculateCttz() const override; 287 bool isCheapToSpeculateCtlz() const override; 288 289 /// Return the register type for a given MVT, ensuring vectors are treated 290 /// as a series of gpr sized integers. 291 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 292 EVT VT) const override; 293 294 /// Return the number of registers for a given MVT, ensuring vectors are 295 /// treated as a series of gpr sized integers. 296 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 297 CallingConv::ID CC, 298 EVT VT) const override; 299 300 /// Break down vectors to the correct number of gpr sized integers. 301 unsigned getVectorTypeBreakdownForCallingConv( 302 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 303 unsigned &NumIntermediates, MVT &RegisterVT) const override; 304 305 /// Return the correct alignment for the current calling convention. getABIAlignmentForCallingConv(Type * ArgTy,DataLayout DL)306 unsigned getABIAlignmentForCallingConv(Type *ArgTy, 307 DataLayout DL) const override { 308 if (ArgTy->isVectorTy()) 309 return std::min(DL.getABITypeAlignment(ArgTy), 8U); 310 return DL.getABITypeAlignment(ArgTy); 311 } 312 getExtendForAtomicOps()313 ISD::NodeType getExtendForAtomicOps() const override { 314 return ISD::SIGN_EXTEND; 315 } 316 317 void LowerOperationWrapper(SDNode *N, 318 SmallVectorImpl<SDValue> &Results, 319 SelectionDAG &DAG) const override; 320 321 /// LowerOperation - Provide custom lowering hooks for some operations. 322 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 323 324 /// ReplaceNodeResults - Replace the results of node with an illegal result 325 /// type with new values built out of custom code. 326 /// 327 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 328 SelectionDAG &DAG) const override; 329 330 /// getTargetNodeName - This method returns the name of a target specific 331 // DAG node. 332 const char *getTargetNodeName(unsigned Opcode) const override; 333 334 /// getSetCCResultType - get the ISD::SETCC result ValueType 335 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 336 EVT VT) const override; 337 338 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 339 340 MachineBasicBlock * 341 EmitInstrWithCustomInserter(MachineInstr &MI, 342 MachineBasicBlock *MBB) const override; 343 344 void AdjustInstrPostInstrSelection(MachineInstr &MI, 345 SDNode *Node) const override; 346 347 void HandleByVal(CCState *, unsigned &, unsigned) const override; 348 349 unsigned getRegisterByName(const char* RegName, EVT VT, 350 SelectionDAG &DAG) const override; 351 352 /// If a physical register, this returns the register that receives the 353 /// exception address on entry to an EH pad. 354 unsigned getExceptionPointerRegister(const Constant * PersonalityFn)355 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 356 return ABI.IsN64() ? Mips::A0_64 : Mips::A0; 357 } 358 359 /// If a physical register, this returns the register that receives the 360 /// exception typeid on entry to a landing pad. 361 unsigned getExceptionSelectorRegister(const Constant * PersonalityFn)362 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 363 return ABI.IsN64() ? Mips::A1_64 : Mips::A1; 364 } 365 366 /// Returns true if a cast between SrcAS and DestAS is a noop. isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS)367 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 368 // Mips doesn't have any special address spaces so we just reserve 369 // the first 256 for software use (e.g. OpenCL) and treat casts 370 // between them as noops. 371 return SrcAS < 256 && DestAS < 256; 372 } 373 isJumpTableRelative()374 bool isJumpTableRelative() const override { 375 return getTargetMachine().isPositionIndependent(); 376 } 377 378 CCAssignFn *CCAssignFnForCall() const; 379 380 CCAssignFn *CCAssignFnForReturn() const; 381 382 protected: 383 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 384 385 // This method creates the following nodes, which are necessary for 386 // computing a local symbol's address: 387 // 388 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 389 template <class NodeTy> getAddrLocal(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,bool IsN32OrN64)390 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, 391 bool IsN32OrN64) const { 392 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 393 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 394 getTargetNode(N, Ty, DAG, GOTFlag)); 395 SDValue Load = 396 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 397 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 398 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 399 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 400 getTargetNode(N, Ty, DAG, LoFlag)); 401 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 402 } 403 404 // This method creates the following nodes, which are necessary for 405 // computing a global symbol's address: 406 // 407 // (load (wrapper $gp, %got(sym))) 408 template <class NodeTy> getAddrGlobal(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned Flag,SDValue Chain,const MachinePointerInfo & PtrInfo)409 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, 410 unsigned Flag, SDValue Chain, 411 const MachinePointerInfo &PtrInfo) const { 412 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 413 getTargetNode(N, Ty, DAG, Flag)); 414 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo); 415 } 416 417 // This method creates the following nodes, which are necessary for 418 // computing a global symbol's address in large-GOT mode: 419 // 420 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 421 template <class NodeTy> getAddrGlobalLargeGOT(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned HiFlag,unsigned LoFlag,SDValue Chain,const MachinePointerInfo & PtrInfo)422 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, 423 SelectionDAG &DAG, unsigned HiFlag, 424 unsigned LoFlag, SDValue Chain, 425 const MachinePointerInfo &PtrInfo) const { 426 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty, 427 getTargetNode(N, Ty, DAG, HiFlag)); 428 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 429 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 430 getTargetNode(N, Ty, DAG, LoFlag)); 431 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo); 432 } 433 434 // This method creates the following nodes, which are necessary for 435 // computing a symbol's address in non-PIC mode: 436 // 437 // (add %hi(sym), %lo(sym)) 438 // 439 // This method covers O32, N32 and N64 in sym32 mode. 440 template <class NodeTy> getAddrNonPIC(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG)441 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, 442 SelectionDAG &DAG) const { 443 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 444 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 445 return DAG.getNode(ISD::ADD, DL, Ty, 446 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 447 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 448 } 449 450 // This method creates the following nodes, which are necessary for 451 // computing a symbol's address in non-PIC mode for N64. 452 // 453 // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)), 454 // 16), %lo(%sym)) 455 // 456 // FIXME: This method is not efficent for (micro)MIPS64R6. 457 template <class NodeTy> getAddrNonPICSym64(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG)458 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, 459 SelectionDAG &DAG) const { 460 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 461 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 462 463 SDValue Highest = 464 DAG.getNode(MipsISD::Highest, DL, Ty, 465 getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST)); 466 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER); 467 SDValue HigherPart = 468 DAG.getNode(ISD::ADD, DL, Ty, Highest, 469 DAG.getNode(MipsISD::Higher, DL, Ty, Higher)); 470 SDValue Cst = DAG.getConstant(16, DL, MVT::i32); 471 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst); 472 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift, 473 DAG.getNode(MipsISD::Hi, DL, Ty, Hi)); 474 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); 475 476 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, 477 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 478 } 479 480 // This method creates the following nodes, which are necessary for 481 // computing a symbol's address using gp-relative addressing: 482 // 483 // (add $gp, %gp_rel(sym)) 484 template <class NodeTy> getAddrGPRel(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,bool IsN64)485 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, 486 SelectionDAG &DAG, bool IsN64) const { 487 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); 488 return DAG.getNode( 489 ISD::ADD, DL, Ty, 490 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty), 491 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel)); 492 } 493 494 /// This function fills Ops, which is the list of operands that will later 495 /// be used when a function call node is created. It also generates 496 /// copyToReg nodes to set up argument registers. 497 virtual void 498 getOpndList(SmallVectorImpl<SDValue> &Ops, 499 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 500 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 501 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 502 SDValue Chain) const; 503 504 protected: 505 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 506 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 507 508 // Subtarget Info 509 const MipsSubtarget &Subtarget; 510 // Cache the ABI from the TargetMachine, we use it everywhere. 511 const MipsABIInfo &ABI; 512 513 private: 514 // Create a TargetGlobalAddress node. 515 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 516 unsigned Flag) const; 517 518 // Create a TargetExternalSymbol node. 519 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 520 unsigned Flag) const; 521 522 // Create a TargetBlockAddress node. 523 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 524 unsigned Flag) const; 525 526 // Create a TargetJumpTable node. 527 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 528 unsigned Flag) const; 529 530 // Create a TargetConstantPool node. 531 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 532 unsigned Flag) const; 533 534 // Lower Operand helpers 535 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 536 CallingConv::ID CallConv, bool isVarArg, 537 const SmallVectorImpl<ISD::InputArg> &Ins, 538 const SDLoc &dl, SelectionDAG &DAG, 539 SmallVectorImpl<SDValue> &InVals, 540 TargetLowering::CallLoweringInfo &CLI) const; 541 542 // Lower Operand specifics 543 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 544 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 545 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 546 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 547 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 548 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 549 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 550 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 551 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 552 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 553 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 554 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 555 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 556 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 557 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 558 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 559 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 560 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 561 bool IsSRA) const; 562 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 563 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 564 565 /// isEligibleForTailCallOptimization - Check whether the call is eligible 566 /// for tail call optimization. 567 virtual bool 568 isEligibleForTailCallOptimization(const CCState &CCInfo, 569 unsigned NextStackOffset, 570 const MipsFunctionInfo &FI) const = 0; 571 572 /// copyByValArg - Copy argument registers which were used to pass a byval 573 /// argument to the stack. Create a stack frame object for the byval 574 /// argument. 575 void copyByValRegs(SDValue Chain, const SDLoc &DL, 576 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 577 const ISD::ArgFlagsTy &Flags, 578 SmallVectorImpl<SDValue> &InVals, 579 const Argument *FuncArg, unsigned FirstReg, 580 unsigned LastReg, const CCValAssign &VA, 581 MipsCCState &State) const; 582 583 /// passByValArg - Pass a byval argument in registers or on stack. 584 void passByValArg(SDValue Chain, const SDLoc &DL, 585 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 586 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 587 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, 588 unsigned FirstReg, unsigned LastReg, 589 const ISD::ArgFlagsTy &Flags, bool isLittle, 590 const CCValAssign &VA) const; 591 592 /// writeVarArgRegs - Write variable function arguments passed in registers 593 /// to the stack. Also create a stack frame object for the first variable 594 /// argument. 595 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, 596 const SDLoc &DL, SelectionDAG &DAG, 597 CCState &State) const; 598 599 SDValue 600 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 601 const SmallVectorImpl<ISD::InputArg> &Ins, 602 const SDLoc &dl, SelectionDAG &DAG, 603 SmallVectorImpl<SDValue> &InVals) const override; 604 605 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 606 SDValue Arg, const SDLoc &DL, bool IsTailCall, 607 SelectionDAG &DAG) const; 608 609 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 610 SmallVectorImpl<SDValue> &InVals) const override; 611 612 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 613 bool isVarArg, 614 const SmallVectorImpl<ISD::OutputArg> &Outs, 615 LLVMContext &Context) const override; 616 617 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 618 const SmallVectorImpl<ISD::OutputArg> &Outs, 619 const SmallVectorImpl<SDValue> &OutVals, 620 const SDLoc &dl, SelectionDAG &DAG) const override; 621 622 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 623 const SDLoc &DL, SelectionDAG &DAG) const; 624 625 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 626 627 // Inline asm support 628 ConstraintType getConstraintType(StringRef Constraint) const override; 629 630 /// Examine constraint string and operand type and determine a weight value. 631 /// The operand object must already have been set up with the operand type. 632 ConstraintWeight getSingleConstraintMatchWeight( 633 AsmOperandInfo &info, const char *constraint) const override; 634 635 /// This function parses registers that appear in inline-asm constraints. 636 /// It returns pair (0, 0) on failure. 637 std::pair<unsigned, const TargetRegisterClass *> 638 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 639 640 std::pair<unsigned, const TargetRegisterClass *> 641 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 642 StringRef Constraint, MVT VT) const override; 643 644 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 645 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 646 /// true it means one of the asm constraint of the inline asm instruction 647 /// being processed is 'm'. 648 void LowerAsmOperandForConstraint(SDValue Op, 649 std::string &Constraint, 650 std::vector<SDValue> &Ops, 651 SelectionDAG &DAG) const override; 652 653 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)654 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 655 if (ConstraintCode == "R") 656 return InlineAsm::Constraint_R; 657 else if (ConstraintCode == "ZC") 658 return InlineAsm::Constraint_ZC; 659 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 660 } 661 662 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 663 Type *Ty, unsigned AS, 664 Instruction *I = nullptr) const override; 665 666 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 667 668 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 669 unsigned SrcAlign, 670 bool IsMemset, bool ZeroMemset, 671 bool MemcpyStrSrc, 672 MachineFunction &MF) const override; 673 674 /// isFPImmLegal - Returns true if the target can instruction select the 675 /// specified FP immediate natively. If false, the legalizer will 676 /// materialize the FP immediate as a load from a constant pool. 677 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 678 679 unsigned getJumpTableEncoding() const override; 680 bool useSoftFloat() const override; 681 shouldInsertFencesForAtomic(const Instruction * I)682 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 683 return true; 684 } 685 686 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 687 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI, 688 MachineBasicBlock *BB, 689 unsigned Size, unsigned DstReg, 690 unsigned SrcRec) const; 691 692 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, 693 MachineBasicBlock *BB) const; 694 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI, 695 MachineBasicBlock *BB, 696 unsigned Size) const; 697 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, 698 MachineBasicBlock *BB) const; 699 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI, 700 MachineBasicBlock *BB, 701 unsigned Size) const; 702 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const; 703 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB, 704 bool isFPCmp, unsigned Opc) const; 705 MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI, 706 MachineBasicBlock *BB) const; 707 }; 708 709 /// Create MipsTargetLowering objects. 710 const MipsTargetLowering * 711 createMips16TargetLowering(const MipsTargetMachine &TM, 712 const MipsSubtarget &STI); 713 const MipsTargetLowering * 714 createMipsSETargetLowering(const MipsTargetMachine &TM, 715 const MipsSubtarget &STI); 716 717 namespace Mips { 718 719 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 720 const TargetLibraryInfo *libInfo); 721 722 } // end namespace Mips 723 724 } // end namespace llvm 725 726 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 727