1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 clk_108MHz: clk-108M { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 clock-frequency = <108000000>; 19 clock-output-names = "108MHz-clock"; 20 }; 21 22 soc { 23 /* 24 * Defined ranges: 25 * Common BCM283x peripherals 26 * BCM2711-specific peripherals 27 * ARM-local peripherals 28 */ 29 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 30 <0x7c000000 0x0 0xfc000000 0x02000000>, 31 <0x40000000 0x0 0xff800000 0x00800000>; 32 /* Emulate a contiguous 30-bit address range for DMA */ 33 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 34 35 /* 36 * This node is the provider for the enable-method for 37 * bringing up secondary cores. 38 */ 39 local_intc: local_intc@40000000 { 40 compatible = "brcm,bcm2836-l1-intc"; 41 reg = <0x40000000 0x100>; 42 }; 43 44 gicv2: interrupt-controller@40041000 { 45 interrupt-controller; 46 #interrupt-cells = <3>; 47 compatible = "arm,gic-400"; 48 reg = <0x40041000 0x1000>, 49 <0x40042000 0x2000>, 50 <0x40044000 0x2000>, 51 <0x40046000 0x2000>; 52 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 53 IRQ_TYPE_LEVEL_HIGH)>; 54 }; 55 56 avs_monitor: avs-monitor@7d5d2000 { 57 compatible = "brcm,bcm2711-avs-monitor", 58 "syscon", "simple-mfd"; 59 reg = <0x7d5d2000 0xf00>; 60 61 thermal: thermal { 62 compatible = "brcm,bcm2711-thermal"; 63 #thermal-sensor-cells = <0>; 64 }; 65 }; 66 67 dma: dma@7e007000 { 68 compatible = "brcm,bcm2835-dma"; 69 reg = <0x7e007000 0xb00>; 70 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 77 /* DMA lite 7 - 10 */ 78 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 82 interrupt-names = "dma0", 83 "dma1", 84 "dma2", 85 "dma3", 86 "dma4", 87 "dma5", 88 "dma6", 89 "dma7", 90 "dma8", 91 "dma9", 92 "dma10"; 93 #dma-cells = <1>; 94 brcm,dma-channel-mask = <0x07f5>; 95 }; 96 97 pm: watchdog@7e100000 { 98 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 99 #power-domain-cells = <1>; 100 #reset-cells = <1>; 101 reg = <0x7e100000 0x114>, 102 <0x7e00a000 0x24>, 103 <0x7ec11000 0x20>; 104 clocks = <&clocks BCM2835_CLOCK_V3D>, 105 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 106 <&clocks BCM2835_CLOCK_H264>, 107 <&clocks BCM2835_CLOCK_ISP>; 108 clock-names = "v3d", "peri_image", "h264", "isp"; 109 system-power-controller; 110 }; 111 112 rng@7e104000 { 113 compatible = "brcm,bcm2711-rng200"; 114 reg = <0x7e104000 0x28>; 115 }; 116 117 uart2: serial@7e201400 { 118 compatible = "arm,pl011", "arm,primecell"; 119 reg = <0x7e201400 0x200>; 120 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&clocks BCM2835_CLOCK_UART>, 122 <&clocks BCM2835_CLOCK_VPU>; 123 clock-names = "uartclk", "apb_pclk"; 124 arm,primecell-periphid = <0x00241011>; 125 status = "disabled"; 126 }; 127 128 uart3: serial@7e201600 { 129 compatible = "arm,pl011", "arm,primecell"; 130 reg = <0x7e201600 0x200>; 131 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&clocks BCM2835_CLOCK_UART>, 133 <&clocks BCM2835_CLOCK_VPU>; 134 clock-names = "uartclk", "apb_pclk"; 135 arm,primecell-periphid = <0x00241011>; 136 status = "disabled"; 137 }; 138 139 uart4: serial@7e201800 { 140 compatible = "arm,pl011", "arm,primecell"; 141 reg = <0x7e201800 0x200>; 142 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&clocks BCM2835_CLOCK_UART>, 144 <&clocks BCM2835_CLOCK_VPU>; 145 clock-names = "uartclk", "apb_pclk"; 146 arm,primecell-periphid = <0x00241011>; 147 status = "disabled"; 148 }; 149 150 uart5: serial@7e201a00 { 151 compatible = "arm,pl011", "arm,primecell"; 152 reg = <0x7e201a00 0x200>; 153 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&clocks BCM2835_CLOCK_UART>, 155 <&clocks BCM2835_CLOCK_VPU>; 156 clock-names = "uartclk", "apb_pclk"; 157 arm,primecell-periphid = <0x00241011>; 158 status = "disabled"; 159 }; 160 161 spi3: spi@7e204600 { 162 compatible = "brcm,bcm2835-spi"; 163 reg = <0x7e204600 0x0200>; 164 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&clocks BCM2835_CLOCK_VPU>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 status = "disabled"; 169 }; 170 171 spi4: spi@7e204800 { 172 compatible = "brcm,bcm2835-spi"; 173 reg = <0x7e204800 0x0200>; 174 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&clocks BCM2835_CLOCK_VPU>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 status = "disabled"; 179 }; 180 181 spi5: spi@7e204a00 { 182 compatible = "brcm,bcm2835-spi"; 183 reg = <0x7e204a00 0x0200>; 184 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&clocks BCM2835_CLOCK_VPU>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 status = "disabled"; 189 }; 190 191 spi6: spi@7e204c00 { 192 compatible = "brcm,bcm2835-spi"; 193 reg = <0x7e204c00 0x0200>; 194 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&clocks BCM2835_CLOCK_VPU>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 status = "disabled"; 199 }; 200 201 i2c3: i2c@7e205600 { 202 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 203 reg = <0x7e205600 0x200>; 204 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&clocks BCM2835_CLOCK_VPU>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 status = "disabled"; 209 }; 210 211 i2c4: i2c@7e205800 { 212 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 213 reg = <0x7e205800 0x200>; 214 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&clocks BCM2835_CLOCK_VPU>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 status = "disabled"; 219 }; 220 221 i2c5: i2c@7e205a00 { 222 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 223 reg = <0x7e205a00 0x200>; 224 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&clocks BCM2835_CLOCK_VPU>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 status = "disabled"; 229 }; 230 231 i2c6: i2c@7e205c00 { 232 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 233 reg = <0x7e205c00 0x200>; 234 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&clocks BCM2835_CLOCK_VPU>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 status = "disabled"; 239 }; 240 241 pwm1: pwm@7e20c800 { 242 compatible = "brcm,bcm2835-pwm"; 243 reg = <0x7e20c800 0x28>; 244 clocks = <&clocks BCM2835_CLOCK_PWM>; 245 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 246 assigned-clock-rates = <10000000>; 247 #pwm-cells = <2>; 248 status = "disabled"; 249 }; 250 251 hvs@7e400000 { 252 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 253 }; 254 255 dvp: clock@7ef00000 { 256 compatible = "brcm,brcm2711-dvp"; 257 reg = <0x7ef00000 0x10>; 258 clocks = <&clk_108MHz>; 259 #clock-cells = <1>; 260 #reset-cells = <1>; 261 }; 262 }; 263 264 /* 265 * emmc2 has different DMA constraints based on SoC revisions. It was 266 * moved into its own bus, so as for RPi4's firmware to update them. 267 * The firmware will find whether the emmc2bus alias is defined, and if 268 * so, it'll edit the dma-ranges property below accordingly. 269 */ 270 emmc2bus: emmc2bus { 271 compatible = "simple-bus"; 272 #address-cells = <2>; 273 #size-cells = <1>; 274 275 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 276 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 277 278 emmc2: emmc2@7e340000 { 279 compatible = "brcm,bcm2711-emmc2"; 280 reg = <0x0 0x7e340000 0x100>; 281 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 283 status = "disabled"; 284 }; 285 }; 286 287 arm-pmu { 288 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 289 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 294 }; 295 296 timer { 297 compatible = "arm,armv8-timer"; 298 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 299 IRQ_TYPE_LEVEL_LOW)>, 300 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 301 IRQ_TYPE_LEVEL_LOW)>, 302 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 303 IRQ_TYPE_LEVEL_LOW)>, 304 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 305 IRQ_TYPE_LEVEL_LOW)>; 306 /* This only applies to the ARMv7 stub */ 307 arm,cpu-registers-not-fw-configured; 308 }; 309 310 cpus: cpus { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 314 315 cpu0: cpu@0 { 316 device_type = "cpu"; 317 compatible = "arm,cortex-a72"; 318 reg = <0>; 319 enable-method = "spin-table"; 320 cpu-release-addr = <0x0 0x000000d8>; 321 }; 322 323 cpu1: cpu@1 { 324 device_type = "cpu"; 325 compatible = "arm,cortex-a72"; 326 reg = <1>; 327 enable-method = "spin-table"; 328 cpu-release-addr = <0x0 0x000000e0>; 329 }; 330 331 cpu2: cpu@2 { 332 device_type = "cpu"; 333 compatible = "arm,cortex-a72"; 334 reg = <2>; 335 enable-method = "spin-table"; 336 cpu-release-addr = <0x0 0x000000e8>; 337 }; 338 339 cpu3: cpu@3 { 340 device_type = "cpu"; 341 compatible = "arm,cortex-a72"; 342 reg = <3>; 343 enable-method = "spin-table"; 344 cpu-release-addr = <0x0 0x000000f0>; 345 }; 346 }; 347 348 scb { 349 compatible = "simple-bus"; 350 #address-cells = <2>; 351 #size-cells = <1>; 352 353 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 354 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 355 356 pcie0: pcie@7d500000 { 357 compatible = "brcm,bcm2711-pcie"; 358 reg = <0x0 0x7d500000 0x9310>; 359 device_type = "pci"; 360 #address-cells = <3>; 361 #interrupt-cells = <1>; 362 #size-cells = <2>; 363 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "pcie", "msi"; 366 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 367 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 368 IRQ_TYPE_LEVEL_HIGH>; 369 msi-controller; 370 msi-parent = <&pcie0>; 371 372 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 373 0x0 0x04000000>; 374 /* 375 * The wrapper around the PCIe block has a bug 376 * preventing it from accessing beyond the first 3GB of 377 * memory. 378 */ 379 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 380 0x0 0xc0000000>; 381 brcm,enable-ssc; 382 }; 383 384 genet: ethernet@7d580000 { 385 compatible = "brcm,bcm2711-genet-v5"; 386 reg = <0x0 0x7d580000 0x10000>; 387 #address-cells = <0x1>; 388 #size-cells = <0x1>; 389 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 391 status = "disabled"; 392 393 genet_mdio: mdio@e14 { 394 compatible = "brcm,genet-mdio-v5"; 395 reg = <0xe14 0x8>; 396 reg-names = "mdio"; 397 #address-cells = <0x0>; 398 #size-cells = <0x1>; 399 }; 400 }; 401 }; 402}; 403 404&clk_osc { 405 clock-frequency = <54000000>; 406}; 407 408&clocks { 409 compatible = "brcm,bcm2711-cprman"; 410}; 411 412&cpu_thermal { 413 coefficients = <(-487) 410040>; 414 thermal-sensors = <&thermal>; 415}; 416 417&dsi0 { 418 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 419}; 420 421&dsi1 { 422 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 423}; 424 425&gpio { 426 compatible = "brcm,bcm2711-gpio"; 427 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 431 432 gpclk0_gpio49: gpclk0_gpio49 { 433 pin-gpclk { 434 pins = "gpio49"; 435 function = "alt1"; 436 bias-disable; 437 }; 438 }; 439 gpclk1_gpio50: gpclk1_gpio50 { 440 pin-gpclk { 441 pins = "gpio50"; 442 function = "alt1"; 443 bias-disable; 444 }; 445 }; 446 gpclk2_gpio51: gpclk2_gpio51 { 447 pin-gpclk { 448 pins = "gpio51"; 449 function = "alt1"; 450 bias-disable; 451 }; 452 }; 453 454 i2c0_gpio46: i2c0_gpio46 { 455 pin-sda { 456 function = "alt0"; 457 pins = "gpio46"; 458 bias-pull-up; 459 }; 460 pin-scl { 461 function = "alt0"; 462 pins = "gpio47"; 463 bias-disable; 464 }; 465 }; 466 i2c1_gpio46: i2c1_gpio46 { 467 pin-sda { 468 function = "alt1"; 469 pins = "gpio46"; 470 bias-pull-up; 471 }; 472 pin-scl { 473 function = "alt1"; 474 pins = "gpio47"; 475 bias-disable; 476 }; 477 }; 478 i2c3_gpio2: i2c3_gpio2 { 479 pin-sda { 480 function = "alt5"; 481 pins = "gpio2"; 482 bias-pull-up; 483 }; 484 pin-scl { 485 function = "alt5"; 486 pins = "gpio3"; 487 bias-disable; 488 }; 489 }; 490 i2c3_gpio4: i2c3_gpio4 { 491 pin-sda { 492 function = "alt5"; 493 pins = "gpio4"; 494 bias-pull-up; 495 }; 496 pin-scl { 497 function = "alt5"; 498 pins = "gpio5"; 499 bias-disable; 500 }; 501 }; 502 i2c4_gpio6: i2c4_gpio6 { 503 pin-sda { 504 function = "alt5"; 505 pins = "gpio6"; 506 bias-pull-up; 507 }; 508 pin-scl { 509 function = "alt5"; 510 pins = "gpio7"; 511 bias-disable; 512 }; 513 }; 514 i2c4_gpio8: i2c4_gpio8 { 515 pin-sda { 516 function = "alt5"; 517 pins = "gpio8"; 518 bias-pull-up; 519 }; 520 pin-scl { 521 function = "alt5"; 522 pins = "gpio9"; 523 bias-disable; 524 }; 525 }; 526 i2c5_gpio10: i2c5_gpio10 { 527 pin-sda { 528 function = "alt5"; 529 pins = "gpio10"; 530 bias-pull-up; 531 }; 532 pin-scl { 533 function = "alt5"; 534 pins = "gpio11"; 535 bias-disable; 536 }; 537 }; 538 i2c5_gpio12: i2c5_gpio12 { 539 pin-sda { 540 function = "alt5"; 541 pins = "gpio12"; 542 bias-pull-up; 543 }; 544 pin-scl { 545 function = "alt5"; 546 pins = "gpio13"; 547 bias-disable; 548 }; 549 }; 550 i2c6_gpio0: i2c6_gpio0 { 551 pin-sda { 552 function = "alt5"; 553 pins = "gpio0"; 554 bias-pull-up; 555 }; 556 pin-scl { 557 function = "alt5"; 558 pins = "gpio1"; 559 bias-disable; 560 }; 561 }; 562 i2c6_gpio22: i2c6_gpio22 { 563 pin-sda { 564 function = "alt5"; 565 pins = "gpio22"; 566 bias-pull-up; 567 }; 568 pin-scl { 569 function = "alt5"; 570 pins = "gpio23"; 571 bias-disable; 572 }; 573 }; 574 i2c_slave_gpio8: i2c_slave_gpio8 { 575 pins-i2c-slave { 576 pins = "gpio8", 577 "gpio9", 578 "gpio10", 579 "gpio11"; 580 function = "alt3"; 581 }; 582 }; 583 584 jtag_gpio48: jtag_gpio48 { 585 pins-jtag { 586 pins = "gpio48", 587 "gpio49", 588 "gpio50", 589 "gpio51", 590 "gpio52", 591 "gpio53"; 592 function = "alt4"; 593 }; 594 }; 595 596 mii_gpio28: mii_gpio28 { 597 pins-mii { 598 pins = "gpio28", 599 "gpio29", 600 "gpio30", 601 "gpio31"; 602 function = "alt4"; 603 }; 604 }; 605 mii_gpio36: mii_gpio36 { 606 pins-mii { 607 pins = "gpio36", 608 "gpio37", 609 "gpio38", 610 "gpio39"; 611 function = "alt5"; 612 }; 613 }; 614 615 pcm_gpio50: pcm_gpio50 { 616 pins-pcm { 617 pins = "gpio50", 618 "gpio51", 619 "gpio52", 620 "gpio53"; 621 function = "alt2"; 622 }; 623 }; 624 625 pwm0_0_gpio12: pwm0_0_gpio12 { 626 pin-pwm { 627 pins = "gpio12"; 628 function = "alt0"; 629 bias-disable; 630 }; 631 }; 632 pwm0_0_gpio18: pwm0_0_gpio18 { 633 pin-pwm { 634 pins = "gpio18"; 635 function = "alt5"; 636 bias-disable; 637 }; 638 }; 639 pwm1_0_gpio40: pwm1_0_gpio40 { 640 pin-pwm { 641 pins = "gpio40"; 642 function = "alt0"; 643 bias-disable; 644 }; 645 }; 646 pwm0_1_gpio13: pwm0_1_gpio13 { 647 pin-pwm { 648 pins = "gpio13"; 649 function = "alt0"; 650 bias-disable; 651 }; 652 }; 653 pwm0_1_gpio19: pwm0_1_gpio19 { 654 pin-pwm { 655 pins = "gpio19"; 656 function = "alt5"; 657 bias-disable; 658 }; 659 }; 660 pwm1_1_gpio41: pwm1_1_gpio41 { 661 pin-pwm { 662 pins = "gpio41"; 663 function = "alt0"; 664 bias-disable; 665 }; 666 }; 667 pwm0_1_gpio45: pwm0_1_gpio45 { 668 pin-pwm { 669 pins = "gpio45"; 670 function = "alt0"; 671 bias-disable; 672 }; 673 }; 674 pwm0_0_gpio52: pwm0_0_gpio52 { 675 pin-pwm { 676 pins = "gpio52"; 677 function = "alt1"; 678 bias-disable; 679 }; 680 }; 681 pwm0_1_gpio53: pwm0_1_gpio53 { 682 pin-pwm { 683 pins = "gpio53"; 684 function = "alt1"; 685 bias-disable; 686 }; 687 }; 688 689 rgmii_gpio35: rgmii_gpio35 { 690 pin-start-stop { 691 pins = "gpio35"; 692 function = "alt4"; 693 }; 694 pin-rx-ok { 695 pins = "gpio36"; 696 function = "alt4"; 697 }; 698 }; 699 rgmii_irq_gpio34: rgmii_irq_gpio34 { 700 pin-irq { 701 pins = "gpio34"; 702 function = "alt5"; 703 }; 704 }; 705 rgmii_irq_gpio39: rgmii_irq_gpio39 { 706 pin-irq { 707 pins = "gpio39"; 708 function = "alt4"; 709 }; 710 }; 711 rgmii_mdio_gpio28: rgmii_mdio_gpio28 { 712 pins-mdio { 713 pins = "gpio28", 714 "gpio29"; 715 function = "alt5"; 716 }; 717 }; 718 rgmii_mdio_gpio37: rgmii_mdio_gpio37 { 719 pins-mdio { 720 pins = "gpio37", 721 "gpio38"; 722 function = "alt4"; 723 }; 724 }; 725 726 spi0_gpio46: spi0_gpio46 { 727 pins-spi { 728 pins = "gpio46", 729 "gpio47", 730 "gpio48", 731 "gpio49"; 732 function = "alt2"; 733 }; 734 }; 735 spi2_gpio46: spi2_gpio46 { 736 pins-spi { 737 pins = "gpio46", 738 "gpio47", 739 "gpio48", 740 "gpio49", 741 "gpio50"; 742 function = "alt5"; 743 }; 744 }; 745 spi3_gpio0: spi3_gpio0 { 746 pins-spi { 747 pins = "gpio0", 748 "gpio1", 749 "gpio2", 750 "gpio3"; 751 function = "alt3"; 752 }; 753 }; 754 spi4_gpio4: spi4_gpio4 { 755 pins-spi { 756 pins = "gpio4", 757 "gpio5", 758 "gpio6", 759 "gpio7"; 760 function = "alt3"; 761 }; 762 }; 763 spi5_gpio12: spi5_gpio12 { 764 pins-spi { 765 pins = "gpio12", 766 "gpio13", 767 "gpio14", 768 "gpio15"; 769 function = "alt3"; 770 }; 771 }; 772 spi6_gpio18: spi6_gpio18 { 773 pins-spi { 774 pins = "gpio18", 775 "gpio19", 776 "gpio20", 777 "gpio21"; 778 function = "alt3"; 779 }; 780 }; 781 782 uart2_gpio0: uart2_gpio0 { 783 pin-tx { 784 pins = "gpio0"; 785 function = "alt4"; 786 bias-disable; 787 }; 788 pin-rx { 789 pins = "gpio1"; 790 function = "alt4"; 791 bias-pull-up; 792 }; 793 }; 794 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { 795 pin-cts { 796 pins = "gpio2"; 797 function = "alt4"; 798 bias-pull-up; 799 }; 800 pin-rts { 801 pins = "gpio3"; 802 function = "alt4"; 803 bias-disable; 804 }; 805 }; 806 uart3_gpio4: uart3_gpio4 { 807 pin-tx { 808 pins = "gpio4"; 809 function = "alt4"; 810 bias-disable; 811 }; 812 pin-rx { 813 pins = "gpio5"; 814 function = "alt4"; 815 bias-pull-up; 816 }; 817 }; 818 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { 819 pin-cts { 820 pins = "gpio6"; 821 function = "alt4"; 822 bias-pull-up; 823 }; 824 pin-rts { 825 pins = "gpio7"; 826 function = "alt4"; 827 bias-disable; 828 }; 829 }; 830 uart4_gpio8: uart4_gpio8 { 831 pin-tx { 832 pins = "gpio8"; 833 function = "alt4"; 834 bias-disable; 835 }; 836 pin-rx { 837 pins = "gpio9"; 838 function = "alt4"; 839 bias-pull-up; 840 }; 841 }; 842 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { 843 pin-cts { 844 pins = "gpio10"; 845 function = "alt4"; 846 bias-pull-up; 847 }; 848 pin-rts { 849 pins = "gpio11"; 850 function = "alt4"; 851 bias-disable; 852 }; 853 }; 854 uart5_gpio12: uart5_gpio12 { 855 pin-tx { 856 pins = "gpio12"; 857 function = "alt4"; 858 bias-disable; 859 }; 860 pin-rx { 861 pins = "gpio13"; 862 function = "alt4"; 863 bias-pull-up; 864 }; 865 }; 866 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { 867 pin-cts { 868 pins = "gpio14"; 869 function = "alt4"; 870 bias-pull-up; 871 }; 872 pin-rts { 873 pins = "gpio15"; 874 function = "alt4"; 875 bias-disable; 876 }; 877 }; 878}; 879 880&rmem { 881 #address-cells = <2>; 882}; 883 884&cma { 885 /* 886 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 887 * that's not good enough for the BCM2711 as some devices can 888 * only address the lower 1G of memory (ZONE_DMA). 889 */ 890 alloc-ranges = <0x0 0x00000000 0x40000000>; 891}; 892 893&i2c0 { 894 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 895 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 896}; 897 898&i2c1 { 899 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 900 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 901}; 902 903&mailbox { 904 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 905}; 906 907&sdhci { 908 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 909}; 910 911&sdhost { 912 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 913}; 914 915&spi { 916 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 917}; 918 919&spi1 { 920 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 921}; 922 923&spi2 { 924 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 925}; 926 927&system_timer { 928 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 932}; 933 934&txp { 935 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 936}; 937 938&uart0 { 939 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 940}; 941 942&uart1 { 943 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 944}; 945 946&usb { 947 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 948}; 949 950&vec { 951 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 952}; 953