1 /*-
2 * Copyright (c) 2015 Ruslan Bukin <[email protected]>
3 * Copyright (c) 2014,2016 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This software was developed by Andrew Turner under
7 * the sponsorship of the FreeBSD Foundation.
8 *
9 * This software was developed by Semihalf under
10 * the sponsorship of the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /* Generic ECAM PCIe driver FDT attachment */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 #include "opt_platform.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/rman.h>
48
49 #if defined(INTRNG)
50 #include <machine/intr.h>
51 #endif
52
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56 #include <dev/ofw/ofw_pci.h>
57
58 #include <dev/pci/pcivar.h>
59 #include <dev/pci/pcireg.h>
60 #include <dev/pci/pcib_private.h>
61 #include <dev/pci/pci_host_generic.h>
62 #include <dev/pci/pci_host_generic_fdt.h>
63
64 #include <machine/intr.h>
65
66 #include "pcib_if.h"
67
68 #define SPACE_CODE_SHIFT 24
69 #define SPACE_CODE_MASK 0x3
70 #define SPACE_CODE_IO_SPACE 0x1
71 #define PROPS_CELL_SIZE 1
72 #define PCI_ADDR_CELL_SIZE 2
73
74 /* OFW bus interface */
75 struct generic_pcie_ofw_devinfo {
76 struct ofw_bus_devinfo di_dinfo;
77 struct resource_list di_rl;
78 };
79
80 /* Forward prototypes */
81
82 static int generic_pcie_fdt_probe(device_t dev);
83 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *);
84 static int generic_pcie_fdt_release_resource(device_t dev, device_t child,
85 int type, int rid, struct resource *res);
86 static int generic_pcie_ofw_bus_attach(device_t);
87 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t,
88 device_t);
89
90 static __inline void
get_addr_size_cells(phandle_t node,pcell_t * addr_cells,pcell_t * size_cells)91 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells)
92 {
93
94 *addr_cells = 2;
95 /* Find address cells if present */
96 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells));
97
98 *size_cells = 2;
99 /* Find size cells if present */
100 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells));
101 }
102
103 static int
generic_pcie_fdt_probe(device_t dev)104 generic_pcie_fdt_probe(device_t dev)
105 {
106
107 if (!ofw_bus_status_okay(dev))
108 return (ENXIO);
109
110 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) {
111 device_set_desc(dev, "Generic PCI host controller");
112 return (BUS_PROBE_GENERIC);
113 }
114 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) {
115 device_set_desc(dev, "GEM5 PCIe host controller");
116 return (BUS_PROBE_DEFAULT);
117 }
118
119 return (ENXIO);
120 }
121
122 int
pci_host_generic_setup_fdt(device_t dev)123 pci_host_generic_setup_fdt(device_t dev)
124 {
125 struct generic_pcie_fdt_softc *sc;
126 phandle_t node;
127 int error;
128
129 sc = device_get_softc(dev);
130
131 /* Retrieve 'ranges' property from FDT */
132 if (bootverbose)
133 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam);
134 if (parse_pci_mem_ranges(dev, &sc->base))
135 return (ENXIO);
136
137 /* Attach OFW bus */
138 if (generic_pcie_ofw_bus_attach(dev) != 0)
139 return (ENXIO);
140
141 node = ofw_bus_get_node(dev);
142 if (sc->base.coherent == 0) {
143 sc->base.coherent = OF_hasprop(node, "dma-coherent");
144 }
145 if (bootverbose)
146 device_printf(dev, "Bus is%s cache-coherent\n",
147 sc->base.coherent ? "" : " not");
148
149 /* TODO parse FDT bus ranges */
150 sc->base.bus_start = 0;
151 sc->base.bus_end = 0xFF;
152
153 error = pci_host_generic_core_attach(dev);
154 if (error != 0)
155 return (error);
156
157 if (ofw_bus_is_compatible(dev, "marvell,armada8k-pcie-ecam") ||
158 ofw_bus_is_compatible(dev, "socionext,synquacer-pcie-ecam") ||
159 ofw_bus_is_compatible(dev, "snps,dw-pcie-ecam")) {
160 device_set_desc(dev, "Synopsys DesignWare PCIe Controller");
161 sc->base.quirks |= PCIE_ECAM_DESIGNWARE_QUIRK;
162 }
163
164 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t));
165
166 return (0);
167 }
168
169 int
pci_host_generic_attach(device_t dev)170 pci_host_generic_attach(device_t dev)
171 {
172 struct generic_pcie_fdt_softc *sc;
173 int error;
174
175 sc = device_get_softc(dev);
176
177 error = pci_host_generic_setup_fdt(dev);
178 if (error != 0)
179 return (error);
180
181 device_add_child(dev, "pci", -1);
182 return (bus_generic_attach(dev));
183 }
184
185 static int
parse_pci_mem_ranges(device_t dev,struct generic_pcie_core_softc * sc)186 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc)
187 {
188 pcell_t pci_addr_cells, parent_addr_cells;
189 pcell_t attributes, size_cells;
190 cell_t *base_ranges;
191 int nbase_ranges;
192 phandle_t node;
193 int i, j, k;
194 int tuple;
195
196 node = ofw_bus_get_node(dev);
197
198 OF_getencprop(node, "#address-cells", &pci_addr_cells,
199 sizeof(pci_addr_cells));
200 OF_getencprop(node, "#size-cells", &size_cells,
201 sizeof(size_cells));
202 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells,
203 sizeof(parent_addr_cells));
204
205 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) {
206 device_printf(dev,
207 "Unexpected number of address or size cells in FDT\n");
208 return (ENXIO);
209 }
210
211 nbase_ranges = OF_getproplen(node, "ranges");
212 sc->nranges = nbase_ranges / sizeof(cell_t) /
213 (parent_addr_cells + pci_addr_cells + size_cells);
214 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
215 OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
216
217 for (i = 0, j = 0; i < sc->nranges; i++) {
218 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \
219 SPACE_CODE_MASK;
220 if (attributes == SPACE_CODE_IO_SPACE) {
221 sc->ranges[i].flags |= FLAG_TYPE_IO;
222 } else {
223 sc->ranges[i].flags |= FLAG_TYPE_MEM;
224 }
225
226 sc->ranges[i].pci_base = 0;
227 for (k = 0; k < (pci_addr_cells - 1); k++) {
228 sc->ranges[i].pci_base <<= 32;
229 sc->ranges[i].pci_base |= base_ranges[j++];
230 }
231 sc->ranges[i].phys_base = 0;
232 for (k = 0; k < parent_addr_cells; k++) {
233 sc->ranges[i].phys_base <<= 32;
234 sc->ranges[i].phys_base |= base_ranges[j++];
235 }
236 sc->ranges[i].size = 0;
237 for (k = 0; k < size_cells; k++) {
238 sc->ranges[i].size <<= 32;
239 sc->ranges[i].size |= base_ranges[j++];
240 }
241 }
242
243 for (; i < MAX_RANGES_TUPLES; i++) {
244 /* zero-fill remaining tuples to mark empty elements in array */
245 sc->ranges[i].pci_base = 0;
246 sc->ranges[i].phys_base = 0;
247 sc->ranges[i].size = 0;
248 }
249
250 if (bootverbose) {
251 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
252 device_printf(dev,
253 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n",
254 sc->ranges[tuple].pci_base,
255 sc->ranges[tuple].phys_base,
256 sc->ranges[tuple].size);
257 }
258 }
259
260 free(base_ranges, M_DEVBUF);
261 return (0);
262 }
263
264 static int
generic_pcie_fdt_route_interrupt(device_t bus,device_t dev,int pin)265 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin)
266 {
267 struct generic_pcie_fdt_softc *sc;
268 struct ofw_pci_register reg;
269 uint32_t pintr, mintr[4];
270 phandle_t iparent;
271 int intrcells;
272
273 sc = device_get_softc(bus);
274 pintr = pin;
275
276 bzero(®, sizeof(reg));
277 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
278 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
279 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
280
281 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev),
282 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr),
283 mintr, sizeof(mintr), &iparent);
284 if (intrcells) {
285 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr);
286 return (pintr);
287 }
288
289 device_printf(bus, "could not route pin %d for device %d.%d\n",
290 pin, pci_get_slot(dev), pci_get_function(dev));
291 return (PCI_INVALID_IRQ);
292 }
293
294 static int
generic_pcie_fdt_release_resource(device_t dev,device_t child,int type,int rid,struct resource * res)295 generic_pcie_fdt_release_resource(device_t dev, device_t child, int type,
296 int rid, struct resource *res)
297 {
298
299 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
300 if (type == PCI_RES_BUS) {
301 return (pci_host_generic_core_release_resource(dev, child, type,
302 rid, res));
303 }
304 #endif
305
306 /* For PCIe devices that do not have FDT nodes, use PCIB method */
307 if ((int)ofw_bus_get_node(child) <= 0) {
308 return (pci_host_generic_core_release_resource(dev, child, type,
309 rid, res));
310 }
311
312 /* For other devices use OFW method */
313 return (bus_generic_release_resource(dev, child, type, rid, res));
314 }
315
316 struct resource *
pci_host_generic_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)317 pci_host_generic_alloc_resource(device_t dev, device_t child, int type,
318 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
319 {
320 struct generic_pcie_fdt_softc *sc;
321 struct generic_pcie_ofw_devinfo *di;
322 struct resource_list_entry *rle;
323 int i;
324
325 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
326 if (type == PCI_RES_BUS) {
327 return (pci_host_generic_core_alloc_resource(dev, child, type, rid,
328 start, end, count, flags));
329 }
330 #endif
331
332 /* For PCIe devices that do not have FDT nodes, use PCIB method */
333 if ((int)ofw_bus_get_node(child) <= 0)
334 return (pci_host_generic_core_alloc_resource(dev, child, type,
335 rid, start, end, count, flags));
336
337 /* For other devices use OFW method */
338 sc = device_get_softc(dev);
339
340 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
341 if ((di = device_get_ivars(child)) == NULL)
342 return (NULL);
343 if (type == SYS_RES_IOPORT)
344 type = SYS_RES_MEMORY;
345
346 /* Find defaults for this rid */
347 rle = resource_list_find(&di->di_rl, type, *rid);
348 if (rle == NULL)
349 return (NULL);
350
351 start = rle->start;
352 end = rle->end;
353 count = rle->count;
354 }
355
356 if (type == SYS_RES_MEMORY) {
357 /* Remap through ranges property */
358 for (i = 0; i < MAX_RANGES_TUPLES; i++) {
359 if (start >= sc->base.ranges[i].phys_base &&
360 end < (sc->base.ranges[i].pci_base +
361 sc->base.ranges[i].size)) {
362 start -= sc->base.ranges[i].phys_base;
363 start += sc->base.ranges[i].pci_base;
364 end -= sc->base.ranges[i].phys_base;
365 end += sc->base.ranges[i].pci_base;
366 break;
367 }
368 }
369
370 if (i == MAX_RANGES_TUPLES) {
371 device_printf(dev, "Could not map resource "
372 "%#jx-%#jx\n", start, end);
373 return (NULL);
374 }
375 }
376
377 return (bus_generic_alloc_resource(dev, child, type, rid, start,
378 end, count, flags));
379 }
380
381 static int
generic_pcie_fdt_alloc_msi(device_t pci,device_t child,int count,int maxcount,int * irqs)382 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count,
383 int maxcount, int *irqs)
384 {
385 #if defined(INTRNG)
386 phandle_t msi_parent;
387 int err;
388
389 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
390 &msi_parent, NULL);
391 if (err != 0)
392 return (err);
393 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
394 irqs));
395 #else
396 return (ENXIO);
397 #endif
398 }
399
400 static int
generic_pcie_fdt_release_msi(device_t pci,device_t child,int count,int * irqs)401 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs)
402 {
403 #if defined(INTRNG)
404 phandle_t msi_parent;
405 int err;
406
407 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
408 &msi_parent, NULL);
409 if (err != 0)
410 return (err);
411 return (intr_release_msi(pci, child, msi_parent, count, irqs));
412 #else
413 return (ENXIO);
414 #endif
415 }
416
417 static int
generic_pcie_fdt_map_msi(device_t pci,device_t child,int irq,uint64_t * addr,uint32_t * data)418 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
419 uint32_t *data)
420 {
421 #if defined(INTRNG)
422 phandle_t msi_parent;
423 int err;
424
425 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
426 &msi_parent, NULL);
427 if (err != 0)
428 return (err);
429 return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
430 #else
431 return (ENXIO);
432 #endif
433 }
434
435 static int
generic_pcie_fdt_alloc_msix(device_t pci,device_t child,int * irq)436 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq)
437 {
438 #if defined(INTRNG)
439 phandle_t msi_parent;
440 int err;
441
442 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
443 &msi_parent, NULL);
444 if (err != 0)
445 return (err);
446 return (intr_alloc_msix(pci, child, msi_parent, irq));
447 #else
448 return (ENXIO);
449 #endif
450 }
451
452 static int
generic_pcie_fdt_release_msix(device_t pci,device_t child,int irq)453 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq)
454 {
455 #if defined(INTRNG)
456 phandle_t msi_parent;
457 int err;
458
459 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
460 &msi_parent, NULL);
461 if (err != 0)
462 return (err);
463 return (intr_release_msix(pci, child, msi_parent, irq));
464 #else
465 return (ENXIO);
466 #endif
467 }
468
469 int
generic_pcie_get_id(device_t pci,device_t child,enum pci_id_type type,uintptr_t * id)470 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type,
471 uintptr_t *id)
472 {
473 phandle_t node;
474 int err;
475 uint32_t rid;
476 uint16_t pci_rid;
477
478 if (type != PCI_ID_MSI)
479 return (pcib_get_id(pci, child, type, id));
480
481 node = ofw_bus_get_node(pci);
482 pci_rid = pci_get_rid(child);
483
484 err = ofw_bus_msimap(node, pci_rid, NULL, &rid);
485 if (err != 0)
486 return (err);
487 *id = rid;
488
489 return (0);
490 }
491
492 static const struct ofw_bus_devinfo *
generic_pcie_ofw_get_devinfo(device_t bus __unused,device_t child)493 generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child)
494 {
495 struct generic_pcie_ofw_devinfo *di;
496
497 di = device_get_ivars(child);
498 return (&di->di_dinfo);
499 }
500
501 /* Helper functions */
502
503 static int
generic_pcie_ofw_bus_attach(device_t dev)504 generic_pcie_ofw_bus_attach(device_t dev)
505 {
506 struct generic_pcie_ofw_devinfo *di;
507 device_t child;
508 phandle_t parent, node;
509 pcell_t addr_cells, size_cells;
510
511 parent = ofw_bus_get_node(dev);
512 if (parent > 0) {
513 get_addr_size_cells(parent, &addr_cells, &size_cells);
514 /* Iterate through all bus subordinates */
515 for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
516 /* Allocate and populate devinfo. */
517 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
518 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) {
519 free(di, M_DEVBUF);
520 continue;
521 }
522
523 /* Initialize and populate resource list. */
524 resource_list_init(&di->di_rl);
525 ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells,
526 &di->di_rl);
527 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL);
528
529 /* Add newbus device for this FDT node */
530 child = device_add_child(dev, NULL, -1);
531 if (child == NULL) {
532 resource_list_free(&di->di_rl);
533 ofw_bus_gen_destroy_devinfo(&di->di_dinfo);
534 free(di, M_DEVBUF);
535 continue;
536 }
537
538 device_set_ivars(child, di);
539 }
540 }
541
542 return (0);
543 }
544
545 static device_method_t generic_pcie_fdt_methods[] = {
546 DEVMETHOD(device_probe, generic_pcie_fdt_probe),
547 DEVMETHOD(device_attach, pci_host_generic_attach),
548 DEVMETHOD(bus_alloc_resource, pci_host_generic_alloc_resource),
549 DEVMETHOD(bus_release_resource, generic_pcie_fdt_release_resource),
550
551 /* pcib interface */
552 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt),
553 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi),
554 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi),
555 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix),
556 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix),
557 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi),
558 DEVMETHOD(pcib_get_id, generic_pcie_get_id),
559 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
560
561 /* ofw_bus interface */
562 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo),
563 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
564 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
565 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
566 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
567 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
568
569 DEVMETHOD_END
570 };
571
572 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods,
573 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver);
574
575 static devclass_t generic_pcie_fdt_devclass;
576
577 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver,
578 generic_pcie_fdt_devclass, 0, 0);
579 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass,
580 0, 0);
581