1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
3 *
4 * Copyright (c) 1995, David Greenman
5 * Copyright (c) 2001 Jonathan Lemon <[email protected]>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 /*
36 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 */
38
39 #ifdef HAVE_KERNEL_OPTION_HEADERS
40 #include "opt_device_polling.h"
41 #endif
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/bus.h>
46 #include <sys/endian.h>
47 #include <sys/kernel.h>
48 #include <sys/mbuf.h>
49 #include <sys/lock.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/rman.h>
54 #include <sys/socket.h>
55 #include <sys/sockio.h>
56 #include <sys/sysctl.h>
57
58 #include <net/bpf.h>
59 #include <net/ethernet.h>
60 #include <net/if.h>
61 #include <net/if_var.h>
62 #include <net/if_arp.h>
63 #include <net/if_dl.h>
64 #include <net/if_media.h>
65 #include <net/if_types.h>
66 #include <net/if_vlan_var.h>
67
68 #include <netinet/in.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/ip.h>
71 #include <netinet/tcp.h>
72 #include <netinet/udp.h>
73
74 #include <machine/bus.h>
75 #include <machine/in_cksum.h>
76 #include <machine/resource.h>
77
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
80
81 #include <dev/mii/mii.h>
82 #include <dev/mii/miivar.h>
83
84 #include <dev/fxp/if_fxpreg.h>
85 #include <dev/fxp/if_fxpvar.h>
86 #include <dev/fxp/rcvbundl.h>
87
88 MODULE_DEPEND(fxp, pci, 1, 1, 1);
89 MODULE_DEPEND(fxp, ether, 1, 1, 1);
90 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
91 #include "miibus_if.h"
92
93 /*
94 * NOTE! On !x86 we typically have an alignment constraint. The
95 * card DMAs the packet immediately following the RFA. However,
96 * the first thing in the packet is a 14-byte Ethernet header.
97 * This means that the packet is misaligned. To compensate,
98 * we actually offset the RFA 2 bytes into the cluster. This
99 * alignes the packet after the Ethernet header at a 32-bit
100 * boundary. HOWEVER! This means that the RFA is misaligned!
101 */
102 #define RFA_ALIGNMENT_FUDGE 2
103
104 /*
105 * Set initial transmit threshold at 64 (512 bytes). This is
106 * increased by 64 (512 bytes) at a time, to maximum of 192
107 * (1536 bytes), if an underrun occurs.
108 */
109 static int tx_threshold = 64;
110
111 /*
112 * The configuration byte map has several undefined fields which
113 * must be one or must be zero. Set up a template for these bits.
114 * The actual configuration is performed in fxp_init_body.
115 *
116 * See struct fxp_cb_config for the bit definitions.
117 */
118 static const u_char fxp_cb_config_template[] = {
119 0x0, 0x0, /* cb_status */
120 0x0, 0x0, /* cb_command */
121 0x0, 0x0, 0x0, 0x0, /* link_addr */
122 0x0, /* 0 */
123 0x0, /* 1 */
124 0x0, /* 2 */
125 0x0, /* 3 */
126 0x0, /* 4 */
127 0x0, /* 5 */
128 0x32, /* 6 */
129 0x0, /* 7 */
130 0x0, /* 8 */
131 0x0, /* 9 */
132 0x6, /* 10 */
133 0x0, /* 11 */
134 0x0, /* 12 */
135 0x0, /* 13 */
136 0xf2, /* 14 */
137 0x48, /* 15 */
138 0x0, /* 16 */
139 0x40, /* 17 */
140 0xf0, /* 18 */
141 0x0, /* 19 */
142 0x3f, /* 20 */
143 0x5, /* 21 */
144 0x0, /* 22 */
145 0x0, /* 23 */
146 0x0, /* 24 */
147 0x0, /* 25 */
148 0x0, /* 26 */
149 0x0, /* 27 */
150 0x0, /* 28 */
151 0x0, /* 29 */
152 0x0, /* 30 */
153 0x0 /* 31 */
154 };
155
156 /*
157 * Claim various Intel PCI device identifiers for this driver. The
158 * sub-vendor and sub-device field are extensively used to identify
159 * particular variants, but we don't currently differentiate between
160 * them.
161 */
162 static const struct fxp_ident fxp_ident_table[] = {
163 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
164 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
165 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
166 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
167 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
168 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
169 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
170 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
171 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
172 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
173 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
174 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
175 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
176 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
177 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
178 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
179 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
180 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
181 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
182 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
183 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
184 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
185 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
186 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
187 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
188 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
189 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
190 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
191 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
192 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
193 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
194 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
195 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
196 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
197 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
198 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
199 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
200 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
201 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
202 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
203 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
204 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
205 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
206 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
207 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
208 { 0, 0, -1, 0, NULL },
209 };
210
211 #ifdef FXP_IP_CSUM_WAR
212 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
213 #else
214 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
215 #endif
216
217 static int fxp_probe(device_t dev);
218 static int fxp_attach(device_t dev);
219 static int fxp_detach(device_t dev);
220 static int fxp_shutdown(device_t dev);
221 static int fxp_suspend(device_t dev);
222 static int fxp_resume(device_t dev);
223
224 static const struct fxp_ident *fxp_find_ident(device_t dev);
225 static void fxp_intr(void *xsc);
226 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp,
227 struct mbuf *m, uint16_t status, int pos);
228 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp,
229 uint8_t statack, int count);
230 static void fxp_init(void *xsc);
231 static void fxp_init_body(struct fxp_softc *sc, int);
232 static void fxp_tick(void *xsc);
233 static void fxp_start(if_t ifp);
234 static void fxp_start_body(if_t ifp);
235 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
236 static void fxp_txeof(struct fxp_softc *sc);
237 static void fxp_stop(struct fxp_softc *sc);
238 static void fxp_release(struct fxp_softc *sc);
239 static int fxp_ioctl(if_t ifp, u_long command,
240 caddr_t data);
241 static void fxp_watchdog(struct fxp_softc *sc);
242 static void fxp_add_rfabuf(struct fxp_softc *sc,
243 struct fxp_rx *rxp);
244 static void fxp_discard_rfabuf(struct fxp_softc *sc,
245 struct fxp_rx *rxp);
246 static int fxp_new_rfabuf(struct fxp_softc *sc,
247 struct fxp_rx *rxp);
248 static int fxp_mc_addrs(struct fxp_softc *sc);
249 static void fxp_mc_setup(struct fxp_softc *sc);
250 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
251 int autosize);
252 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
253 uint16_t data);
254 static void fxp_autosize_eeprom(struct fxp_softc *sc);
255 static void fxp_load_eeprom(struct fxp_softc *sc);
256 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
257 int offset, int words);
258 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
259 int offset, int words);
260 static int fxp_ifmedia_upd(if_t ifp);
261 static void fxp_ifmedia_sts(if_t ifp,
262 struct ifmediareq *ifmr);
263 static int fxp_serial_ifmedia_upd(if_t ifp);
264 static void fxp_serial_ifmedia_sts(if_t ifp,
265 struct ifmediareq *ifmr);
266 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
267 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
268 int value);
269 static void fxp_miibus_statchg(device_t dev);
270 static void fxp_load_ucode(struct fxp_softc *sc);
271 static void fxp_update_stats(struct fxp_softc *sc);
272 static void fxp_sysctl_node(struct fxp_softc *sc);
273 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
274 int low, int high);
275 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
276 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
277 static void fxp_scb_wait(struct fxp_softc *sc);
278 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
279 static void fxp_dma_wait(struct fxp_softc *sc,
280 volatile uint16_t *status, bus_dma_tag_t dmat,
281 bus_dmamap_t map);
282
283 static device_method_t fxp_methods[] = {
284 /* Device interface */
285 DEVMETHOD(device_probe, fxp_probe),
286 DEVMETHOD(device_attach, fxp_attach),
287 DEVMETHOD(device_detach, fxp_detach),
288 DEVMETHOD(device_shutdown, fxp_shutdown),
289 DEVMETHOD(device_suspend, fxp_suspend),
290 DEVMETHOD(device_resume, fxp_resume),
291
292 /* MII interface */
293 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
294 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
295 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
296
297 DEVMETHOD_END
298 };
299
300 static driver_t fxp_driver = {
301 "fxp",
302 fxp_methods,
303 sizeof(struct fxp_softc),
304 };
305
306 static devclass_t fxp_devclass;
307
308 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL,
309 SI_ORDER_ANY);
310 MODULE_PNP_INFO("U16:vendor;U16:device", pci, fxp, fxp_ident_table,
311 nitems(fxp_ident_table) - 1);
312 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
313
314 static struct resource_spec fxp_res_spec_mem[] = {
315 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
316 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
317 { -1, 0 }
318 };
319
320 static struct resource_spec fxp_res_spec_io[] = {
321 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
322 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
323 { -1, 0 }
324 };
325
326 /*
327 * Wait for the previous command to be accepted (but not necessarily
328 * completed).
329 */
330 static void
fxp_scb_wait(struct fxp_softc * sc)331 fxp_scb_wait(struct fxp_softc *sc)
332 {
333 union {
334 uint16_t w;
335 uint8_t b[2];
336 } flowctl;
337 int i = 10000;
338
339 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
340 DELAY(2);
341 if (i == 0) {
342 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
343 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
344 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
345 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
346 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
347 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
348 }
349 }
350
351 static void
fxp_scb_cmd(struct fxp_softc * sc,int cmd)352 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
353 {
354
355 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
356 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
357 fxp_scb_wait(sc);
358 }
359 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
360 }
361
362 static void
fxp_dma_wait(struct fxp_softc * sc,volatile uint16_t * status,bus_dma_tag_t dmat,bus_dmamap_t map)363 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
364 bus_dma_tag_t dmat, bus_dmamap_t map)
365 {
366 int i;
367
368 for (i = 10000; i > 0; i--) {
369 DELAY(2);
370 bus_dmamap_sync(dmat, map,
371 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
372 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
373 break;
374 }
375 if (i == 0)
376 device_printf(sc->dev, "DMA timeout\n");
377 }
378
379 static const struct fxp_ident *
fxp_find_ident(device_t dev)380 fxp_find_ident(device_t dev)
381 {
382 uint16_t vendor;
383 uint16_t device;
384 uint8_t revid;
385 const struct fxp_ident *ident;
386
387 vendor = pci_get_vendor(dev);
388 device = pci_get_device(dev);
389 revid = pci_get_revid(dev);
390 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
391 if (ident->vendor == vendor && ident->device == device &&
392 (ident->revid == revid || ident->revid == -1)) {
393 return (ident);
394 }
395 }
396 return (NULL);
397 }
398
399 /*
400 * Return identification string if this device is ours.
401 */
402 static int
fxp_probe(device_t dev)403 fxp_probe(device_t dev)
404 {
405 const struct fxp_ident *ident;
406
407 ident = fxp_find_ident(dev);
408 if (ident != NULL) {
409 device_set_desc(dev, ident->name);
410 return (BUS_PROBE_DEFAULT);
411 }
412 return (ENXIO);
413 }
414
415 static void
fxp_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)416 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
417 {
418 uint32_t *addr;
419
420 if (error)
421 return;
422
423 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
424 addr = arg;
425 *addr = segs->ds_addr;
426 }
427
428 static int
fxp_attach(device_t dev)429 fxp_attach(device_t dev)
430 {
431 struct fxp_softc *sc;
432 struct fxp_cb_tx *tcbp;
433 struct fxp_tx *txp;
434 struct fxp_rx *rxp;
435 if_t ifp;
436 uint32_t val;
437 uint16_t data;
438 u_char eaddr[ETHER_ADDR_LEN];
439 int error, flags, i, pmc, prefer_iomap;
440
441 error = 0;
442 sc = device_get_softc(dev);
443 sc->dev = dev;
444 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
445 MTX_DEF);
446 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
447 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
448 fxp_serial_ifmedia_sts);
449
450 ifp = sc->ifp = if_gethandle(IFT_ETHER);
451 if (ifp == (void *)NULL) {
452 device_printf(dev, "can not if_alloc()\n");
453 error = ENOSPC;
454 goto fail;
455 }
456
457 /*
458 * Enable bus mastering.
459 */
460 pci_enable_busmaster(dev);
461
462 /*
463 * Figure out which we should try first - memory mapping or i/o mapping?
464 * We default to memory mapping. Then we accept an override from the
465 * command line. Then we check to see which one is enabled.
466 */
467 prefer_iomap = 0;
468 resource_int_value(device_get_name(dev), device_get_unit(dev),
469 "prefer_iomap", &prefer_iomap);
470 if (prefer_iomap)
471 sc->fxp_spec = fxp_res_spec_io;
472 else
473 sc->fxp_spec = fxp_res_spec_mem;
474
475 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
476 if (error) {
477 if (sc->fxp_spec == fxp_res_spec_mem)
478 sc->fxp_spec = fxp_res_spec_io;
479 else
480 sc->fxp_spec = fxp_res_spec_mem;
481 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
482 }
483 if (error) {
484 device_printf(dev, "could not allocate resources\n");
485 error = ENXIO;
486 goto fail;
487 }
488
489 if (bootverbose) {
490 device_printf(dev, "using %s space register mapping\n",
491 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
492 }
493
494 /*
495 * Put CU/RU idle state and prepare full reset.
496 */
497 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
498 DELAY(10);
499 /* Full reset and disable interrupts. */
500 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
501 DELAY(10);
502 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
503
504 /*
505 * Find out how large of an SEEPROM we have.
506 */
507 fxp_autosize_eeprom(sc);
508 fxp_load_eeprom(sc);
509
510 /*
511 * Find out the chip revision; lump all 82557 revs together.
512 */
513 sc->ident = fxp_find_ident(dev);
514 if (sc->ident->ich > 0) {
515 /* Assume ICH controllers are 82559. */
516 sc->revision = FXP_REV_82559_A0;
517 } else {
518 data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
519 if ((data >> 8) == 1)
520 sc->revision = FXP_REV_82557;
521 else
522 sc->revision = pci_get_revid(dev);
523 }
524
525 /*
526 * Check availability of WOL. 82559ER does not support WOL.
527 */
528 if (sc->revision >= FXP_REV_82558_A4 &&
529 sc->revision != FXP_REV_82559S_A) {
530 data = sc->eeprom[FXP_EEPROM_MAP_ID];
531 if ((data & 0x20) != 0 &&
532 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
533 sc->flags |= FXP_FLAG_WOLCAP;
534 }
535
536 if (sc->revision == FXP_REV_82550_C) {
537 /*
538 * 82550C with server extension requires microcode to
539 * receive fragmented UDP datagrams. However if the
540 * microcode is used for client-only featured 82550C
541 * it locks up controller.
542 */
543 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
544 if ((data & 0x0400) == 0)
545 sc->flags |= FXP_FLAG_NO_UCODE;
546 }
547
548 /* Receiver lock-up workaround detection. */
549 if (sc->revision < FXP_REV_82558_A4) {
550 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
551 if ((data & 0x03) != 0x03) {
552 sc->flags |= FXP_FLAG_RXBUG;
553 device_printf(dev, "Enabling Rx lock-up workaround\n");
554 }
555 }
556
557 /*
558 * Determine whether we must use the 503 serial interface.
559 */
560 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
561 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
562 && (data & FXP_PHY_SERIAL_ONLY))
563 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
564
565 fxp_sysctl_node(sc);
566 /*
567 * Enable workarounds for certain chip revision deficiencies.
568 *
569 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
570 * some systems based a normal 82559 design, have a defect where
571 * the chip can cause a PCI protocol violation if it receives
572 * a CU_RESUME command when it is entering the IDLE state. The
573 * workaround is to disable Dynamic Standby Mode, so the chip never
574 * deasserts CLKRUN#, and always remains in an active state.
575 *
576 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
577 */
578 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
579 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
580 data = sc->eeprom[FXP_EEPROM_MAP_ID];
581 if (data & 0x02) { /* STB enable */
582 uint16_t cksum;
583 int i;
584
585 device_printf(dev,
586 "Disabling dynamic standby mode in EEPROM\n");
587 data &= ~0x02;
588 sc->eeprom[FXP_EEPROM_MAP_ID] = data;
589 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
590 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
591 cksum = 0;
592 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
593 cksum += sc->eeprom[i];
594 i = (1 << sc->eeprom_size) - 1;
595 cksum = 0xBABA - cksum;
596 fxp_write_eeprom(sc, &cksum, i, 1);
597 device_printf(dev,
598 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
599 i, sc->eeprom[i], cksum);
600 sc->eeprom[i] = cksum;
601 /*
602 * If the user elects to continue, try the software
603 * workaround, as it is better than nothing.
604 */
605 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
606 }
607 }
608
609 /*
610 * If we are not a 82557 chip, we can enable extended features.
611 */
612 if (sc->revision != FXP_REV_82557) {
613 /*
614 * If MWI is enabled in the PCI configuration, and there
615 * is a valid cacheline size (8 or 16 dwords), then tell
616 * the board to turn on MWI.
617 */
618 val = pci_read_config(dev, PCIR_COMMAND, 2);
619 if (val & PCIM_CMD_MWRICEN &&
620 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
621 sc->flags |= FXP_FLAG_MWI_ENABLE;
622
623 /* turn on the extended TxCB feature */
624 sc->flags |= FXP_FLAG_EXT_TXCB;
625
626 /* enable reception of long frames for VLAN */
627 sc->flags |= FXP_FLAG_LONG_PKT_EN;
628 } else {
629 /* a hack to get long VLAN frames on a 82557 */
630 sc->flags |= FXP_FLAG_SAVE_BAD;
631 }
632
633 /* For 82559 or later chips, Rx checksum offload is supported. */
634 if (sc->revision >= FXP_REV_82559_A0) {
635 /* 82559ER does not support Rx checksum offloading. */
636 if (sc->ident->device != 0x1209)
637 sc->flags |= FXP_FLAG_82559_RXCSUM;
638 }
639 /*
640 * Enable use of extended RFDs and TCBs for 82550
641 * and later chips. Note: we need extended TXCB support
642 * too, but that's already enabled by the code above.
643 * Be careful to do this only on the right devices.
644 */
645 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
646 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
647 || sc->revision == FXP_REV_82551_10) {
648 sc->rfa_size = sizeof (struct fxp_rfa);
649 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
650 sc->flags |= FXP_FLAG_EXT_RFA;
651 /* Use extended RFA instead of 82559 checksum mode. */
652 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
653 } else {
654 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
655 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
656 }
657
658 /*
659 * Allocate DMA tags and DMA safe memory.
660 */
661 sc->maxtxseg = FXP_NTXSEG;
662 sc->maxsegsize = MCLBYTES;
663 if (sc->flags & FXP_FLAG_EXT_RFA) {
664 sc->maxtxseg--;
665 sc->maxsegsize = FXP_TSO_SEGSIZE;
666 }
667 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
668 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
669 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
670 sc->maxtxseg, sc->maxsegsize, 0,
671 busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
672 if (error) {
673 device_printf(dev, "could not create TX DMA tag\n");
674 goto fail;
675 }
676
677 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
678 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
679 MCLBYTES, 1, MCLBYTES, 0,
680 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
681 if (error) {
682 device_printf(dev, "could not create RX DMA tag\n");
683 goto fail;
684 }
685
686 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
687 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
688 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
689 busdma_lock_mutex, &Giant, &sc->fxp_stag);
690 if (error) {
691 device_printf(dev, "could not create stats DMA tag\n");
692 goto fail;
693 }
694
695 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
696 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
697 if (error) {
698 device_printf(dev, "could not allocate stats DMA memory\n");
699 goto fail;
700 }
701 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
702 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
703 BUS_DMA_NOWAIT);
704 if (error) {
705 device_printf(dev, "could not load the stats DMA buffer\n");
706 goto fail;
707 }
708
709 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
710 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
711 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
712 busdma_lock_mutex, &Giant, &sc->cbl_tag);
713 if (error) {
714 device_printf(dev, "could not create TxCB DMA tag\n");
715 goto fail;
716 }
717
718 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
719 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
720 if (error) {
721 device_printf(dev, "could not allocate TxCB DMA memory\n");
722 goto fail;
723 }
724
725 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
726 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
727 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
728 if (error) {
729 device_printf(dev, "could not load TxCB DMA buffer\n");
730 goto fail;
731 }
732
733 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
734 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
735 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
736 busdma_lock_mutex, &Giant, &sc->mcs_tag);
737 if (error) {
738 device_printf(dev,
739 "could not create multicast setup DMA tag\n");
740 goto fail;
741 }
742
743 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
744 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
745 if (error) {
746 device_printf(dev,
747 "could not allocate multicast setup DMA memory\n");
748 goto fail;
749 }
750 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
751 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
752 BUS_DMA_NOWAIT);
753 if (error) {
754 device_printf(dev,
755 "can't load the multicast setup DMA buffer\n");
756 goto fail;
757 }
758
759 /*
760 * Pre-allocate the TX DMA maps and setup the pointers to
761 * the TX command blocks.
762 */
763 txp = sc->fxp_desc.tx_list;
764 tcbp = sc->fxp_desc.cbl_list;
765 for (i = 0; i < FXP_NTXCB; i++) {
766 txp[i].tx_cb = tcbp + i;
767 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
768 if (error) {
769 device_printf(dev, "can't create DMA map for TX\n");
770 goto fail;
771 }
772 }
773 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
774 if (error) {
775 device_printf(dev, "can't create spare DMA map\n");
776 goto fail;
777 }
778
779 /*
780 * Pre-allocate our receive buffers.
781 */
782 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
783 for (i = 0; i < FXP_NRFABUFS; i++) {
784 rxp = &sc->fxp_desc.rx_list[i];
785 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
786 if (error) {
787 device_printf(dev, "can't create DMA map for RX\n");
788 goto fail;
789 }
790 if (fxp_new_rfabuf(sc, rxp) != 0) {
791 error = ENOMEM;
792 goto fail;
793 }
794 fxp_add_rfabuf(sc, rxp);
795 }
796
797 /*
798 * Read MAC address.
799 */
800 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
801 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
802 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
803 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
804 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
805 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
806 if (bootverbose) {
807 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
808 pci_get_vendor(dev), pci_get_device(dev),
809 pci_get_subvendor(dev), pci_get_subdevice(dev),
810 pci_get_revid(dev));
811 device_printf(dev, "Dynamic Standby mode is %s\n",
812 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
813 "disabled");
814 }
815
816 /*
817 * If this is only a 10Mbps device, then there is no MII, and
818 * the PHY will use a serial interface instead.
819 *
820 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
821 * doesn't have a programming interface of any sort. The
822 * media is sensed automatically based on how the link partner
823 * is configured. This is, in essence, manual configuration.
824 */
825 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
826 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
827 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
828 } else {
829 /*
830 * i82557 wedge when isolating all of their PHYs.
831 */
832 flags = MIIF_NOISOLATE;
833 if (sc->revision >= FXP_REV_82558_A4)
834 flags |= MIIF_DOPAUSE;
835 error = mii_attach(dev, &sc->miibus, ifp,
836 (ifm_change_cb_t)fxp_ifmedia_upd,
837 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK,
838 MII_PHY_ANY, MII_OFFSET_ANY, flags);
839 if (error != 0) {
840 device_printf(dev, "attaching PHYs failed\n");
841 goto fail;
842 }
843 }
844
845 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
846 if_setdev(ifp, dev);
847 if_setinitfn(ifp, fxp_init);
848 if_setsoftc(ifp, sc);
849 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
850 if_setioctlfn(ifp, fxp_ioctl);
851 if_setstartfn(ifp, fxp_start);
852
853 if_setcapabilities(ifp, 0);
854 if_setcapenable(ifp, 0);
855
856 /* Enable checksum offload/TSO for 82550 or better chips */
857 if (sc->flags & FXP_FLAG_EXT_RFA) {
858 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO);
859 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
860 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
861 }
862
863 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
864 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
865 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
866 }
867
868 if (sc->flags & FXP_FLAG_WOLCAP) {
869 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
870 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
871 }
872
873 #ifdef DEVICE_POLLING
874 /* Inform the world we support polling. */
875 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
876 #endif
877
878 /*
879 * Attach the interface.
880 */
881 ether_ifattach(ifp, eaddr);
882
883 /*
884 * Tell the upper layer(s) we support long frames.
885 * Must appear after the call to ether_ifattach() because
886 * ether_ifattach() sets ifi_hdrlen to the default value.
887 */
888 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
889 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
890 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
891 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
892 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING |
893 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
894 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING |
895 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
896 }
897
898 /*
899 * Let the system queue as many packets as we have available
900 * TX descriptors.
901 */
902 if_setsendqlen(ifp, FXP_NTXCB - 1);
903 if_setsendqready(ifp);
904
905 /*
906 * Hook our interrupt after all initialization is complete.
907 */
908 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
909 NULL, fxp_intr, sc, &sc->ih);
910 if (error) {
911 device_printf(dev, "could not setup irq\n");
912 ether_ifdetach(sc->ifp);
913 goto fail;
914 }
915
916 /*
917 * Configure hardware to reject magic frames otherwise
918 * system will hang on recipt of magic frames.
919 */
920 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
921 FXP_LOCK(sc);
922 /* Clear wakeup events. */
923 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
924 fxp_init_body(sc, 0);
925 fxp_stop(sc);
926 FXP_UNLOCK(sc);
927 }
928
929 fail:
930 if (error)
931 fxp_release(sc);
932 return (error);
933 }
934
935 /*
936 * Release all resources. The softc lock should not be held and the
937 * interrupt should already be torn down.
938 */
939 static void
fxp_release(struct fxp_softc * sc)940 fxp_release(struct fxp_softc *sc)
941 {
942 struct fxp_rx *rxp;
943 struct fxp_tx *txp;
944 int i;
945
946 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
947 KASSERT(sc->ih == NULL,
948 ("fxp_release() called with intr handle still active"));
949 if (sc->miibus)
950 device_delete_child(sc->dev, sc->miibus);
951 bus_generic_detach(sc->dev);
952 ifmedia_removeall(&sc->sc_media);
953 if (sc->fxp_desc.cbl_list) {
954 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
955 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
956 sc->cbl_map);
957 }
958 if (sc->fxp_stats) {
959 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
960 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
961 }
962 if (sc->mcsp) {
963 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
964 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
965 }
966 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
967 if (sc->fxp_rxmtag) {
968 for (i = 0; i < FXP_NRFABUFS; i++) {
969 rxp = &sc->fxp_desc.rx_list[i];
970 if (rxp->rx_mbuf != NULL) {
971 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
972 BUS_DMASYNC_POSTREAD);
973 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
974 m_freem(rxp->rx_mbuf);
975 }
976 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
977 }
978 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
979 bus_dma_tag_destroy(sc->fxp_rxmtag);
980 }
981 if (sc->fxp_txmtag) {
982 for (i = 0; i < FXP_NTXCB; i++) {
983 txp = &sc->fxp_desc.tx_list[i];
984 if (txp->tx_mbuf != NULL) {
985 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
986 BUS_DMASYNC_POSTWRITE);
987 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
988 m_freem(txp->tx_mbuf);
989 }
990 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
991 }
992 bus_dma_tag_destroy(sc->fxp_txmtag);
993 }
994 if (sc->fxp_stag)
995 bus_dma_tag_destroy(sc->fxp_stag);
996 if (sc->cbl_tag)
997 bus_dma_tag_destroy(sc->cbl_tag);
998 if (sc->mcs_tag)
999 bus_dma_tag_destroy(sc->mcs_tag);
1000 if (sc->ifp)
1001 if_free(sc->ifp);
1002
1003 mtx_destroy(&sc->sc_mtx);
1004 }
1005
1006 /*
1007 * Detach interface.
1008 */
1009 static int
fxp_detach(device_t dev)1010 fxp_detach(device_t dev)
1011 {
1012 struct fxp_softc *sc = device_get_softc(dev);
1013
1014 #ifdef DEVICE_POLLING
1015 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1016 ether_poll_deregister(sc->ifp);
1017 #endif
1018
1019 FXP_LOCK(sc);
1020 /*
1021 * Stop DMA and drop transmit queue, but disable interrupts first.
1022 */
1023 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1024 fxp_stop(sc);
1025 FXP_UNLOCK(sc);
1026 callout_drain(&sc->stat_ch);
1027
1028 /*
1029 * Close down routes etc.
1030 */
1031 ether_ifdetach(sc->ifp);
1032
1033 /*
1034 * Unhook interrupt before dropping lock. This is to prevent
1035 * races with fxp_intr().
1036 */
1037 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1038 sc->ih = NULL;
1039
1040 /* Release our allocated resources. */
1041 fxp_release(sc);
1042 return (0);
1043 }
1044
1045 /*
1046 * Device shutdown routine. Called at system shutdown after sync. The
1047 * main purpose of this routine is to shut off receiver DMA so that
1048 * kernel memory doesn't get clobbered during warmboot.
1049 */
1050 static int
fxp_shutdown(device_t dev)1051 fxp_shutdown(device_t dev)
1052 {
1053
1054 /*
1055 * Make sure that DMA is disabled prior to reboot. Not doing
1056 * do could allow DMA to corrupt kernel memory during the
1057 * reboot before the driver initializes.
1058 */
1059 return (fxp_suspend(dev));
1060 }
1061
1062 /*
1063 * Device suspend routine. Stop the interface and save some PCI
1064 * settings in case the BIOS doesn't restore them properly on
1065 * resume.
1066 */
1067 static int
fxp_suspend(device_t dev)1068 fxp_suspend(device_t dev)
1069 {
1070 struct fxp_softc *sc = device_get_softc(dev);
1071 if_t ifp;
1072 int pmc;
1073 uint16_t pmstat;
1074
1075 FXP_LOCK(sc);
1076
1077 ifp = sc->ifp;
1078 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1079 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1080 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1081 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1082 /* Request PME. */
1083 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1084 sc->flags |= FXP_FLAG_WOL;
1085 /* Reconfigure hardware to accept magic frames. */
1086 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1087 fxp_init_body(sc, 0);
1088 }
1089 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1090 }
1091 fxp_stop(sc);
1092
1093 sc->suspended = 1;
1094
1095 FXP_UNLOCK(sc);
1096 return (0);
1097 }
1098
1099 /*
1100 * Device resume routine. re-enable busmastering, and restart the interface if
1101 * appropriate.
1102 */
1103 static int
fxp_resume(device_t dev)1104 fxp_resume(device_t dev)
1105 {
1106 struct fxp_softc *sc = device_get_softc(dev);
1107 if_t ifp = sc->ifp;
1108 int pmc;
1109 uint16_t pmstat;
1110
1111 FXP_LOCK(sc);
1112
1113 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1114 sc->flags &= ~FXP_FLAG_WOL;
1115 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1116 /* Disable PME and clear PME status. */
1117 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1118 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1119 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1120 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1121 CSR_READ_1(sc, FXP_CSR_PMDR));
1122 }
1123
1124 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1125 DELAY(10);
1126
1127 /* reinitialize interface if necessary */
1128 if (if_getflags(ifp) & IFF_UP)
1129 fxp_init_body(sc, 1);
1130
1131 sc->suspended = 0;
1132
1133 FXP_UNLOCK(sc);
1134 return (0);
1135 }
1136
1137 static void
fxp_eeprom_shiftin(struct fxp_softc * sc,int data,int length)1138 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1139 {
1140 uint16_t reg;
1141 int x;
1142
1143 /*
1144 * Shift in data.
1145 */
1146 for (x = 1 << (length - 1); x; x >>= 1) {
1147 if (data & x)
1148 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1149 else
1150 reg = FXP_EEPROM_EECS;
1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1152 DELAY(1);
1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1154 DELAY(1);
1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1156 DELAY(1);
1157 }
1158 }
1159
1160 /*
1161 * Read from the serial EEPROM. Basically, you manually shift in
1162 * the read opcode (one bit at a time) and then shift in the address,
1163 * and then you shift out the data (all of this one bit at a time).
1164 * The word size is 16 bits, so you have to provide the address for
1165 * every 16 bits of data.
1166 */
1167 static uint16_t
fxp_eeprom_getword(struct fxp_softc * sc,int offset,int autosize)1168 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1169 {
1170 uint16_t reg, data;
1171 int x;
1172
1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1174 /*
1175 * Shift in read opcode.
1176 */
1177 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1178 /*
1179 * Shift in address.
1180 */
1181 data = 0;
1182 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1183 if (offset & x)
1184 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1185 else
1186 reg = FXP_EEPROM_EECS;
1187 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1188 DELAY(1);
1189 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1190 DELAY(1);
1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1192 DELAY(1);
1193 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1194 data++;
1195 if (autosize && reg == 0) {
1196 sc->eeprom_size = data;
1197 break;
1198 }
1199 }
1200 /*
1201 * Shift out data.
1202 */
1203 data = 0;
1204 reg = FXP_EEPROM_EECS;
1205 for (x = 1 << 15; x; x >>= 1) {
1206 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1207 DELAY(1);
1208 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1209 data |= x;
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1211 DELAY(1);
1212 }
1213 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1214 DELAY(1);
1215
1216 return (data);
1217 }
1218
1219 static void
fxp_eeprom_putword(struct fxp_softc * sc,int offset,uint16_t data)1220 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1221 {
1222 int i;
1223
1224 /*
1225 * Erase/write enable.
1226 */
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1228 fxp_eeprom_shiftin(sc, 0x4, 3);
1229 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1230 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1231 DELAY(1);
1232 /*
1233 * Shift in write opcode, address, data.
1234 */
1235 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1236 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1237 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1238 fxp_eeprom_shiftin(sc, data, 16);
1239 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1240 DELAY(1);
1241 /*
1242 * Wait for EEPROM to finish up.
1243 */
1244 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1245 DELAY(1);
1246 for (i = 0; i < 1000; i++) {
1247 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1248 break;
1249 DELAY(50);
1250 }
1251 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1252 DELAY(1);
1253 /*
1254 * Erase/write disable.
1255 */
1256 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1257 fxp_eeprom_shiftin(sc, 0x4, 3);
1258 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1259 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1260 DELAY(1);
1261 }
1262
1263 /*
1264 * From NetBSD:
1265 *
1266 * Figure out EEPROM size.
1267 *
1268 * 559's can have either 64-word or 256-word EEPROMs, the 558
1269 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1270 * talks about the existence of 16 to 256 word EEPROMs.
1271 *
1272 * The only known sizes are 64 and 256, where the 256 version is used
1273 * by CardBus cards to store CIS information.
1274 *
1275 * The address is shifted in msb-to-lsb, and after the last
1276 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1277 * after which follows the actual data. We try to detect this zero, by
1278 * probing the data-out bit in the EEPROM control register just after
1279 * having shifted in a bit. If the bit is zero, we assume we've
1280 * shifted enough address bits. The data-out should be tri-state,
1281 * before this, which should translate to a logical one.
1282 */
1283 static void
fxp_autosize_eeprom(struct fxp_softc * sc)1284 fxp_autosize_eeprom(struct fxp_softc *sc)
1285 {
1286
1287 /* guess maximum size of 256 words */
1288 sc->eeprom_size = 8;
1289
1290 /* autosize */
1291 (void) fxp_eeprom_getword(sc, 0, 1);
1292 }
1293
1294 static void
fxp_read_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1295 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1296 {
1297 int i;
1298
1299 for (i = 0; i < words; i++)
1300 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1301 }
1302
1303 static void
fxp_write_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1304 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1305 {
1306 int i;
1307
1308 for (i = 0; i < words; i++)
1309 fxp_eeprom_putword(sc, offset + i, data[i]);
1310 }
1311
1312 static void
fxp_load_eeprom(struct fxp_softc * sc)1313 fxp_load_eeprom(struct fxp_softc *sc)
1314 {
1315 int i;
1316 uint16_t cksum;
1317
1318 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1319 cksum = 0;
1320 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1321 cksum += sc->eeprom[i];
1322 cksum = 0xBABA - cksum;
1323 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1324 device_printf(sc->dev,
1325 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1326 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1327 }
1328
1329 /*
1330 * Grab the softc lock and call the real fxp_start_body() routine
1331 */
1332 static void
fxp_start(if_t ifp)1333 fxp_start(if_t ifp)
1334 {
1335 struct fxp_softc *sc = if_getsoftc(ifp);
1336
1337 FXP_LOCK(sc);
1338 fxp_start_body(ifp);
1339 FXP_UNLOCK(sc);
1340 }
1341
1342 /*
1343 * Start packet transmission on the interface.
1344 * This routine must be called with the softc lock held, and is an
1345 * internal entry point only.
1346 */
1347 static void
fxp_start_body(if_t ifp)1348 fxp_start_body(if_t ifp)
1349 {
1350 struct fxp_softc *sc = if_getsoftc(ifp);
1351 struct mbuf *mb_head;
1352 int txqueued;
1353
1354 FXP_LOCK_ASSERT(sc, MA_OWNED);
1355
1356 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1357 IFF_DRV_RUNNING)
1358 return;
1359
1360 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1361 fxp_txeof(sc);
1362 /*
1363 * We're finished if there is nothing more to add to the list or if
1364 * we're all filled up with buffers to transmit.
1365 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1366 * a NOP command when needed.
1367 */
1368 txqueued = 0;
1369 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) {
1370
1371 /*
1372 * Grab a packet to transmit.
1373 */
1374 mb_head = if_dequeue(ifp);
1375 if (mb_head == NULL)
1376 break;
1377
1378 if (fxp_encap(sc, &mb_head)) {
1379 if (mb_head == NULL)
1380 break;
1381 if_sendq_prepend(ifp, mb_head);
1382 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1383 }
1384 txqueued++;
1385 /*
1386 * Pass packet to bpf if there is a listener.
1387 */
1388 if_bpfmtap(ifp, mb_head);
1389 }
1390
1391 /*
1392 * We're finished. If we added to the list, issue a RESUME to get DMA
1393 * going again if suspended.
1394 */
1395 if (txqueued > 0) {
1396 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1398 fxp_scb_wait(sc);
1399 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1400 /*
1401 * Set a 5 second timer just in case we don't hear
1402 * from the card again.
1403 */
1404 sc->watchdog_timer = 5;
1405 }
1406 }
1407
1408 static int
fxp_encap(struct fxp_softc * sc,struct mbuf ** m_head)1409 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1410 {
1411 if_t ifp;
1412 struct mbuf *m;
1413 struct fxp_tx *txp;
1414 struct fxp_cb_tx *cbp;
1415 struct tcphdr *tcp;
1416 bus_dma_segment_t segs[FXP_NTXSEG];
1417 int error, i, nseg, tcp_payload;
1418
1419 FXP_LOCK_ASSERT(sc, MA_OWNED);
1420 ifp = sc->ifp;
1421
1422 tcp_payload = 0;
1423 tcp = NULL;
1424 /*
1425 * Get pointer to next available tx desc.
1426 */
1427 txp = sc->fxp_desc.tx_last->tx_next;
1428
1429 /*
1430 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1431 * Ethernet Controller Family Open Source Software
1432 * Developer Manual says:
1433 * Using software parsing is only allowed with legal
1434 * TCP/IP or UDP/IP packets.
1435 * ...
1436 * For all other datagrams, hardware parsing must
1437 * be used.
1438 * Software parsing appears to truncate ICMP and
1439 * fragmented UDP packets that contain one to three
1440 * bytes in the second (and final) mbuf of the packet.
1441 */
1442 if (sc->flags & FXP_FLAG_EXT_RFA)
1443 txp->tx_cb->ipcb_ip_activation_high =
1444 FXP_IPCB_HARDWAREPARSING_ENABLE;
1445
1446 m = *m_head;
1447 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1448 /*
1449 * 82550/82551 requires ethernet/IP/TCP headers must be
1450 * contained in the first active transmit buffer.
1451 */
1452 struct ether_header *eh;
1453 struct ip *ip;
1454 uint32_t ip_off, poff;
1455
1456 if (M_WRITABLE(*m_head) == 0) {
1457 /* Get a writable copy. */
1458 m = m_dup(*m_head, M_NOWAIT);
1459 m_freem(*m_head);
1460 if (m == NULL) {
1461 *m_head = NULL;
1462 return (ENOBUFS);
1463 }
1464 *m_head = m;
1465 }
1466 ip_off = sizeof(struct ether_header);
1467 m = m_pullup(*m_head, ip_off);
1468 if (m == NULL) {
1469 *m_head = NULL;
1470 return (ENOBUFS);
1471 }
1472 eh = mtod(m, struct ether_header *);
1473 /* Check the existence of VLAN tag. */
1474 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1475 ip_off = sizeof(struct ether_vlan_header);
1476 m = m_pullup(m, ip_off);
1477 if (m == NULL) {
1478 *m_head = NULL;
1479 return (ENOBUFS);
1480 }
1481 }
1482 m = m_pullup(m, ip_off + sizeof(struct ip));
1483 if (m == NULL) {
1484 *m_head = NULL;
1485 return (ENOBUFS);
1486 }
1487 ip = (struct ip *)(mtod(m, char *) + ip_off);
1488 poff = ip_off + (ip->ip_hl << 2);
1489 m = m_pullup(m, poff + sizeof(struct tcphdr));
1490 if (m == NULL) {
1491 *m_head = NULL;
1492 return (ENOBUFS);
1493 }
1494 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1495 m = m_pullup(m, poff + (tcp->th_off << 2));
1496 if (m == NULL) {
1497 *m_head = NULL;
1498 return (ENOBUFS);
1499 }
1500
1501 /*
1502 * Since 82550/82551 doesn't modify IP length and pseudo
1503 * checksum in the first frame driver should compute it.
1504 */
1505 ip = (struct ip *)(mtod(m, char *) + ip_off);
1506 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1507 ip->ip_sum = 0;
1508 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1509 (tcp->th_off << 2));
1510 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1511 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1512 m->m_pkthdr.tso_segsz));
1513 /* Compute total TCP payload. */
1514 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1515 tcp_payload -= tcp->th_off << 2;
1516 *m_head = m;
1517 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1518 /*
1519 * Deal with TCP/IP checksum offload. Note that
1520 * in order for TCP checksum offload to work,
1521 * the pseudo header checksum must have already
1522 * been computed and stored in the checksum field
1523 * in the TCP header. The stack should have
1524 * already done this for us.
1525 */
1526 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1527 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1528 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1529
1530 #ifdef FXP_IP_CSUM_WAR
1531 /*
1532 * XXX The 82550 chip appears to have trouble
1533 * dealing with IP header checksums in very small
1534 * datagrams, namely fragments from 1 to 3 bytes
1535 * in size. For example, say you want to transmit
1536 * a UDP packet of 1473 bytes. The packet will be
1537 * fragmented over two IP datagrams, the latter
1538 * containing only one byte of data. The 82550 will
1539 * botch the header checksum on the 1-byte fragment.
1540 * As long as the datagram contains 4 or more bytes
1541 * of data, you're ok.
1542 *
1543 * The following code attempts to work around this
1544 * problem: if the datagram is less than 38 bytes
1545 * in size (14 bytes ether header, 20 bytes IP header,
1546 * plus 4 bytes of data), we punt and compute the IP
1547 * header checksum by hand. This workaround doesn't
1548 * work very well, however, since it can be fooled
1549 * by things like VLAN tags and IP options that make
1550 * the header sizes/offsets vary.
1551 */
1552
1553 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1554 if (m->m_pkthdr.len < 38) {
1555 struct ip *ip;
1556 m->m_data += ETHER_HDR_LEN;
1557 ip = mtod(m, struct ip *);
1558 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1559 m->m_data -= ETHER_HDR_LEN;
1560 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1561 } else {
1562 txp->tx_cb->ipcb_ip_activation_high =
1563 FXP_IPCB_HARDWAREPARSING_ENABLE;
1564 txp->tx_cb->ipcb_ip_schedule |=
1565 FXP_IPCB_IP_CHECKSUM_ENABLE;
1566 }
1567 }
1568 #endif
1569 }
1570
1571 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1572 segs, &nseg, 0);
1573 if (error == EFBIG) {
1574 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1575 if (m == NULL) {
1576 m_freem(*m_head);
1577 *m_head = NULL;
1578 return (ENOMEM);
1579 }
1580 *m_head = m;
1581 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1582 *m_head, segs, &nseg, 0);
1583 if (error != 0) {
1584 m_freem(*m_head);
1585 *m_head = NULL;
1586 return (ENOMEM);
1587 }
1588 } else if (error != 0)
1589 return (error);
1590 if (nseg == 0) {
1591 m_freem(*m_head);
1592 *m_head = NULL;
1593 return (EIO);
1594 }
1595
1596 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1597 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1598
1599 cbp = txp->tx_cb;
1600 for (i = 0; i < nseg; i++) {
1601 /*
1602 * If this is an 82550/82551, then we're using extended
1603 * TxCBs _and_ we're using checksum offload. This means
1604 * that the TxCB is really an IPCB. One major difference
1605 * between the two is that with plain extended TxCBs,
1606 * the bottom half of the TxCB contains two entries from
1607 * the TBD array, whereas IPCBs contain just one entry:
1608 * one entry (8 bytes) has been sacrificed for the TCP/IP
1609 * checksum offload control bits. So to make things work
1610 * right, we have to start filling in the TBD array
1611 * starting from a different place depending on whether
1612 * the chip is an 82550/82551 or not.
1613 */
1614 if (sc->flags & FXP_FLAG_EXT_RFA) {
1615 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1616 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1617 } else {
1618 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1619 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1620 }
1621 }
1622 if (sc->flags & FXP_FLAG_EXT_RFA) {
1623 /* Configure dynamic TBD for 82550/82551. */
1624 cbp->tbd_number = 0xFF;
1625 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1626 } else
1627 cbp->tbd_number = nseg;
1628 /* Configure TSO. */
1629 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1630 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1631 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1632 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1633 FXP_IPCB_IP_CHECKSUM_ENABLE |
1634 FXP_IPCB_TCP_PACKET |
1635 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1636 }
1637 /* Configure VLAN hardware tag insertion. */
1638 if ((m->m_flags & M_VLANTAG) != 0) {
1639 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1640 txp->tx_cb->ipcb_ip_activation_high |=
1641 FXP_IPCB_INSERTVLAN_ENABLE;
1642 }
1643
1644 txp->tx_mbuf = m;
1645 txp->tx_cb->cb_status = 0;
1646 txp->tx_cb->byte_count = 0;
1647 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1648 txp->tx_cb->cb_command =
1649 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1650 FXP_CB_COMMAND_S);
1651 else
1652 txp->tx_cb->cb_command =
1653 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1654 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1655 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1656 txp->tx_cb->tx_threshold = tx_threshold;
1657
1658 /*
1659 * Advance the end of list forward.
1660 */
1661 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1662 sc->fxp_desc.tx_last = txp;
1663
1664 /*
1665 * Advance the beginning of the list forward if there are
1666 * no other packets queued (when nothing is queued, tx_first
1667 * sits on the last TxCB that was sent out).
1668 */
1669 if (sc->tx_queued == 0)
1670 sc->fxp_desc.tx_first = txp;
1671
1672 sc->tx_queued++;
1673
1674 return (0);
1675 }
1676
1677 #ifdef DEVICE_POLLING
1678 static poll_handler_t fxp_poll;
1679
1680 static int
fxp_poll(if_t ifp,enum poll_cmd cmd,int count)1681 fxp_poll(if_t ifp, enum poll_cmd cmd, int count)
1682 {
1683 struct fxp_softc *sc = if_getsoftc(ifp);
1684 uint8_t statack;
1685 int rx_npkts = 0;
1686
1687 FXP_LOCK(sc);
1688 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1689 FXP_UNLOCK(sc);
1690 return (rx_npkts);
1691 }
1692
1693 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1694 FXP_SCB_STATACK_FR;
1695 if (cmd == POLL_AND_CHECK_STATUS) {
1696 uint8_t tmp;
1697
1698 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1699 if (tmp == 0xff || tmp == 0) {
1700 FXP_UNLOCK(sc);
1701 return (rx_npkts); /* nothing to do */
1702 }
1703 tmp &= ~statack;
1704 /* ack what we can */
1705 if (tmp != 0)
1706 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1707 statack |= tmp;
1708 }
1709 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1710 FXP_UNLOCK(sc);
1711 return (rx_npkts);
1712 }
1713 #endif /* DEVICE_POLLING */
1714
1715 /*
1716 * Process interface interrupts.
1717 */
1718 static void
fxp_intr(void * xsc)1719 fxp_intr(void *xsc)
1720 {
1721 struct fxp_softc *sc = xsc;
1722 if_t ifp = sc->ifp;
1723 uint8_t statack;
1724
1725 FXP_LOCK(sc);
1726 if (sc->suspended) {
1727 FXP_UNLOCK(sc);
1728 return;
1729 }
1730
1731 #ifdef DEVICE_POLLING
1732 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1733 FXP_UNLOCK(sc);
1734 return;
1735 }
1736 #endif
1737 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1738 /*
1739 * It should not be possible to have all bits set; the
1740 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1741 * all bits are set, this may indicate that the card has
1742 * been physically ejected, so ignore it.
1743 */
1744 if (statack == 0xff) {
1745 FXP_UNLOCK(sc);
1746 return;
1747 }
1748
1749 /*
1750 * First ACK all the interrupts in this pass.
1751 */
1752 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1753 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1754 fxp_intr_body(sc, ifp, statack, -1);
1755 }
1756 FXP_UNLOCK(sc);
1757 }
1758
1759 static void
fxp_txeof(struct fxp_softc * sc)1760 fxp_txeof(struct fxp_softc *sc)
1761 {
1762 if_t ifp;
1763 struct fxp_tx *txp;
1764
1765 ifp = sc->ifp;
1766 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1767 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1768 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1769 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1770 txp = txp->tx_next) {
1771 if (txp->tx_mbuf != NULL) {
1772 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1773 BUS_DMASYNC_POSTWRITE);
1774 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1775 m_freem(txp->tx_mbuf);
1776 txp->tx_mbuf = NULL;
1777 /* clear this to reset csum offload bits */
1778 txp->tx_cb->tbd[0].tb_addr = 0;
1779 }
1780 sc->tx_queued--;
1781 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1782 }
1783 sc->fxp_desc.tx_first = txp;
1784 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1785 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1786 if (sc->tx_queued == 0)
1787 sc->watchdog_timer = 0;
1788 }
1789
1790 static void
fxp_rxcsum(struct fxp_softc * sc,if_t ifp,struct mbuf * m,uint16_t status,int pos)1791 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m,
1792 uint16_t status, int pos)
1793 {
1794 struct ether_header *eh;
1795 struct ip *ip;
1796 struct udphdr *uh;
1797 int32_t hlen, len, pktlen, temp32;
1798 uint16_t csum, *opts;
1799
1800 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1801 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1802 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1803 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1804 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1805 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1806 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1807 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1808 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1809 CSUM_PSEUDO_HDR;
1810 m->m_pkthdr.csum_data = 0xffff;
1811 }
1812 }
1813 return;
1814 }
1815
1816 pktlen = m->m_pkthdr.len;
1817 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1818 return;
1819 eh = mtod(m, struct ether_header *);
1820 if (eh->ether_type != htons(ETHERTYPE_IP))
1821 return;
1822 ip = (struct ip *)(eh + 1);
1823 if (ip->ip_v != IPVERSION)
1824 return;
1825
1826 hlen = ip->ip_hl << 2;
1827 pktlen -= sizeof(struct ether_header);
1828 if (hlen < sizeof(struct ip))
1829 return;
1830 if (ntohs(ip->ip_len) < hlen)
1831 return;
1832 if (ntohs(ip->ip_len) != pktlen)
1833 return;
1834 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1835 return; /* can't handle fragmented packet */
1836
1837 switch (ip->ip_p) {
1838 case IPPROTO_TCP:
1839 if (pktlen < (hlen + sizeof(struct tcphdr)))
1840 return;
1841 break;
1842 case IPPROTO_UDP:
1843 if (pktlen < (hlen + sizeof(struct udphdr)))
1844 return;
1845 uh = (struct udphdr *)((caddr_t)ip + hlen);
1846 if (uh->uh_sum == 0)
1847 return; /* no checksum */
1848 break;
1849 default:
1850 return;
1851 }
1852 /* Extract computed checksum. */
1853 csum = be16dec(mtod(m, char *) + pos);
1854 /* checksum fixup for IP options */
1855 len = hlen - sizeof(struct ip);
1856 if (len > 0) {
1857 opts = (uint16_t *)(ip + 1);
1858 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1859 temp32 = csum - *opts;
1860 temp32 = (temp32 >> 16) + (temp32 & 65535);
1861 csum = temp32 & 65535;
1862 }
1863 }
1864 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1865 m->m_pkthdr.csum_data = csum;
1866 }
1867
1868 static int
fxp_intr_body(struct fxp_softc * sc,if_t ifp,uint8_t statack,int count)1869 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack,
1870 int count)
1871 {
1872 struct mbuf *m;
1873 struct fxp_rx *rxp;
1874 struct fxp_rfa *rfa;
1875 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1876 int rx_npkts;
1877 uint16_t status;
1878
1879 rx_npkts = 0;
1880 FXP_LOCK_ASSERT(sc, MA_OWNED);
1881
1882 if (rnr)
1883 sc->rnr++;
1884 #ifdef DEVICE_POLLING
1885 /* Pick up a deferred RNR condition if `count' ran out last time. */
1886 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1887 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1888 rnr = 1;
1889 }
1890 #endif
1891
1892 /*
1893 * Free any finished transmit mbuf chains.
1894 *
1895 * Handle the CNA event likt a CXTNO event. It used to
1896 * be that this event (control unit not ready) was not
1897 * encountered, but it is now with the SMPng modifications.
1898 * The exact sequence of events that occur when the interface
1899 * is brought up are different now, and if this event
1900 * goes unhandled, the configuration/rxfilter setup sequence
1901 * can stall for several seconds. The result is that no
1902 * packets go out onto the wire for about 5 to 10 seconds
1903 * after the interface is ifconfig'ed for the first time.
1904 */
1905 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1906 fxp_txeof(sc);
1907
1908 /*
1909 * Try to start more packets transmitting.
1910 */
1911 if (!if_sendq_empty(ifp))
1912 fxp_start_body(ifp);
1913
1914 /*
1915 * Just return if nothing happened on the receive side.
1916 */
1917 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1918 return (rx_npkts);
1919
1920 /*
1921 * Process receiver interrupts. If a no-resource (RNR)
1922 * condition exists, get whatever packets we can and
1923 * re-start the receiver.
1924 *
1925 * When using polling, we do not process the list to completion,
1926 * so when we get an RNR interrupt we must defer the restart
1927 * until we hit the last buffer with the C bit set.
1928 * If we run out of cycles and rfa_headm has the C bit set,
1929 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1930 * that the info will be used in the subsequent polling cycle.
1931 */
1932 for (;;) {
1933 rxp = sc->fxp_desc.rx_head;
1934 m = rxp->rx_mbuf;
1935 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1936 RFA_ALIGNMENT_FUDGE);
1937 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1938 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1939
1940 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1941 if (count >= 0 && count-- == 0) {
1942 if (rnr) {
1943 /* Defer RNR processing until the next time. */
1944 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1945 rnr = 0;
1946 }
1947 break;
1948 }
1949 #endif /* DEVICE_POLLING */
1950
1951 status = le16toh(rfa->rfa_status);
1952 if ((status & FXP_RFA_STATUS_C) == 0)
1953 break;
1954
1955 if ((status & FXP_RFA_STATUS_RNR) != 0)
1956 rnr++;
1957 /*
1958 * Advance head forward.
1959 */
1960 sc->fxp_desc.rx_head = rxp->rx_next;
1961
1962 /*
1963 * Add a new buffer to the receive chain.
1964 * If this fails, the old buffer is recycled
1965 * instead.
1966 */
1967 if (fxp_new_rfabuf(sc, rxp) == 0) {
1968 int total_len;
1969
1970 /*
1971 * Fetch packet length (the top 2 bits of
1972 * actual_size are flags set by the controller
1973 * upon completion), and drop the packet in case
1974 * of bogus length or CRC errors.
1975 */
1976 total_len = le16toh(rfa->actual_size) & 0x3fff;
1977 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1978 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1979 /* Adjust for appended checksum bytes. */
1980 total_len -= 2;
1981 }
1982 if (total_len < (int)sizeof(struct ether_header) ||
1983 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1984 sc->rfa_size) ||
1985 status & (FXP_RFA_STATUS_CRC |
1986 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1987 m_freem(m);
1988 fxp_add_rfabuf(sc, rxp);
1989 continue;
1990 }
1991
1992 m->m_pkthdr.len = m->m_len = total_len;
1993 if_setrcvif(m, ifp);
1994
1995 /* Do IP checksum checking. */
1996 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1997 fxp_rxcsum(sc, ifp, m, status, total_len);
1998 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1999 (status & FXP_RFA_STATUS_VLAN) != 0) {
2000 m->m_pkthdr.ether_vtag =
2001 ntohs(rfa->rfax_vlan_id);
2002 m->m_flags |= M_VLANTAG;
2003 }
2004 /*
2005 * Drop locks before calling if_input() since it
2006 * may re-enter fxp_start() in the netisr case.
2007 * This would result in a lock reversal. Better
2008 * performance might be obtained by chaining all
2009 * packets received, dropping the lock, and then
2010 * calling if_input() on each one.
2011 */
2012 FXP_UNLOCK(sc);
2013 if_input(ifp, m);
2014 FXP_LOCK(sc);
2015 rx_npkts++;
2016 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2017 return (rx_npkts);
2018 } else {
2019 /* Reuse RFA and loaded DMA map. */
2020 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2021 fxp_discard_rfabuf(sc, rxp);
2022 }
2023 fxp_add_rfabuf(sc, rxp);
2024 }
2025 if (rnr) {
2026 fxp_scb_wait(sc);
2027 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2028 sc->fxp_desc.rx_head->rx_addr);
2029 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2030 }
2031 return (rx_npkts);
2032 }
2033
2034 static void
fxp_update_stats(struct fxp_softc * sc)2035 fxp_update_stats(struct fxp_softc *sc)
2036 {
2037 if_t ifp = sc->ifp;
2038 struct fxp_stats *sp = sc->fxp_stats;
2039 struct fxp_hwstats *hsp;
2040 uint32_t *status;
2041
2042 FXP_LOCK_ASSERT(sc, MA_OWNED);
2043
2044 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2045 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2046 /* Update statistical counters. */
2047 if (sc->revision >= FXP_REV_82559_A0)
2048 status = &sp->completion_status;
2049 else if (sc->revision >= FXP_REV_82558_A4)
2050 status = (uint32_t *)&sp->tx_tco;
2051 else
2052 status = &sp->tx_pause;
2053 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2054 hsp = &sc->fxp_hwstats;
2055 hsp->tx_good += le32toh(sp->tx_good);
2056 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2057 hsp->tx_latecols += le32toh(sp->tx_latecols);
2058 hsp->tx_underruns += le32toh(sp->tx_underruns);
2059 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2060 hsp->tx_deffered += le32toh(sp->tx_deffered);
2061 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2062 hsp->tx_multiple_collisions +=
2063 le32toh(sp->tx_multiple_collisions);
2064 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2065 hsp->rx_good += le32toh(sp->rx_good);
2066 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2067 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2068 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2069 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2070 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2071 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2072 hsp->tx_pause += le32toh(sp->tx_pause);
2073 hsp->rx_pause += le32toh(sp->rx_pause);
2074 hsp->rx_controls += le32toh(sp->rx_controls);
2075 hsp->tx_tco += le16toh(sp->tx_tco);
2076 hsp->rx_tco += le16toh(sp->rx_tco);
2077
2078 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good));
2079 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2080 le32toh(sp->tx_total_collisions));
2081 if (sp->rx_good) {
2082 if_inc_counter(ifp, IFCOUNTER_IPACKETS,
2083 le32toh(sp->rx_good));
2084 sc->rx_idle_secs = 0;
2085 } else if (sc->flags & FXP_FLAG_RXBUG) {
2086 /*
2087 * Receiver's been idle for another second.
2088 */
2089 sc->rx_idle_secs++;
2090 }
2091 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2092 le32toh(sp->rx_crc_errors) +
2093 le32toh(sp->rx_alignment_errors) +
2094 le32toh(sp->rx_rnr_errors) +
2095 le32toh(sp->rx_overrun_errors));
2096 /*
2097 * If any transmit underruns occurred, bump up the transmit
2098 * threshold by another 512 bytes (64 * 8).
2099 */
2100 if (sp->tx_underruns) {
2101 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2102 le32toh(sp->tx_underruns));
2103 if (tx_threshold < 192)
2104 tx_threshold += 64;
2105 }
2106 *status = 0;
2107 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2108 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2109 }
2110 }
2111
2112 /*
2113 * Update packet in/out/collision statistics. The i82557 doesn't
2114 * allow you to access these counters without doing a fairly
2115 * expensive DMA to get _all_ of the statistics it maintains, so
2116 * we do this operation here only once per second. The statistics
2117 * counters in the kernel are updated from the previous dump-stats
2118 * DMA and then a new dump-stats DMA is started. The on-chip
2119 * counters are zeroed when the DMA completes. If we can't start
2120 * the DMA immediately, we don't wait - we just prepare to read
2121 * them again next time.
2122 */
2123 static void
fxp_tick(void * xsc)2124 fxp_tick(void *xsc)
2125 {
2126 struct fxp_softc *sc = xsc;
2127 if_t ifp = sc->ifp;
2128
2129 FXP_LOCK_ASSERT(sc, MA_OWNED);
2130
2131 /* Update statistical counters. */
2132 fxp_update_stats(sc);
2133
2134 /*
2135 * Release any xmit buffers that have completed DMA. This isn't
2136 * strictly necessary to do here, but it's advantagous for mbufs
2137 * with external storage to be released in a timely manner rather
2138 * than being defered for a potentially long time. This limits
2139 * the delay to a maximum of one second.
2140 */
2141 fxp_txeof(sc);
2142
2143 /*
2144 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2145 * then assume the receiver has locked up and attempt to clear
2146 * the condition by reprogramming the multicast filter. This is
2147 * a work-around for a bug in the 82557 where the receiver locks
2148 * up if it gets certain types of garbage in the synchronization
2149 * bits prior to the packet header. This bug is supposed to only
2150 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2151 * mode as well (perhaps due to a 10/100 speed transition).
2152 */
2153 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2154 sc->rx_idle_secs = 0;
2155 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2156 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2157 fxp_init_body(sc, 1);
2158 }
2159 return;
2160 }
2161 /*
2162 * If there is no pending command, start another stats
2163 * dump. Otherwise punt for now.
2164 */
2165 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2166 /*
2167 * Start another stats dump.
2168 */
2169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2170 }
2171 if (sc->miibus != NULL)
2172 mii_tick(device_get_softc(sc->miibus));
2173
2174 /*
2175 * Check that chip hasn't hung.
2176 */
2177 fxp_watchdog(sc);
2178
2179 /*
2180 * Schedule another timeout one second from now.
2181 */
2182 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2183 }
2184
2185 /*
2186 * Stop the interface. Cancels the statistics updater and resets
2187 * the interface.
2188 */
2189 static void
fxp_stop(struct fxp_softc * sc)2190 fxp_stop(struct fxp_softc *sc)
2191 {
2192 if_t ifp = sc->ifp;
2193 struct fxp_tx *txp;
2194 int i;
2195
2196 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2197 sc->watchdog_timer = 0;
2198
2199 /*
2200 * Cancel stats updater.
2201 */
2202 callout_stop(&sc->stat_ch);
2203
2204 /*
2205 * Preserve PCI configuration, configure, IA/multicast
2206 * setup and put RU and CU into idle state.
2207 */
2208 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2209 DELAY(50);
2210 /* Disable interrupts. */
2211 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2212
2213 fxp_update_stats(sc);
2214
2215 /*
2216 * Release any xmit buffers.
2217 */
2218 txp = sc->fxp_desc.tx_list;
2219 for (i = 0; i < FXP_NTXCB; i++) {
2220 if (txp[i].tx_mbuf != NULL) {
2221 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2222 BUS_DMASYNC_POSTWRITE);
2223 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map);
2224 m_freem(txp[i].tx_mbuf);
2225 txp[i].tx_mbuf = NULL;
2226 /* clear this to reset csum offload bits */
2227 txp[i].tx_cb->tbd[0].tb_addr = 0;
2228 }
2229 }
2230 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2231 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2232 sc->tx_queued = 0;
2233 }
2234
2235 /*
2236 * Watchdog/transmission transmit timeout handler. Called when a
2237 * transmission is started on the interface, but no interrupt is
2238 * received before the timeout. This usually indicates that the
2239 * card has wedged for some reason.
2240 */
2241 static void
fxp_watchdog(struct fxp_softc * sc)2242 fxp_watchdog(struct fxp_softc *sc)
2243 {
2244 if_t ifp = sc->ifp;
2245
2246 FXP_LOCK_ASSERT(sc, MA_OWNED);
2247
2248 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2249 return;
2250
2251 device_printf(sc->dev, "device timeout\n");
2252 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2253
2254 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2255 fxp_init_body(sc, 1);
2256 }
2257
2258 /*
2259 * Acquire locks and then call the real initialization function. This
2260 * is necessary because ether_ioctl() calls if_init() and this would
2261 * result in mutex recursion if the mutex was held.
2262 */
2263 static void
fxp_init(void * xsc)2264 fxp_init(void *xsc)
2265 {
2266 struct fxp_softc *sc = xsc;
2267
2268 FXP_LOCK(sc);
2269 fxp_init_body(sc, 1);
2270 FXP_UNLOCK(sc);
2271 }
2272
2273 /*
2274 * Perform device initialization. This routine must be called with the
2275 * softc lock held.
2276 */
2277 static void
fxp_init_body(struct fxp_softc * sc,int setmedia)2278 fxp_init_body(struct fxp_softc *sc, int setmedia)
2279 {
2280 if_t ifp = sc->ifp;
2281 struct mii_data *mii;
2282 struct fxp_cb_config *cbp;
2283 struct fxp_cb_ias *cb_ias;
2284 struct fxp_cb_tx *tcbp;
2285 struct fxp_tx *txp;
2286 int i, prm;
2287
2288 FXP_LOCK_ASSERT(sc, MA_OWNED);
2289
2290 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2291 return;
2292
2293 /*
2294 * Cancel any pending I/O
2295 */
2296 fxp_stop(sc);
2297
2298 /*
2299 * Issue software reset, which also unloads the microcode.
2300 */
2301 sc->flags &= ~FXP_FLAG_UCODE;
2302 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2303 DELAY(50);
2304
2305 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0;
2306
2307 /*
2308 * Initialize base of CBL and RFA memory. Loading with zero
2309 * sets it up for regular linear addressing.
2310 */
2311 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2312 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2313
2314 fxp_scb_wait(sc);
2315 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2316
2317 /*
2318 * Initialize base of dump-stats buffer.
2319 */
2320 fxp_scb_wait(sc);
2321 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2322 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2323 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2324 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2325 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2326
2327 /*
2328 * Attempt to load microcode if requested.
2329 * For ICH based controllers do not load microcode.
2330 */
2331 if (sc->ident->ich == 0) {
2332 if (if_getflags(ifp) & IFF_LINK0 &&
2333 (sc->flags & FXP_FLAG_UCODE) == 0)
2334 fxp_load_ucode(sc);
2335 }
2336
2337 /*
2338 * Set IFF_ALLMULTI status. It's needed in configure action
2339 * command.
2340 */
2341 fxp_mc_addrs(sc);
2342
2343 /*
2344 * We temporarily use memory that contains the TxCB list to
2345 * construct the config CB. The TxCB list memory is rebuilt
2346 * later.
2347 */
2348 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2349
2350 /*
2351 * This bcopy is kind of disgusting, but there are a bunch of must be
2352 * zero and must be one bits in this structure and this is the easiest
2353 * way to initialize them all to proper values.
2354 */
2355 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2356
2357 cbp->cb_status = 0;
2358 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2359 FXP_CB_COMMAND_EL);
2360 cbp->link_addr = 0xffffffff; /* (no) next command */
2361 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2362 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2363 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2364 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2365 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2366 cbp->type_enable = 0; /* actually reserved */
2367 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2368 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2369 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2370 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2371 cbp->dma_mbce = 0; /* (disable) dma max counters */
2372 cbp->late_scb = 0; /* (don't) defer SCB update */
2373 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2374 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2375 cbp->ci_int = 1; /* interrupt on CU idle */
2376 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2377 cbp->ext_stats_dis = 1; /* disable extended counters */
2378 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2379 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2380 cbp->disc_short_rx = !prm; /* discard short packets */
2381 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2382 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2383 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2384 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2385 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2386 cbp->csma_dis = 0; /* (don't) disable link */
2387 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2388 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0;
2389 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2390 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2391 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2392 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2393 cbp->nsai = 1; /* (don't) disable source addr insert */
2394 cbp->preamble_length = 2; /* (7 byte) preamble */
2395 cbp->loopback = 0; /* (don't) loopback */
2396 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2397 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2398 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2399 cbp->promiscuous = prm; /* promiscuous mode */
2400 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2401 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2402 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2403 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2404 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2405
2406 cbp->stripping = !prm; /* truncate rx packet to byte count */
2407 cbp->padding = 1; /* (do) pad short tx packets */
2408 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2409 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2410 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2411 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2412 cbp->force_fdx = 0; /* (don't) force full duplex */
2413 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2414 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2415 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm;
2416 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2417 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2418 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2419
2420 if (sc->revision == FXP_REV_82557) {
2421 /*
2422 * The 82557 has no hardware flow control, the values
2423 * below are the defaults for the chip.
2424 */
2425 cbp->fc_delay_lsb = 0;
2426 cbp->fc_delay_msb = 0x40;
2427 cbp->pri_fc_thresh = 3;
2428 cbp->tx_fc_dis = 0;
2429 cbp->rx_fc_restop = 0;
2430 cbp->rx_fc_restart = 0;
2431 cbp->fc_filter = 0;
2432 cbp->pri_fc_loc = 1;
2433 } else {
2434 /* Set pause RX FIFO threshold to 1KB. */
2435 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2436 /* Set pause time. */
2437 cbp->fc_delay_lsb = 0xff;
2438 cbp->fc_delay_msb = 0xff;
2439 cbp->pri_fc_thresh = 3;
2440 mii = device_get_softc(sc->miibus);
2441 if ((IFM_OPTIONS(mii->mii_media_active) &
2442 IFM_ETH_TXPAUSE) != 0)
2443 /* enable transmit FC */
2444 cbp->tx_fc_dis = 0;
2445 else
2446 /* disable transmit FC */
2447 cbp->tx_fc_dis = 1;
2448 if ((IFM_OPTIONS(mii->mii_media_active) &
2449 IFM_ETH_RXPAUSE) != 0) {
2450 /* enable FC restart/restop frames */
2451 cbp->rx_fc_restart = 1;
2452 cbp->rx_fc_restop = 1;
2453 } else {
2454 /* disable FC restart/restop frames */
2455 cbp->rx_fc_restart = 0;
2456 cbp->rx_fc_restop = 0;
2457 }
2458 cbp->fc_filter = !prm; /* drop FC frames to host */
2459 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2460 }
2461
2462 /* Enable 82558 and 82559 extended statistics functionality. */
2463 if (sc->revision >= FXP_REV_82558_A4) {
2464 if (sc->revision >= FXP_REV_82559_A0) {
2465 /*
2466 * Extend configuration table size to 32
2467 * to include TCO configuration.
2468 */
2469 cbp->byte_count = 32;
2470 cbp->ext_stats_dis = 1;
2471 /* Enable TCO stats. */
2472 cbp->tno_int_or_tco_en = 1;
2473 cbp->gamla_rx = 1;
2474 } else
2475 cbp->ext_stats_dis = 0;
2476 }
2477
2478 /*
2479 * Start the config command/DMA.
2480 */
2481 fxp_scb_wait(sc);
2482 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2484 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2485 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2486 /* ...and wait for it to complete. */
2487 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2488
2489 /*
2490 * Now initialize the station address. Temporarily use the TxCB
2491 * memory area like we did above for the config CB.
2492 */
2493 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2494 cb_ias->cb_status = 0;
2495 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2496 cb_ias->link_addr = 0xffffffff;
2497 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2498
2499 /*
2500 * Start the IAS (Individual Address Setup) command/DMA.
2501 */
2502 fxp_scb_wait(sc);
2503 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2505 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2506 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2507 /* ...and wait for it to complete. */
2508 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2509
2510 /*
2511 * Initialize the multicast address list.
2512 */
2513 fxp_mc_setup(sc);
2514
2515 /*
2516 * Initialize transmit control block (TxCB) list.
2517 */
2518 txp = sc->fxp_desc.tx_list;
2519 tcbp = sc->fxp_desc.cbl_list;
2520 bzero(tcbp, FXP_TXCB_SZ);
2521 for (i = 0; i < FXP_NTXCB; i++) {
2522 txp[i].tx_mbuf = NULL;
2523 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2524 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2525 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2526 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2527 if (sc->flags & FXP_FLAG_EXT_TXCB)
2528 tcbp[i].tbd_array_addr =
2529 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2530 else
2531 tcbp[i].tbd_array_addr =
2532 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2533 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2534 }
2535 /*
2536 * Set the suspend flag on the first TxCB and start the control
2537 * unit. It will execute the NOP and then suspend.
2538 */
2539 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2540 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2542 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2543 sc->tx_queued = 1;
2544
2545 fxp_scb_wait(sc);
2546 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2547 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2548
2549 /*
2550 * Initialize receiver buffer area - RFA.
2551 */
2552 fxp_scb_wait(sc);
2553 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2554 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2555
2556 if (sc->miibus != NULL && setmedia != 0)
2557 mii_mediachg(device_get_softc(sc->miibus));
2558
2559 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2560
2561 /*
2562 * Enable interrupts.
2563 */
2564 #ifdef DEVICE_POLLING
2565 /*
2566 * ... but only do that if we are not polling. And because (presumably)
2567 * the default is interrupts on, we need to disable them explicitly!
2568 */
2569 if (if_getcapenable(ifp) & IFCAP_POLLING )
2570 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2571 else
2572 #endif /* DEVICE_POLLING */
2573 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2574
2575 /*
2576 * Start stats updater.
2577 */
2578 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2579 }
2580
2581 static int
fxp_serial_ifmedia_upd(if_t ifp)2582 fxp_serial_ifmedia_upd(if_t ifp)
2583 {
2584
2585 return (0);
2586 }
2587
2588 static void
fxp_serial_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2589 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2590 {
2591
2592 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2593 }
2594
2595 /*
2596 * Change media according to request.
2597 */
2598 static int
fxp_ifmedia_upd(if_t ifp)2599 fxp_ifmedia_upd(if_t ifp)
2600 {
2601 struct fxp_softc *sc = if_getsoftc(ifp);
2602 struct mii_data *mii;
2603 struct mii_softc *miisc;
2604
2605 mii = device_get_softc(sc->miibus);
2606 FXP_LOCK(sc);
2607 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2608 PHY_RESET(miisc);
2609 mii_mediachg(mii);
2610 FXP_UNLOCK(sc);
2611 return (0);
2612 }
2613
2614 /*
2615 * Notify the world which media we're using.
2616 */
2617 static void
fxp_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2618 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2619 {
2620 struct fxp_softc *sc = if_getsoftc(ifp);
2621 struct mii_data *mii;
2622
2623 mii = device_get_softc(sc->miibus);
2624 FXP_LOCK(sc);
2625 mii_pollstat(mii);
2626 ifmr->ifm_active = mii->mii_media_active;
2627 ifmr->ifm_status = mii->mii_media_status;
2628 FXP_UNLOCK(sc);
2629 }
2630
2631 /*
2632 * Add a buffer to the end of the RFA buffer list.
2633 * Return 0 if successful, 1 for failure. A failure results in
2634 * reusing the RFA buffer.
2635 * The RFA struct is stuck at the beginning of mbuf cluster and the
2636 * data pointer is fixed up to point just past it.
2637 */
2638 static int
fxp_new_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2639 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2640 {
2641 struct mbuf *m;
2642 struct fxp_rfa *rfa;
2643 bus_dmamap_t tmp_map;
2644 int error;
2645
2646 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2647 if (m == NULL)
2648 return (ENOBUFS);
2649
2650 /*
2651 * Move the data pointer up so that the incoming data packet
2652 * will be 32-bit aligned.
2653 */
2654 m->m_data += RFA_ALIGNMENT_FUDGE;
2655
2656 /*
2657 * Get a pointer to the base of the mbuf cluster and move
2658 * data start past it.
2659 */
2660 rfa = mtod(m, struct fxp_rfa *);
2661 m->m_data += sc->rfa_size;
2662 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2663
2664 rfa->rfa_status = 0;
2665 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2666 rfa->actual_size = 0;
2667 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2668 sc->rfa_size;
2669
2670 /*
2671 * Initialize the rest of the RFA. Note that since the RFA
2672 * is misaligned, we cannot store values directly. We're thus
2673 * using the le32enc() function which handles endianness and
2674 * is also alignment-safe.
2675 */
2676 le32enc(&rfa->link_addr, 0xffffffff);
2677 le32enc(&rfa->rbd_addr, 0xffffffff);
2678
2679 /* Map the RFA into DMA memory. */
2680 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2681 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2682 &rxp->rx_addr, BUS_DMA_NOWAIT);
2683 if (error) {
2684 m_freem(m);
2685 return (error);
2686 }
2687
2688 if (rxp->rx_mbuf != NULL)
2689 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2690 tmp_map = sc->spare_map;
2691 sc->spare_map = rxp->rx_map;
2692 rxp->rx_map = tmp_map;
2693 rxp->rx_mbuf = m;
2694
2695 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2696 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2697 return (0);
2698 }
2699
2700 static void
fxp_add_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2701 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2702 {
2703 struct fxp_rfa *p_rfa;
2704 struct fxp_rx *p_rx;
2705
2706 /*
2707 * If there are other buffers already on the list, attach this
2708 * one to the end by fixing up the tail to point to this one.
2709 */
2710 if (sc->fxp_desc.rx_head != NULL) {
2711 p_rx = sc->fxp_desc.rx_tail;
2712 p_rfa = (struct fxp_rfa *)
2713 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2714 p_rx->rx_next = rxp;
2715 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2716 p_rfa->rfa_control = 0;
2717 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2718 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2719 } else {
2720 rxp->rx_next = NULL;
2721 sc->fxp_desc.rx_head = rxp;
2722 }
2723 sc->fxp_desc.rx_tail = rxp;
2724 }
2725
2726 static void
fxp_discard_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2727 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2728 {
2729 struct mbuf *m;
2730 struct fxp_rfa *rfa;
2731
2732 m = rxp->rx_mbuf;
2733 m->m_data = m->m_ext.ext_buf;
2734 /*
2735 * Move the data pointer up so that the incoming data packet
2736 * will be 32-bit aligned.
2737 */
2738 m->m_data += RFA_ALIGNMENT_FUDGE;
2739
2740 /*
2741 * Get a pointer to the base of the mbuf cluster and move
2742 * data start past it.
2743 */
2744 rfa = mtod(m, struct fxp_rfa *);
2745 m->m_data += sc->rfa_size;
2746 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2747
2748 rfa->rfa_status = 0;
2749 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2750 rfa->actual_size = 0;
2751
2752 /*
2753 * Initialize the rest of the RFA. Note that since the RFA
2754 * is misaligned, we cannot store values directly. We're thus
2755 * using the le32enc() function which handles endianness and
2756 * is also alignment-safe.
2757 */
2758 le32enc(&rfa->link_addr, 0xffffffff);
2759 le32enc(&rfa->rbd_addr, 0xffffffff);
2760
2761 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2762 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2763 }
2764
2765 static int
fxp_miibus_readreg(device_t dev,int phy,int reg)2766 fxp_miibus_readreg(device_t dev, int phy, int reg)
2767 {
2768 struct fxp_softc *sc = device_get_softc(dev);
2769 int count = 10000;
2770 int value;
2771
2772 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2773 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2774
2775 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2776 && count--)
2777 DELAY(10);
2778
2779 if (count <= 0)
2780 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2781
2782 return (value & 0xffff);
2783 }
2784
2785 static int
fxp_miibus_writereg(device_t dev,int phy,int reg,int value)2786 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2787 {
2788 struct fxp_softc *sc = device_get_softc(dev);
2789 int count = 10000;
2790
2791 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2792 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2793 (value & 0xffff));
2794
2795 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2796 count--)
2797 DELAY(10);
2798
2799 if (count <= 0)
2800 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2801 return (0);
2802 }
2803
2804 static void
fxp_miibus_statchg(device_t dev)2805 fxp_miibus_statchg(device_t dev)
2806 {
2807 struct fxp_softc *sc;
2808 struct mii_data *mii;
2809 if_t ifp;
2810
2811 sc = device_get_softc(dev);
2812 mii = device_get_softc(sc->miibus);
2813 ifp = sc->ifp;
2814 if (mii == NULL || ifp == (void *)NULL ||
2815 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
2816 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2817 (IFM_AVALID | IFM_ACTIVE))
2818 return;
2819
2820 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2821 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2822 sc->cu_resume_bug = 1;
2823 else
2824 sc->cu_resume_bug = 0;
2825 /*
2826 * Call fxp_init_body in order to adjust the flow control settings.
2827 * Note that the 82557 doesn't support hardware flow control.
2828 */
2829 if (sc->revision == FXP_REV_82557)
2830 return;
2831 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2832 fxp_init_body(sc, 0);
2833 }
2834
2835 static int
fxp_ioctl(if_t ifp,u_long command,caddr_t data)2836 fxp_ioctl(if_t ifp, u_long command, caddr_t data)
2837 {
2838 struct fxp_softc *sc = if_getsoftc(ifp);
2839 struct ifreq *ifr = (struct ifreq *)data;
2840 struct mii_data *mii;
2841 int flag, mask, error = 0, reinit;
2842
2843 switch (command) {
2844 case SIOCSIFFLAGS:
2845 FXP_LOCK(sc);
2846 /*
2847 * If interface is marked up and not running, then start it.
2848 * If it is marked down and running, stop it.
2849 * XXX If it's up then re-initialize it. This is so flags
2850 * such as IFF_PROMISC are handled.
2851 */
2852 if (if_getflags(ifp) & IFF_UP) {
2853 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) &&
2854 ((if_getflags(ifp) ^ sc->if_flags) &
2855 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2856 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2857 fxp_init_body(sc, 0);
2858 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2859 fxp_init_body(sc, 1);
2860 } else {
2861 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2862 fxp_stop(sc);
2863 }
2864 sc->if_flags = if_getflags(ifp);
2865 FXP_UNLOCK(sc);
2866 break;
2867
2868 case SIOCADDMULTI:
2869 case SIOCDELMULTI:
2870 FXP_LOCK(sc);
2871 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2872 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2873 fxp_init_body(sc, 0);
2874 }
2875 FXP_UNLOCK(sc);
2876 break;
2877
2878 case SIOCSIFMEDIA:
2879 case SIOCGIFMEDIA:
2880 if (sc->miibus != NULL) {
2881 mii = device_get_softc(sc->miibus);
2882 error = ifmedia_ioctl(ifp, ifr,
2883 &mii->mii_media, command);
2884 } else {
2885 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2886 }
2887 break;
2888
2889 case SIOCSIFCAP:
2890 reinit = 0;
2891 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
2892 #ifdef DEVICE_POLLING
2893 if (mask & IFCAP_POLLING) {
2894 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2895 error = ether_poll_register(fxp_poll, ifp);
2896 if (error)
2897 return(error);
2898 FXP_LOCK(sc);
2899 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2900 FXP_SCB_INTR_DISABLE);
2901 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2902 FXP_UNLOCK(sc);
2903 } else {
2904 error = ether_poll_deregister(ifp);
2905 /* Enable interrupts in any case */
2906 FXP_LOCK(sc);
2907 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2908 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2909 FXP_UNLOCK(sc);
2910 }
2911 }
2912 #endif
2913 FXP_LOCK(sc);
2914 if ((mask & IFCAP_TXCSUM) != 0 &&
2915 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2916 if_togglecapenable(ifp, IFCAP_TXCSUM);
2917 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2918 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0);
2919 else
2920 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES);
2921 }
2922 if ((mask & IFCAP_RXCSUM) != 0 &&
2923 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
2924 if_togglecapenable(ifp, IFCAP_RXCSUM);
2925 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2926 reinit++;
2927 }
2928 if ((mask & IFCAP_TSO4) != 0 &&
2929 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2930 if_togglecapenable(ifp, IFCAP_TSO4);
2931 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2932 if_sethwassistbits(ifp, CSUM_TSO, 0);
2933 else
2934 if_sethwassistbits(ifp, 0, CSUM_TSO);
2935 }
2936 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2937 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2938 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2939 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2940 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) {
2941 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
2942 if (sc->revision != FXP_REV_82557)
2943 flag = FXP_FLAG_LONG_PKT_EN;
2944 else /* a hack to get long frames on the old chip */
2945 flag = FXP_FLAG_SAVE_BAD;
2946 sc->flags ^= flag;
2947 if (if_getflags(ifp) & IFF_UP)
2948 reinit++;
2949 }
2950 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2951 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2952 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2953 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2954 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2955 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2956 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2957 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2958 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2959 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2960 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO |
2961 IFCAP_VLAN_HWCSUM);
2962 reinit++;
2963 }
2964 if (reinit > 0 &&
2965 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2966 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2967 fxp_init_body(sc, 0);
2968 }
2969 FXP_UNLOCK(sc);
2970 if_vlancap(ifp);
2971 break;
2972
2973 default:
2974 error = ether_ioctl(ifp, command, data);
2975 }
2976 return (error);
2977 }
2978
2979 /*
2980 * Fill in the multicast address list and return number of entries.
2981 */
2982 static int
fxp_mc_addrs(struct fxp_softc * sc)2983 fxp_mc_addrs(struct fxp_softc *sc)
2984 {
2985 struct fxp_cb_mcs *mcsp = sc->mcsp;
2986 if_t ifp = sc->ifp;
2987 int nmcasts = 0;
2988
2989 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) {
2990 if_maddr_rlock(ifp);
2991 if_setupmultiaddr(ifp, mcsp->mc_addr, &nmcasts, MAXMCADDR);
2992 if (nmcasts >= MAXMCADDR) {
2993 if_setflagbits(ifp, IFF_ALLMULTI, 0);
2994 nmcasts = 0;
2995 }
2996 if_maddr_runlock(ifp);
2997 }
2998 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2999 return (nmcasts);
3000 }
3001
3002 /*
3003 * Program the multicast filter.
3004 *
3005 * We have an artificial restriction that the multicast setup command
3006 * must be the first command in the chain, so we take steps to ensure
3007 * this. By requiring this, it allows us to keep up the performance of
3008 * the pre-initialized command ring (esp. link pointers) by not actually
3009 * inserting the mcsetup command in the ring - i.e. its link pointer
3010 * points to the TxCB ring, but the mcsetup descriptor itself is not part
3011 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
3012 * lead into the regular TxCB ring when it completes.
3013 */
3014 static void
fxp_mc_setup(struct fxp_softc * sc)3015 fxp_mc_setup(struct fxp_softc *sc)
3016 {
3017 struct fxp_cb_mcs *mcsp;
3018 int count;
3019
3020 FXP_LOCK_ASSERT(sc, MA_OWNED);
3021
3022 mcsp = sc->mcsp;
3023 mcsp->cb_status = 0;
3024 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3025 mcsp->link_addr = 0xffffffff;
3026 fxp_mc_addrs(sc);
3027
3028 /*
3029 * Wait until command unit is idle. This should never be the
3030 * case when nothing is queued, but make sure anyway.
3031 */
3032 count = 100;
3033 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3034 FXP_SCB_CUS_IDLE && --count)
3035 DELAY(10);
3036 if (count == 0) {
3037 device_printf(sc->dev, "command queue timeout\n");
3038 return;
3039 }
3040
3041 /*
3042 * Start the multicast setup command.
3043 */
3044 fxp_scb_wait(sc);
3045 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3047 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3048 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3049 /* ...and wait for it to complete. */
3050 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3051 }
3052
3053 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3054 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3055 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3056 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3057 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3058 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3059 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3060
3061 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3062
3063 static const struct ucode {
3064 uint32_t revision;
3065 uint32_t *ucode;
3066 int length;
3067 u_short int_delay_offset;
3068 u_short bundle_max_offset;
3069 } ucode_table[] = {
3070 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3071 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3072 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3073 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3074 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3075 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3076 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3077 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3078 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3079 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3080 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3081 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3082 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3083 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3084 { 0, NULL, 0, 0, 0 }
3085 };
3086
3087 static void
fxp_load_ucode(struct fxp_softc * sc)3088 fxp_load_ucode(struct fxp_softc *sc)
3089 {
3090 const struct ucode *uc;
3091 struct fxp_cb_ucode *cbp;
3092 int i;
3093
3094 if (sc->flags & FXP_FLAG_NO_UCODE)
3095 return;
3096
3097 for (uc = ucode_table; uc->ucode != NULL; uc++)
3098 if (sc->revision == uc->revision)
3099 break;
3100 if (uc->ucode == NULL)
3101 return;
3102 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3103 cbp->cb_status = 0;
3104 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3105 cbp->link_addr = 0xffffffff; /* (no) next command */
3106 for (i = 0; i < uc->length; i++)
3107 cbp->ucode[i] = htole32(uc->ucode[i]);
3108 if (uc->int_delay_offset)
3109 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3110 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3111 if (uc->bundle_max_offset)
3112 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3113 htole16(sc->tunable_bundle_max);
3114 /*
3115 * Download the ucode to the chip.
3116 */
3117 fxp_scb_wait(sc);
3118 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3119 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3120 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3121 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3122 /* ...and wait for it to complete. */
3123 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3124 device_printf(sc->dev,
3125 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3126 sc->tunable_int_delay,
3127 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3128 sc->flags |= FXP_FLAG_UCODE;
3129 bzero(cbp, FXP_TXCB_SZ);
3130 }
3131
3132 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3133 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3134
3135 static void
fxp_sysctl_node(struct fxp_softc * sc)3136 fxp_sysctl_node(struct fxp_softc *sc)
3137 {
3138 struct sysctl_ctx_list *ctx;
3139 struct sysctl_oid_list *child, *parent;
3140 struct sysctl_oid *tree;
3141 struct fxp_hwstats *hsp;
3142
3143 ctx = device_get_sysctl_ctx(sc->dev);
3144 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3145
3146 SYSCTL_ADD_PROC(ctx, child,
3147 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
3148 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3149 "FXP driver receive interrupt microcode bundling delay");
3150 SYSCTL_ADD_PROC(ctx, child,
3151 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
3152 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3153 "FXP driver receive interrupt microcode bundle size limit");
3154 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3155 "FXP RNR events");
3156
3157 /*
3158 * Pull in device tunables.
3159 */
3160 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3161 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3162 (void) resource_int_value(device_get_name(sc->dev),
3163 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3164 (void) resource_int_value(device_get_name(sc->dev),
3165 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3166 sc->rnr = 0;
3167
3168 hsp = &sc->fxp_hwstats;
3169 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3170 NULL, "FXP statistics");
3171 parent = SYSCTL_CHILDREN(tree);
3172
3173 /* Rx MAC statistics. */
3174 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3175 NULL, "Rx MAC statistics");
3176 child = SYSCTL_CHILDREN(tree);
3177 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3178 &hsp->rx_good, "Good frames");
3179 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3180 &hsp->rx_crc_errors, "CRC errors");
3181 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3182 &hsp->rx_alignment_errors, "Alignment errors");
3183 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3184 &hsp->rx_rnr_errors, "RNR errors");
3185 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3186 &hsp->rx_overrun_errors, "Overrun errors");
3187 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3188 &hsp->rx_cdt_errors, "Collision detect errors");
3189 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3190 &hsp->rx_shortframes, "Short frame errors");
3191 if (sc->revision >= FXP_REV_82558_A4) {
3192 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3193 &hsp->rx_pause, "Pause frames");
3194 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3195 &hsp->rx_controls, "Unsupported control frames");
3196 }
3197 if (sc->revision >= FXP_REV_82559_A0)
3198 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3199 &hsp->rx_tco, "TCO frames");
3200
3201 /* Tx MAC statistics. */
3202 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3203 NULL, "Tx MAC statistics");
3204 child = SYSCTL_CHILDREN(tree);
3205 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3206 &hsp->tx_good, "Good frames");
3207 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3208 &hsp->tx_maxcols, "Maximum collisions errors");
3209 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3210 &hsp->tx_latecols, "Late collisions errors");
3211 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3212 &hsp->tx_underruns, "Underrun errors");
3213 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3214 &hsp->tx_lostcrs, "Lost carrier sense");
3215 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3216 &hsp->tx_deffered, "Deferred");
3217 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3218 &hsp->tx_single_collisions, "Single collisions");
3219 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3220 &hsp->tx_multiple_collisions, "Multiple collisions");
3221 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3222 &hsp->tx_total_collisions, "Total collisions");
3223 if (sc->revision >= FXP_REV_82558_A4)
3224 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3225 &hsp->tx_pause, "Pause frames");
3226 if (sc->revision >= FXP_REV_82559_A0)
3227 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3228 &hsp->tx_tco, "TCO frames");
3229 }
3230
3231 #undef FXP_SYSCTL_STAT_ADD
3232
3233 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3234 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3235 {
3236 int error, value;
3237
3238 value = *(int *)arg1;
3239 error = sysctl_handle_int(oidp, &value, 0, req);
3240 if (error || !req->newptr)
3241 return (error);
3242 if (value < low || value > high)
3243 return (EINVAL);
3244 *(int *)arg1 = value;
3245 return (0);
3246 }
3247
3248 /*
3249 * Interrupt delay is expressed in microseconds, a multiplier is used
3250 * to convert this to the appropriate clock ticks before using.
3251 */
3252 static int
sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)3253 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3254 {
3255
3256 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3257 }
3258
3259 static int
sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)3260 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3261 {
3262
3263 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
3264 }
3265