1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann ([email protected]). 5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6 at Cygnus Support. 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2, or (at your option) 13 any later version. 14 15 GCC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING. If not, write to 22 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 23 Boston, MA 02110-1301, USA. */ 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 /* Define the specific costs for a given cpu */ 29 30 struct processor_costs { 31 /* Integer load */ 32 const int int_load; 33 34 /* Integer signed load */ 35 const int int_sload; 36 37 /* Integer zeroed load */ 38 const int int_zload; 39 40 /* Float load */ 41 const int float_load; 42 43 /* fmov, fneg, fabs */ 44 const int float_move; 45 46 /* fadd, fsub */ 47 const int float_plusminus; 48 49 /* fcmp */ 50 const int float_cmp; 51 52 /* fmov, fmovr */ 53 const int float_cmove; 54 55 /* fmul */ 56 const int float_mul; 57 58 /* fdivs */ 59 const int float_div_sf; 60 61 /* fdivd */ 62 const int float_div_df; 63 64 /* fsqrts */ 65 const int float_sqrt_sf; 66 67 /* fsqrtd */ 68 const int float_sqrt_df; 69 70 /* umul/smul */ 71 const int int_mul; 72 73 /* mulX */ 74 const int int_mulX; 75 76 /* integer multiply cost for each bit set past the most 77 significant 3, so the formula for multiply cost becomes: 78 79 if (rs1 < 0) 80 highest_bit = highest_clear_bit(rs1); 81 else 82 highest_bit = highest_set_bit(rs1); 83 if (highest_bit < 3) 84 highest_bit = 3; 85 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor); 86 87 A value of zero indicates that the multiply costs is fixed, 88 and not variable. */ 89 const int int_mul_bit_factor; 90 91 /* udiv/sdiv */ 92 const int int_div; 93 94 /* divX */ 95 const int int_divX; 96 97 /* movcc, movr */ 98 const int int_cmove; 99 100 /* penalty for shifts, due to scheduling rules etc. */ 101 const int shift_penalty; 102 }; 103 104 extern const struct processor_costs *sparc_costs; 105 106 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of 107 Solaris only; otherwise just define __sparc__. Sadly the headers 108 are such a mess there is no Solaris-specific header. */ 109 #define TARGET_CPU_CPP_BUILTINS() \ 110 do \ 111 { \ 112 builtin_define_std ("sparc"); \ 113 if (TARGET_64BIT) \ 114 { \ 115 builtin_assert ("cpu=sparc64"); \ 116 builtin_assert ("machine=sparc64"); \ 117 } \ 118 else \ 119 { \ 120 builtin_assert ("cpu=sparc"); \ 121 builtin_assert ("machine=sparc"); \ 122 } \ 123 } \ 124 while (0) 125 126 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 127 /* #define SPARC_BI_ARCH */ 128 129 /* Macro used later in this file to determine default architecture. */ 130 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 131 132 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 133 architectures to compile for. We allow targets to choose compile time or 134 runtime selection. */ 135 #ifdef IN_LIBGCC2 136 #if defined(__sparcv9) || defined(__arch64__) 137 #define TARGET_ARCH32 0 138 #else 139 #define TARGET_ARCH32 1 140 #endif /* sparc64 */ 141 #else 142 #ifdef SPARC_BI_ARCH 143 #define TARGET_ARCH32 (! TARGET_64BIT) 144 #else 145 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 146 #endif /* SPARC_BI_ARCH */ 147 #endif /* IN_LIBGCC2 */ 148 #define TARGET_ARCH64 (! TARGET_ARCH32) 149 150 /* Code model selection in 64-bit environment. 151 152 The machine mode used for addresses is 32-bit wide: 153 154 TARGET_CM_32: 32-bit address space. 155 It is the code model used when generating 32-bit code. 156 157 The machine mode used for addresses is 64-bit wide: 158 159 TARGET_CM_MEDLOW: 32-bit address space. 160 The executable must be in the low 32 bits of memory. 161 This avoids generating %uhi and %ulo terms. Programs 162 can be statically or dynamically linked. 163 164 TARGET_CM_MEDMID: 44-bit address space. 165 The executable must be in the low 44 bits of memory, 166 and the %[hml]44 terms are used. The text and data 167 segments have a maximum size of 2GB (31-bit span). 168 The maximum offset from any instruction to the label 169 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 170 171 TARGET_CM_MEDANY: 64-bit address space. 172 The text and data segments have a maximum size of 2GB 173 (31-bit span) and may be located anywhere in memory. 174 The maximum offset from any instruction to the label 175 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 176 177 TARGET_CM_EMBMEDANY: 64-bit address space. 178 The text and data segments have a maximum size of 2GB 179 (31-bit span) and may be located anywhere in memory. 180 The global register %g4 contains the start address of 181 the data segment. Programs are statically linked and 182 PIC is not supported. 183 184 Different code models are not supported in 32-bit environment. */ 185 186 enum cmodel { 187 CM_32, 188 CM_MEDLOW, 189 CM_MEDMID, 190 CM_MEDANY, 191 CM_EMBMEDANY 192 }; 193 194 /* One of CM_FOO. */ 195 extern enum cmodel sparc_cmodel; 196 197 /* V9 code model selection. */ 198 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 199 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 200 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 201 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 202 203 #define SPARC_DEFAULT_CMODEL CM_32 204 205 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) 206 which requires the following macro to be true if enabled. Prior to V9, 207 there are no instructions to even talk about memory synchronization. 208 Note that the UltraSPARC III processors don't implement RMO, unlike the 209 UltraSPARC II processors. Niagara does not implement RMO either. 210 211 Default to false; for example, Solaris never enables RMO, only ever uses 212 total memory ordering (TMO). */ 213 #define SPARC_RELAXED_ORDERING false 214 215 /* Do not use the .note.GNU-stack convention by default. */ 216 #define NEED_INDICATE_EXEC_STACK 0 217 218 /* This is call-clobbered in the normal ABI, but is reserved in the 219 home grown (aka upward compatible) embedded ABI. */ 220 #define EMBMEDANY_BASE_REG "%g4" 221 222 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 223 and specified by the user via --with-cpu=foo. 224 This specifies the cpu implementation, not the architecture size. */ 225 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 226 capable cpu's. */ 227 #define TARGET_CPU_sparc 0 228 #define TARGET_CPU_v7 0 /* alias for previous */ 229 #define TARGET_CPU_sparclet 1 230 #define TARGET_CPU_sparclite 2 231 #define TARGET_CPU_v8 3 /* generic v8 implementation */ 232 #define TARGET_CPU_supersparc 4 233 #define TARGET_CPU_hypersparc 5 234 #define TARGET_CPU_sparc86x 6 235 #define TARGET_CPU_sparclite86x 6 236 #define TARGET_CPU_v9 7 /* generic v9 implementation */ 237 #define TARGET_CPU_sparcv9 7 /* alias */ 238 #define TARGET_CPU_sparc64 7 /* alias */ 239 #define TARGET_CPU_ultrasparc 8 240 #define TARGET_CPU_ultrasparc3 9 241 #define TARGET_CPU_niagara 10 242 243 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 244 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 245 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 246 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara 247 248 #define CPP_CPU32_DEFAULT_SPEC "" 249 #define ASM_CPU32_DEFAULT_SPEC "" 250 251 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 252 /* ??? What does Sun's CC pass? */ 253 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 254 /* ??? It's not clear how other assemblers will handle this, so by default 255 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 256 is handled in sol2.h. */ 257 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 258 #endif 259 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 260 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 261 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 262 #endif 263 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 264 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 265 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 266 #endif 267 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 268 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 269 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 270 #endif 271 272 #else 273 274 #define CPP_CPU64_DEFAULT_SPEC "" 275 #define ASM_CPU64_DEFAULT_SPEC "" 276 277 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 278 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 279 #define CPP_CPU32_DEFAULT_SPEC "" 280 #define ASM_CPU32_DEFAULT_SPEC "" 281 #endif 282 283 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 284 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 285 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 286 #endif 287 288 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 289 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 290 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 291 #endif 292 293 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 294 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 295 #define ASM_CPU32_DEFAULT_SPEC "" 296 #endif 297 298 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 299 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 300 #define ASM_CPU32_DEFAULT_SPEC "" 301 #endif 302 303 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 304 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 305 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 306 #endif 307 308 #endif 309 310 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 311 #error Unrecognized value in TARGET_CPU_DEFAULT. 312 #endif 313 314 #ifdef SPARC_BI_ARCH 315 316 #define CPP_CPU_DEFAULT_SPEC \ 317 (DEFAULT_ARCH32_P ? "\ 318 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 319 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 320 " : "\ 321 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 322 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 323 ") 324 #define ASM_CPU_DEFAULT_SPEC \ 325 (DEFAULT_ARCH32_P ? "\ 326 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 327 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 328 " : "\ 329 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 330 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 331 ") 332 333 #else /* !SPARC_BI_ARCH */ 334 335 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 336 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 337 338 #endif /* !SPARC_BI_ARCH */ 339 340 /* Define macros to distinguish architectures. */ 341 342 /* Common CPP definitions used by CPP_SPEC amongst the various targets 343 for handling -mcpu=xxx switches. */ 344 #define CPP_CPU_SPEC "\ 345 %{msoft-float:-D_SOFT_FLOAT} \ 346 %{mcypress:} \ 347 %{msparclite:-D__sparclite__} \ 348 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ 349 %{mv8:-D__sparc_v8__} \ 350 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ 351 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 352 %{mcpu=sparclite:-D__sparclite__} \ 353 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 354 %{mcpu=v8:-D__sparc_v8__} \ 355 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 356 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 357 %{mcpu=sparclite86x:-D__sparclite86x__} \ 358 %{mcpu=v9:-D__sparc_v9__} \ 359 %{mcpu=ultrasparc:-D__sparc_v9__} \ 360 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 361 %{mcpu=niagara:-D__sparc_v9__} \ 362 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ 363 " 364 #define CPP_ARCH32_SPEC "" 365 #define CPP_ARCH64_SPEC "-D__arch64__" 366 367 #define CPP_ARCH_DEFAULT_SPEC \ 368 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 369 370 #define CPP_ARCH_SPEC "\ 371 %{m32:%(cpp_arch32)} \ 372 %{m64:%(cpp_arch64)} \ 373 %{!m32:%{!m64:%(cpp_arch_default)}} \ 374 " 375 376 /* Macros to distinguish endianness. */ 377 #define CPP_ENDIAN_SPEC "\ 378 %{mlittle-endian:-D__LITTLE_ENDIAN__} \ 379 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" 380 381 /* Macros to distinguish the particular subtarget. */ 382 #define CPP_SUBTARGET_SPEC "" 383 384 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" 385 386 /* Prevent error on `-sun4' and `-target sun4' options. */ 387 /* This used to translate -dalign to -malign, but that is no good 388 because it can't turn off the usual meaning of making debugging dumps. */ 389 /* Translate old style -m<cpu> into new style -mcpu=<cpu>. 390 ??? Delete support for -m<cpu> for 2.9. */ 391 392 #define CC1_SPEC "\ 393 %{sun4:} %{target:} \ 394 %{mcypress:-mcpu=cypress} \ 395 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ 396 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ 397 " 398 399 /* Override in target specific files. */ 400 #define ASM_CPU_SPEC "\ 401 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 402 %{msparclite:-Asparclite} \ 403 %{mf930:-Asparclite} %{mf934:-Asparclite} \ 404 %{mcpu=sparclite:-Asparclite} \ 405 %{mcpu=sparclite86x:-Asparclite} \ 406 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 407 %{mv8plus:-Av8plus} \ 408 %{mcpu=v9:-Av9} \ 409 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 410 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 411 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ 412 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ 413 " 414 415 /* Word size selection, among other things. 416 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 417 418 #define ASM_ARCH32_SPEC "-32" 419 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 420 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 421 #else 422 #define ASM_ARCH64_SPEC "-64" 423 #endif 424 #define ASM_ARCH_DEFAULT_SPEC \ 425 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 426 427 #define ASM_ARCH_SPEC "\ 428 %{m32:%(asm_arch32)} \ 429 %{m64:%(asm_arch64)} \ 430 %{!m32:%{!m64:%(asm_arch_default)}} \ 431 " 432 433 #ifdef HAVE_AS_RELAX_OPTION 434 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 435 #else 436 #define ASM_RELAX_SPEC "" 437 #endif 438 439 /* Special flags to the Sun-4 assembler when using pipe for input. */ 440 441 #define ASM_SPEC "\ 442 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ 443 %(asm_cpu) %(asm_relax)" 444 445 #define AS_NEEDS_DASH_FOR_PIPED_INPUT 446 447 /* This macro defines names of additional specifications to put in the specs 448 that can be used in various specifications like CC1_SPEC. Its definition 449 is an initializer with a subgrouping for each command option. 450 451 Each subgrouping contains a string constant, that defines the 452 specification name, and a string constant that used by the GCC driver 453 program. 454 455 Do not define this macro if it does not need to do anything. */ 456 457 #define EXTRA_SPECS \ 458 { "cpp_cpu", CPP_CPU_SPEC }, \ 459 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 460 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 461 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 462 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 463 { "cpp_arch", CPP_ARCH_SPEC }, \ 464 { "cpp_endian", CPP_ENDIAN_SPEC }, \ 465 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 466 { "asm_cpu", ASM_CPU_SPEC }, \ 467 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 468 { "asm_arch32", ASM_ARCH32_SPEC }, \ 469 { "asm_arch64", ASM_ARCH64_SPEC }, \ 470 { "asm_relax", ASM_RELAX_SPEC }, \ 471 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 472 { "asm_arch", ASM_ARCH_SPEC }, \ 473 SUBTARGET_EXTRA_SPECS 474 475 #define SUBTARGET_EXTRA_SPECS 476 477 /* Because libgcc can generate references back to libc (via .umul etc.) we have 478 to list libc again after the second libgcc. */ 479 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 480 481 482 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 483 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 484 485 /* ??? This should be 32 bits for v9 but what can we do? */ 486 #define WCHAR_TYPE "short unsigned int" 487 #define WCHAR_TYPE_SIZE 16 488 489 /* Show we can debug even without a frame pointer. */ 490 #define CAN_DEBUG_WITHOUT_FP 491 492 /* Option handling. */ 493 494 #define OVERRIDE_OPTIONS sparc_override_options () 495 496 /* Mask of all CPU selection flags. */ 497 #define MASK_ISA \ 498 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 499 500 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. 501 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y 502 to get high 32 bits. False in V8+ or V9 because multiply stores 503 a 64 bit result in a register. */ 504 505 #define TARGET_HARD_MUL32 \ 506 ((TARGET_V8 || TARGET_SPARCLITE \ 507 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ 508 && ! TARGET_V8PLUS && TARGET_ARCH32) 509 510 #define TARGET_HARD_MUL \ 511 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ 512 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) 513 514 /* MASK_APP_REGS must always be the default because that's what 515 FIXED_REGISTERS is set to and -ffixed- is processed before 516 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ 517 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 518 519 /* Processor type. 520 These must match the values for the cpu attribute in sparc.md. */ 521 enum processor_type { 522 PROCESSOR_V7, 523 PROCESSOR_CYPRESS, 524 PROCESSOR_V8, 525 PROCESSOR_SUPERSPARC, 526 PROCESSOR_SPARCLITE, 527 PROCESSOR_F930, 528 PROCESSOR_F934, 529 PROCESSOR_HYPERSPARC, 530 PROCESSOR_SPARCLITE86X, 531 PROCESSOR_SPARCLET, 532 PROCESSOR_TSC701, 533 PROCESSOR_V9, 534 PROCESSOR_ULTRASPARC, 535 PROCESSOR_ULTRASPARC3, 536 PROCESSOR_NIAGARA 537 }; 538 539 /* This is set from -m{cpu,tune}=xxx. */ 540 extern enum processor_type sparc_cpu; 541 542 /* Recast the cpu class to be the cpu attribute. 543 Every file includes us, but not every file includes insn-attr.h. */ 544 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 545 546 /* Support for a compile-time default CPU, et cetera. The rules are: 547 --with-cpu is ignored if -mcpu is specified. 548 --with-tune is ignored if -mtune is specified. 549 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 550 are specified. */ 551 #define OPTION_DEFAULT_SPECS \ 552 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 553 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 554 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" } 555 556 /* sparc_select[0] is reserved for the default cpu. */ 557 struct sparc_cpu_select 558 { 559 const char *string; 560 const char *const name; 561 const int set_tune_p; 562 const int set_arch_p; 563 }; 564 565 extern struct sparc_cpu_select sparc_select[]; 566 567 /* target machine storage layout */ 568 569 /* Define this if most significant bit is lowest numbered 570 in instructions that operate on numbered bit-fields. */ 571 #define BITS_BIG_ENDIAN 1 572 573 /* Define this if most significant byte of a word is the lowest numbered. */ 574 #define BYTES_BIG_ENDIAN 1 575 576 /* Define this if most significant word of a multiword number is the lowest 577 numbered. */ 578 #define WORDS_BIG_ENDIAN 1 579 580 /* Define this to set the endianness to use in libgcc2.c, which can 581 not depend on target_flags. */ 582 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) 583 #define LIBGCC2_WORDS_BIG_ENDIAN 0 584 #else 585 #define LIBGCC2_WORDS_BIG_ENDIAN 1 586 #endif 587 588 #define MAX_BITS_PER_WORD 64 589 590 /* Width of a word, in units (bytes). */ 591 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 592 #ifdef IN_LIBGCC2 593 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 594 #else 595 #define MIN_UNITS_PER_WORD 4 596 #endif 597 598 #define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : UNITS_PER_WORD) 599 600 /* Now define the sizes of the C data types. */ 601 602 #define SHORT_TYPE_SIZE 16 603 #define INT_TYPE_SIZE 32 604 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 605 #define LONG_LONG_TYPE_SIZE 64 606 #define FLOAT_TYPE_SIZE 32 607 #define DOUBLE_TYPE_SIZE 64 608 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 609 SPARC ABI says that it is 128-bit wide. */ 610 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 611 612 /* Width in bits of a pointer. 613 See also the macro `Pmode' defined below. */ 614 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 615 616 /* If we have to extend pointers (only when TARGET_ARCH64 and not 617 TARGET_PTR64), we want to do it unsigned. This macro does nothing 618 if ptr_mode and Pmode are the same. */ 619 #define POINTERS_EXTEND_UNSIGNED 1 620 621 /* For TARGET_ARCH64 we need this, as we don't have instructions 622 for arithmetic operations which do zero/sign extension at the same time, 623 so without this we end up with a srl/sra after every assignment to an 624 user variable, which means very very bad code. */ 625 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \ 626 if (TARGET_ARCH64 \ 627 && GET_MODE_CLASS (MODE) == MODE_INT \ 628 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 629 (MODE) = word_mode; 630 631 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 632 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 633 634 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 635 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 636 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 637 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 638 /* Temporary hack until the FIXME above is fixed. */ 639 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 640 641 /* ALIGN FRAMES on double word boundaries */ 642 643 #define SPARC_STACK_ALIGN(LOC) \ 644 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 645 646 /* Allocation boundary (in *bits*) for the code of a function. */ 647 #define FUNCTION_BOUNDARY 32 648 649 /* Alignment of field after `int : 0' in a structure. */ 650 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 651 652 /* Every structure's size must be a multiple of this. */ 653 #define STRUCTURE_SIZE_BOUNDARY 8 654 655 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 656 #define PCC_BITFIELD_TYPE_MATTERS 1 657 658 /* No data type wants to be aligned rounder than this. */ 659 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 660 661 /* The best alignment to use in cases where we have a choice. */ 662 #define FASTEST_ALIGNMENT 64 663 664 /* Define this macro as an expression for the alignment of a structure 665 (given by STRUCT as a tree node) if the alignment computed in the 666 usual way is COMPUTED and the alignment explicitly specified was 667 SPECIFIED. 668 669 The default is to use SPECIFIED if it is larger; otherwise, use 670 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 671 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 672 (TARGET_FASTER_STRUCTS ? \ 673 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 674 || TREE_CODE (STRUCT) == UNION_TYPE \ 675 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 676 && TYPE_FIELDS (STRUCT) != 0 \ 677 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 678 : MAX ((COMPUTED), (SPECIFIED))) \ 679 : MAX ((COMPUTED), (SPECIFIED))) 680 681 /* Make strings word-aligned so strcpy from constants will be faster. */ 682 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 683 ((TREE_CODE (EXP) == STRING_CST \ 684 && (ALIGN) < FASTEST_ALIGNMENT) \ 685 ? FASTEST_ALIGNMENT : (ALIGN)) 686 687 /* Make arrays of chars word-aligned for the same reasons. */ 688 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 689 (TREE_CODE (TYPE) == ARRAY_TYPE \ 690 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 691 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 692 693 /* Set this nonzero if move instructions will actually fail to work 694 when given unaligned data. */ 695 #define STRICT_ALIGNMENT 1 696 697 /* Things that must be doubleword aligned cannot go in the text section, 698 because the linker fails to align the text section enough! 699 Put them in the data section. This macro is only used in this file. */ 700 #define MAX_TEXT_ALIGN 32 701 702 /* Standard register usage. */ 703 704 /* Number of actual hardware registers. 705 The hardware registers are assigned numbers for the compiler 706 from 0 to just below FIRST_PSEUDO_REGISTER. 707 All registers that the compiler knows about must be given numbers, 708 even those that are not normally considered general registers. 709 710 SPARC has 32 integer registers and 32 floating point registers. 711 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not 712 accessible. We still account for them to simplify register computations 713 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 714 32+32+32+4 == 100. 715 Register 100 is used as the integer condition code register. 716 Register 101 is used as the soft frame pointer register. */ 717 718 #define FIRST_PSEUDO_REGISTER 102 719 720 #define SPARC_FIRST_FP_REG 32 721 /* Additional V9 fp regs. */ 722 #define SPARC_FIRST_V9_FP_REG 64 723 #define SPARC_LAST_V9_FP_REG 95 724 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 725 #define SPARC_FIRST_V9_FCC_REG 96 726 #define SPARC_LAST_V9_FCC_REG 99 727 /* V8 fcc reg. */ 728 #define SPARC_FCC_REG 96 729 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 730 #define SPARC_ICC_REG 100 731 732 /* Nonzero if REGNO is an fp reg. */ 733 #define SPARC_FP_REG_P(REGNO) \ 734 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 735 736 /* Argument passing regs. */ 737 #define SPARC_OUTGOING_INT_ARG_FIRST 8 738 #define SPARC_INCOMING_INT_ARG_FIRST 24 739 #define SPARC_FP_ARG_FIRST 32 740 741 /* 1 for registers that have pervasive standard uses 742 and are not available for the register allocator. 743 744 On non-v9 systems: 745 g1 is free to use as temporary. 746 g2-g4 are reserved for applications. Gcc normally uses them as 747 temporaries, but this can be disabled via the -mno-app-regs option. 748 g5 through g7 are reserved for the operating system. 749 750 On v9 systems: 751 g1,g5 are free to use as temporaries, and are free to use between calls 752 if the call is to an external function via the PLT. 753 g4 is free to use as a temporary in the non-embedded case. 754 g4 is reserved in the embedded case. 755 g2-g3 are reserved for applications. Gcc normally uses them as 756 temporaries, but this can be disabled via the -mno-app-regs option. 757 g6-g7 are reserved for the operating system (or application in 758 embedded case). 759 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 760 currently be a fixed register until this pattern is rewritten. 761 Register 1 is also used when restoring call-preserved registers in large 762 stack frames. 763 764 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 765 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 766 */ 767 768 #define FIXED_REGISTERS \ 769 {1, 0, 2, 2, 2, 2, 1, 1, \ 770 0, 0, 0, 0, 0, 0, 1, 0, \ 771 0, 0, 0, 0, 0, 0, 0, 0, \ 772 0, 0, 0, 0, 0, 0, 1, 1, \ 773 \ 774 0, 0, 0, 0, 0, 0, 0, 0, \ 775 0, 0, 0, 0, 0, 0, 0, 0, \ 776 0, 0, 0, 0, 0, 0, 0, 0, \ 777 0, 0, 0, 0, 0, 0, 0, 0, \ 778 \ 779 0, 0, 0, 0, 0, 0, 0, 0, \ 780 0, 0, 0, 0, 0, 0, 0, 0, \ 781 0, 0, 0, 0, 0, 0, 0, 0, \ 782 0, 0, 0, 0, 0, 0, 0, 0, \ 783 \ 784 0, 0, 0, 0, 0, 1} 785 786 /* 1 for registers not available across function calls. 787 These must include the FIXED_REGISTERS and also any 788 registers that can be used without being saved. 789 The latter must include the registers where values are returned 790 and the register where structure-value addresses are passed. 791 Aside from that, you can include as many other registers as you like. */ 792 793 #define CALL_USED_REGISTERS \ 794 {1, 1, 1, 1, 1, 1, 1, 1, \ 795 1, 1, 1, 1, 1, 1, 1, 1, \ 796 0, 0, 0, 0, 0, 0, 0, 0, \ 797 0, 0, 0, 0, 0, 0, 1, 1, \ 798 \ 799 1, 1, 1, 1, 1, 1, 1, 1, \ 800 1, 1, 1, 1, 1, 1, 1, 1, \ 801 1, 1, 1, 1, 1, 1, 1, 1, \ 802 1, 1, 1, 1, 1, 1, 1, 1, \ 803 \ 804 1, 1, 1, 1, 1, 1, 1, 1, \ 805 1, 1, 1, 1, 1, 1, 1, 1, \ 806 1, 1, 1, 1, 1, 1, 1, 1, \ 807 1, 1, 1, 1, 1, 1, 1, 1, \ 808 \ 809 1, 1, 1, 1, 1, 1} 810 811 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that 812 they won't be allocated. */ 813 814 #define CONDITIONAL_REGISTER_USAGE \ 815 do \ 816 { \ 817 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 818 { \ 819 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 820 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 821 } \ 822 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ 823 /* then honor it. */ \ 824 if (TARGET_ARCH32 && fixed_regs[5]) \ 825 fixed_regs[5] = 1; \ 826 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ 827 fixed_regs[5] = 0; \ 828 if (! TARGET_V9) \ 829 { \ 830 int regno; \ 831 for (regno = SPARC_FIRST_V9_FP_REG; \ 832 regno <= SPARC_LAST_V9_FP_REG; \ 833 regno++) \ 834 fixed_regs[regno] = 1; \ 835 /* %fcc0 is used by v8 and v9. */ \ 836 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ 837 regno <= SPARC_LAST_V9_FCC_REG; \ 838 regno++) \ 839 fixed_regs[regno] = 1; \ 840 } \ 841 if (! TARGET_FPU) \ 842 { \ 843 int regno; \ 844 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ 845 fixed_regs[regno] = 1; \ 846 } \ 847 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ 848 /* then honor it. Likewise with g3 and g4. */ \ 849 if (fixed_regs[2] == 2) \ 850 fixed_regs[2] = ! TARGET_APP_REGS; \ 851 if (fixed_regs[3] == 2) \ 852 fixed_regs[3] = ! TARGET_APP_REGS; \ 853 if (TARGET_ARCH32 && fixed_regs[4] == 2) \ 854 fixed_regs[4] = ! TARGET_APP_REGS; \ 855 else if (TARGET_CM_EMBMEDANY) \ 856 fixed_regs[4] = 1; \ 857 else if (fixed_regs[4] == 2) \ 858 fixed_regs[4] = 0; \ 859 } \ 860 while (0) 861 862 /* Return number of consecutive hard regs needed starting at reg REGNO 863 to hold something of mode MODE. 864 This is ordinarily the length in words of a value of mode MODE 865 but can be less for certain modes in special long registers. 866 867 On SPARC, ordinary registers hold 32 bits worth; 868 this means both integer and floating point registers. 869 On v9, integer regs hold 64 bits worth; floating point regs hold 870 32 bits worth (this includes the new fp regs as even the odd ones are 871 included in the hard register count). */ 872 873 #define HARD_REGNO_NREGS(REGNO, MODE) \ 874 (TARGET_ARCH64 \ 875 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ 876 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 877 : (GET_MODE_SIZE (MODE) + 3) / 4) \ 878 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 879 880 /* Due to the ARCH64 discrepancy above we must override this next 881 macro too. */ 882 #define REGMODE_NATURAL_SIZE(MODE) \ 883 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) 884 885 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 886 See sparc.c for how we initialize this. */ 887 extern const int *hard_regno_mode_classes; 888 extern int sparc_mode_class[]; 889 890 /* ??? Because of the funny way we pass parameters we should allow certain 891 ??? types of float/complex values to be in integer registers during 892 ??? RTL generation. This only matters on arch32. */ 893 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 894 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 895 896 /* Value is 1 if it is OK to rename a hard register FROM to another hard 897 register TO. We cannot rename %g1 as it may be used before the save 898 register window instruction in the prologue. */ 899 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 900 901 /* Value is 1 if it is a good idea to tie two pseudo registers 902 when one has mode MODE1 and one has mode MODE2. 903 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 904 for any hard reg, then this must be 0 for correct output. 905 906 For V9: SFmode can't be combined with other float modes, because they can't 907 be allocated to the %d registers. Also, DFmode won't fit in odd %f 908 registers, but SFmode will. */ 909 #define MODES_TIEABLE_P(MODE1, MODE2) \ 910 ((MODE1) == (MODE2) \ 911 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 912 && (! TARGET_V9 \ 913 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ 914 || (MODE1 != SFmode && MODE2 != SFmode))))) 915 916 /* Specify the registers used for certain standard purposes. 917 The values of these macros are register numbers. */ 918 919 /* Register to use for pushing function arguments. */ 920 #define STACK_POINTER_REGNUM 14 921 922 /* The stack bias (amount by which the hardware register is offset by). */ 923 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 924 925 /* Actual top-of-stack address is 92/176 greater than the contents of the 926 stack pointer register for !v9/v9. That is: 927 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 928 address, and 6*4 bytes for the 6 register parameters. 929 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 930 parameter regs. */ 931 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 932 933 /* Base register for access to local variables of the function. */ 934 #define HARD_FRAME_POINTER_REGNUM 30 935 936 /* The soft frame pointer does not have the stack bias applied. */ 937 #define FRAME_POINTER_REGNUM 101 938 939 /* Given the stack bias, the stack pointer isn't actually aligned. */ 940 #define INIT_EXPANDERS \ 941 do { \ 942 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \ 943 { \ 944 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ 945 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ 946 } \ 947 } while (0) 948 949 /* Value should be nonzero if functions must have frame pointers. 950 Zero means the frame pointer need not be set up (and parms 951 may be accessed via the stack pointer) in functions that seem suitable. 952 Used in flow.c, global.c, ra.c and reload1.c. */ 953 #define FRAME_POINTER_REQUIRED \ 954 (! (leaf_function_p () && only_leaf_regs_used ())) 955 956 /* Base register for access to arguments of the function. */ 957 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 958 959 /* Register in which static-chain is passed to a function. This must 960 not be a register used by the prologue. */ 961 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 962 963 /* Register which holds offset table for position-independent 964 data references. */ 965 966 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM) 967 968 /* Pick a default value we can notice from override_options: 969 !v9: Default is on. 970 v9: Default is off. */ 971 972 #define DEFAULT_PCC_STRUCT_RETURN -1 973 974 /* Functions which return large structures get the address 975 to place the wanted value at offset 64 from the frame. 976 Must reserve 64 bytes for the in and local registers. 977 v9: Functions which return large structures get the address to place the 978 wanted value from an invisible first argument. */ 979 #define STRUCT_VALUE_OFFSET 64 980 981 /* Define the classes of registers for register constraints in the 982 machine description. Also define ranges of constants. 983 984 One of the classes must always be named ALL_REGS and include all hard regs. 985 If there is more than one class, another class must be named NO_REGS 986 and contain no registers. 987 988 The name GENERAL_REGS must be the name of a class (or an alias for 989 another name such as ALL_REGS). This is the class of registers 990 that is allowed by "g" or "r" in a register constraint. 991 Also, registers outside this class are allocated only when 992 instructions express preferences for them. 993 994 The classes must be numbered in nondecreasing order; that is, 995 a larger-numbered class must never be contained completely 996 in a smaller-numbered class. 997 998 For any two classes, it is very desirable that there be another 999 class that represents their union. */ 1000 1001 /* The SPARC has various kinds of registers: general, floating point, 1002 and condition codes [well, it has others as well, but none that we 1003 care directly about]. 1004 1005 For v9 we must distinguish between the upper and lower floating point 1006 registers because the upper ones can't hold SFmode values. 1007 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 1008 satisfying a group need for a class will also satisfy a single need for 1009 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 1010 regs. 1011 1012 It is important that one class contains all the general and all the standard 1013 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 1014 because reg_class_record() will bias the selection in favor of fp regs, 1015 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 1016 because FP_REGS > GENERAL_REGS. 1017 1018 It is also important that one class contain all the general and all 1019 the fp regs. Otherwise when spilling a DFmode reg, it may be from 1020 EXTRA_FP_REGS but find_reloads() may use class 1021 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 1022 because the compiler thinks it doesn't have a spill reg when in 1023 fact it does. 1024 1025 v9 also has 4 floating point condition code registers. Since we don't 1026 have a class that is the union of FPCC_REGS with either of the others, 1027 it is important that it appear first. Otherwise the compiler will die 1028 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 1029 constraints. 1030 1031 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine 1032 may try to use it to hold an SImode value. See register_operand. 1033 ??? Should %fcc[0123] be handled similarly? 1034 */ 1035 1036 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 1037 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 1038 ALL_REGS, LIM_REG_CLASSES }; 1039 1040 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1041 1042 /* Give names of register classes as strings for dump file. */ 1043 1044 #define REG_CLASS_NAMES \ 1045 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 1046 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 1047 "ALL_REGS" } 1048 1049 /* Define which registers fit in which classes. 1050 This is an initializer for a vector of HARD_REG_SET 1051 of length N_REG_CLASSES. */ 1052 1053 #define REG_CLASS_CONTENTS \ 1054 {{0, 0, 0, 0}, /* NO_REGS */ \ 1055 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 1056 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 1057 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 1058 {0, -1, 0, 0}, /* FP_REGS */ \ 1059 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 1060 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 1061 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 1062 {-1, -1, -1, 0x3f}} /* ALL_REGS */ 1063 1064 /* Defines invalid mode changes. Borrowed from pa64-regs.h. 1065 1066 SImode loads to floating-point registers are not zero-extended. 1067 The definition for LOAD_EXTEND_OP specifies that integer loads 1068 narrower than BITS_PER_WORD will be zero-extended. As a result, 1069 we inhibit changes from SImode unless they are to a mode that is 1070 identical in size. */ 1071 1072 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1073 (TARGET_ARCH64 \ 1074 && (FROM) == SImode \ 1075 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1076 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 1077 1078 /* The same information, inverted: 1079 Return the class number of the smallest class containing 1080 reg number REGNO. This could be a conditional expression 1081 or could index an array. */ 1082 1083 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 1084 1085 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 1086 1087 /* This is the order in which to allocate registers normally. 1088 1089 We put %f0-%f7 last among the float registers, so as to make it more 1090 likely that a pseudo-register which dies in the float return register 1091 area will get allocated to the float return register, thus saving a move 1092 instruction at the end of the function. 1093 1094 Similarly for integer return value registers. 1095 1096 We know in this case that we will not end up with a leaf function. 1097 1098 The register allocator is given the global and out registers first 1099 because these registers are call clobbered and thus less useful to 1100 global register allocation. 1101 1102 Next we list the local and in registers. They are not call clobbered 1103 and thus very useful for global register allocation. We list the input 1104 registers before the locals so that it is more likely the incoming 1105 arguments received in those registers can just stay there and not be 1106 reloaded. */ 1107 1108 #define REG_ALLOC_ORDER \ 1109 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1110 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1111 15, /* %o7 */ \ 1112 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1113 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 1114 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1115 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1116 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1117 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1118 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1119 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1120 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1121 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1122 96, 97, 98, 99, /* %fcc0-3 */ \ 1123 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ 1124 1125 /* This is the order in which to allocate registers for 1126 leaf functions. If all registers can fit in the global and 1127 output registers, then we have the possibility of having a leaf 1128 function. 1129 1130 The macro actually mentioned the input registers first, 1131 because they get renumbered into the output registers once 1132 we know really do have a leaf function. 1133 1134 To be more precise, this register allocation order is used 1135 when %o7 is found to not be clobbered right before register 1136 allocation. Normally, the reason %o7 would be clobbered is 1137 due to a call which could not be transformed into a sibling 1138 call. 1139 1140 As a consequence, it is possible to use the leaf register 1141 allocation order and not end up with a leaf function. We will 1142 not get suboptimal register allocation in that case because by 1143 definition of being potentially leaf, there were no function 1144 calls. Therefore, allocation order within the local register 1145 window is not critical like it is when we do have function calls. */ 1146 1147 #define REG_LEAF_ALLOC_ORDER \ 1148 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1149 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 1150 15, /* %o7 */ \ 1151 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1152 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1153 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1154 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1155 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1156 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1157 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1158 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1159 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1160 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1161 96, 97, 98, 99, /* %fcc0-3 */ \ 1162 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ 1163 1164 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 1165 1166 extern char sparc_leaf_regs[]; 1167 #define LEAF_REGISTERS sparc_leaf_regs 1168 1169 extern char leaf_reg_remap[]; 1170 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1171 1172 /* The class value for index registers, and the one for base regs. */ 1173 #define INDEX_REG_CLASS GENERAL_REGS 1174 #define BASE_REG_CLASS GENERAL_REGS 1175 1176 /* Local macro to handle the two v9 classes of FP regs. */ 1177 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1178 1179 /* Get reg_class from a letter such as appears in the machine description. 1180 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the 1181 .md file for v8 and v9. 1182 'd' and 'b' are used for single and double precision VIS operations, 1183 if TARGET_VIS. 1184 'h' is used for V8+ 64 bit global and out registers. */ 1185 1186 #define REG_CLASS_FROM_LETTER(C) \ 1187 (TARGET_V9 \ 1188 ? ((C) == 'f' ? FP_REGS \ 1189 : (C) == 'e' ? EXTRA_FP_REGS \ 1190 : (C) == 'c' ? FPCC_REGS \ 1191 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\ 1192 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\ 1193 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\ 1194 : NO_REGS) \ 1195 : ((C) == 'f' ? FP_REGS \ 1196 : (C) == 'e' ? FP_REGS \ 1197 : (C) == 'c' ? FPCC_REGS \ 1198 : NO_REGS)) 1199 1200 /* The letters I, J, K, L, M, N, O, P in a register constraint string 1201 can be used to stand for particular ranges of CONST_INTs. 1202 This macro defines what the ranges are. 1203 C is the letter, and VALUE is a constant value. 1204 Return 1 if VALUE is in the range specified by C. 1205 1206 `I' is used for the range of constants an insn can actually contain. 1207 `J' is used for the range which is just zero (since that is R0). 1208 `K' is used for constants which can be loaded with a single sethi insn. 1209 `L' is used for the range of constants supported by the movcc insns. 1210 `M' is used for the range of constants supported by the movrcc insns. 1211 `N' is like K, but for constants wider than 32 bits. 1212 `O' is used for the range which is just 4096. 1213 `P' is free. */ 1214 1215 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */ 1216 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1217 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1218 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1219 1220 /* 10- and 11-bit immediates are only used for a few specific insns. 1221 SMALL_INT is used throughout the port so we continue to use it. */ 1222 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1223 1224 /* Predicate for constants that can be loaded with a sethi instruction. 1225 This is the general, 64-bit aware, bitwise version that ensures that 1226 only constants whose representation fits in the mask 1227 1228 0x00000000fffffc00 1229 1230 are accepted. It will reject, for example, negative SImode constants 1231 on 64-bit hosts, so correct handling is to mask the value beforehand 1232 according to the mode of the instruction. */ 1233 #define SPARC_SETHI_P(X) \ 1234 (((unsigned HOST_WIDE_INT) (X) \ 1235 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1236 1237 /* Version of the above predicate for SImode constants and below. */ 1238 #define SPARC_SETHI32_P(X) \ 1239 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1240 1241 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1242 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ 1243 : (C) == 'J' ? (VALUE) == 0 \ 1244 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \ 1245 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ 1246 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ 1247 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \ 1248 : (C) == 'O' ? (VALUE) == 4096 \ 1249 : 0) 1250 1251 /* Similar, but for CONST_DOUBLEs, and defining letters G and H. 1252 Here VALUE is the CONST_DOUBLE rtx itself. */ 1253 1254 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1255 ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \ 1256 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ 1257 : 0) 1258 1259 /* Given an rtx X being reloaded into a reg required to be 1260 in class CLASS, return the class of reg to actually use. 1261 In general this is just CLASS; but on some machines 1262 in some cases it is preferable to use a more restrictive class. */ 1263 /* - We can't load constants into FP registers. 1264 - We can't load FP constants into integer registers when soft-float, 1265 because there is no soft-float pattern with a r/F constraint. 1266 - We can't load FP constants into integer registers for TFmode unless 1267 it is 0.0L, because there is no movtf pattern with a r/F constraint. 1268 - Try and reload integer constants (symbolic or otherwise) back into 1269 registers directly, rather than having them dumped to memory. */ 1270 1271 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1272 (CONSTANT_P (X) \ 1273 ? ((FP_REG_CLASS_P (CLASS) \ 1274 || (CLASS) == GENERAL_OR_FP_REGS \ 1275 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \ 1276 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1277 && ! TARGET_FPU) \ 1278 || (GET_MODE (X) == TFmode \ 1279 && ! const_zero_operand (X, TFmode))) \ 1280 ? NO_REGS \ 1281 : (!FP_REG_CLASS_P (CLASS) \ 1282 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ 1283 ? GENERAL_REGS \ 1284 : (CLASS)) \ 1285 : (CLASS)) 1286 1287 /* Return the register class of a scratch register needed to load IN into 1288 a register of class CLASS in MODE. 1289 1290 We need a temporary when loading/storing a HImode/QImode value 1291 between memory and the FPU registers. This can happen when combine puts 1292 a paradoxical subreg in a float/fix conversion insn. 1293 1294 We need a temporary when loading/storing a DFmode value between 1295 unaligned memory and the upper FPU registers. */ 1296 1297 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1298 ((FP_REG_CLASS_P (CLASS) \ 1299 && ((MODE) == HImode || (MODE) == QImode) \ 1300 && (GET_CODE (IN) == MEM \ 1301 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1302 && true_regnum (IN) == -1))) \ 1303 ? GENERAL_REGS \ 1304 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1305 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1306 && ! mem_min_alignment ((IN), 8)) \ 1307 ? FP_REGS \ 1308 : (((TARGET_CM_MEDANY \ 1309 && symbolic_operand ((IN), (MODE))) \ 1310 || (TARGET_CM_EMBMEDANY \ 1311 && text_segment_operand ((IN), (MODE)))) \ 1312 && !flag_pic) \ 1313 ? GENERAL_REGS \ 1314 : NO_REGS) 1315 1316 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1317 ((FP_REG_CLASS_P (CLASS) \ 1318 && ((MODE) == HImode || (MODE) == QImode) \ 1319 && (GET_CODE (IN) == MEM \ 1320 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1321 && true_regnum (IN) == -1))) \ 1322 ? GENERAL_REGS \ 1323 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1324 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1325 && ! mem_min_alignment ((IN), 8)) \ 1326 ? FP_REGS \ 1327 : (((TARGET_CM_MEDANY \ 1328 && symbolic_operand ((IN), (MODE))) \ 1329 || (TARGET_CM_EMBMEDANY \ 1330 && text_segment_operand ((IN), (MODE)))) \ 1331 && !flag_pic) \ 1332 ? GENERAL_REGS \ 1333 : NO_REGS) 1334 1335 /* On SPARC it is not possible to directly move data between 1336 GENERAL_REGS and FP_REGS. */ 1337 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1338 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1339 1340 /* Return the stack location to use for secondary memory needed reloads. 1341 We want to use the reserved location just below the frame pointer. 1342 However, we must ensure that there is a frame, so use assign_stack_local 1343 if the frame size is zero. */ 1344 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1345 (get_frame_size () == 0 \ 1346 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ 1347 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \ 1348 STARTING_FRAME_OFFSET))) 1349 1350 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 1351 because the movsi and movsf patterns don't handle r/f moves. 1352 For v8 we copy the default definition. */ 1353 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1354 (TARGET_ARCH64 \ 1355 ? (GET_MODE_BITSIZE (MODE) < 32 \ 1356 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1357 : MODE) \ 1358 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1359 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1360 : MODE)) 1361 1362 /* Return the maximum number of consecutive registers 1363 needed to represent mode MODE in a register of class CLASS. */ 1364 /* On SPARC, this is the size of MODE in words. */ 1365 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1366 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1367 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1368 1369 /* Stack layout; function entry, exit and calling. */ 1370 1371 /* Define this if pushing a word on the stack 1372 makes the stack pointer a smaller address. */ 1373 #define STACK_GROWS_DOWNWARD 1374 1375 /* Define this to nonzero if the nominal address of the stack frame 1376 is at the high-address end of the local variables; 1377 that is, each additional local variable allocated 1378 goes at a more negative offset in the frame. */ 1379 #define FRAME_GROWS_DOWNWARD 1 1380 1381 /* Offset within stack frame to start allocating local variables at. 1382 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1383 first local allocated. Otherwise, it is the offset to the BEGINNING 1384 of the first local allocated. */ 1385 /* This allows space for one TFmode floating point value, which is used 1386 by SECONDARY_MEMORY_NEEDED_RTX. */ 1387 #define STARTING_FRAME_OFFSET \ 1388 (TARGET_ARCH64 ? -16 \ 1389 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) 1390 1391 /* Offset of first parameter from the argument pointer register value. 1392 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1393 even if this function isn't going to use it. 1394 v9: This is 128 for the ins and locals. */ 1395 #define FIRST_PARM_OFFSET(FNDECL) \ 1396 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1397 1398 /* Offset from the argument pointer register value to the CFA. 1399 This is different from FIRST_PARM_OFFSET because the register window 1400 comes between the CFA and the arguments. */ 1401 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1402 1403 /* When a parameter is passed in a register, stack space is still 1404 allocated for it. 1405 !v9: All 6 possible integer registers have backing store allocated. 1406 v9: Only space for the arguments passed is allocated. */ 1407 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1408 meaning to the backend. Further, we need to be able to detect if a 1409 varargs/unprototyped function is called, as they may want to spill more 1410 registers than we've provided space. Ugly, ugly. So for now we retain 1411 all 6 slots even for v9. */ 1412 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1413 1414 /* Definitions for register elimination. */ 1415 1416 #define ELIMINABLE_REGS \ 1417 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1418 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1419 1420 /* The way this is structured, we can't eliminate SFP in favor of SP 1421 if the frame pointer is required: we want to use the SFP->HFP elimination 1422 in that case. But the test in update_eliminables doesn't know we are 1423 assuming below that we only do the former elimination. */ 1424 #define CAN_ELIMINATE(FROM, TO) \ 1425 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED) 1426 1427 /* We always pretend that this is a leaf function because if it's not, 1428 there's no point in trying to eliminate the frame pointer. If it 1429 is a leaf function, we guessed right! */ 1430 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1431 do { \ 1432 if ((TO) == STACK_POINTER_REGNUM) \ 1433 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \ 1434 else \ 1435 (OFFSET) = 0; \ 1436 (OFFSET) += SPARC_STACK_BIAS; \ 1437 } while (0) 1438 1439 /* Keep the stack pointer constant throughout the function. 1440 This is both an optimization and a necessity: longjmp 1441 doesn't behave itself when the stack pointer moves within 1442 the function! */ 1443 #define ACCUMULATE_OUTGOING_ARGS 1 1444 1445 /* Value is the number of bytes of arguments automatically 1446 popped when returning from a subroutine call. 1447 FUNDECL is the declaration node of the function (as a tree), 1448 FUNTYPE is the data type of the function (as a tree), 1449 or for a library call it is an identifier node for the subroutine name. 1450 SIZE is the number of bytes of arguments passed on the stack. */ 1451 1452 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1453 1454 /* Define this macro if the target machine has "register windows". This 1455 C expression returns the register number as seen by the called function 1456 corresponding to register number OUT as seen by the calling function. 1457 Return OUT if register number OUT is not an outbound register. */ 1458 1459 #define INCOMING_REGNO(OUT) \ 1460 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1461 1462 /* Define this macro if the target machine has "register windows". This 1463 C expression returns the register number as seen by the calling function 1464 corresponding to register number IN as seen by the called function. 1465 Return IN if register number IN is not an inbound register. */ 1466 1467 #define OUTGOING_REGNO(IN) \ 1468 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1469 1470 /* Define this macro if the target machine has register windows. This 1471 C expression returns true if the register is call-saved but is in the 1472 register window. */ 1473 1474 #define LOCAL_REGNO(REGNO) \ 1475 ((REGNO) >= 16 && (REGNO) <= 31) 1476 1477 /* Define how to find the value returned by a function. 1478 VALTYPE is the data type of the value (as a tree). 1479 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1480 otherwise, FUNC is 0. */ 1481 1482 /* On SPARC the value is found in the first "output" register. */ 1483 1484 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1485 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) 1486 1487 /* But the called function leaves it in the first "input" register. */ 1488 1489 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1490 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) 1491 1492 /* Define how to find the value returned by a library function 1493 assuming the value has mode MODE. */ 1494 1495 #define LIBCALL_VALUE(MODE) \ 1496 function_value (NULL_TREE, (MODE), 1) 1497 1498 /* 1 if N is a possible register number for a function value 1499 as seen by the caller. 1500 On SPARC, the first "output" reg is used for integer values, 1501 and the first floating point register is used for floating point values. */ 1502 1503 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1504 1505 /* Define the size of space to allocate for the return value of an 1506 untyped_call. */ 1507 1508 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1509 1510 /* 1 if N is a possible register number for function argument passing. 1511 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1512 1513 #define FUNCTION_ARG_REGNO_P(N) \ 1514 (TARGET_ARCH64 \ 1515 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ 1516 : ((N) >= 8 && (N) <= 13)) 1517 1518 /* Define a data type for recording info about an argument list 1519 during the scan of that argument list. This data type should 1520 hold all necessary information about the function itself 1521 and about the args processed so far, enough to enable macros 1522 such as FUNCTION_ARG to determine where the next arg should go. 1523 1524 On SPARC (!v9), this is a single integer, which is a number of words 1525 of arguments scanned so far (including the invisible argument, 1526 if any, which holds the structure-value-address). 1527 Thus 7 or more means all following args should go on the stack. 1528 1529 For v9, we also need to know whether a prototype is present. */ 1530 1531 struct sparc_args { 1532 int words; /* number of words passed so far */ 1533 int prototype_p; /* nonzero if a prototype is present */ 1534 int libcall_p; /* nonzero if a library call */ 1535 }; 1536 #define CUMULATIVE_ARGS struct sparc_args 1537 1538 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1539 for a call to a function whose data type is FNTYPE. 1540 For a library call, FNTYPE is 0. */ 1541 1542 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1543 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1544 1545 /* Update the data in CUM to advance over an argument 1546 of mode MODE and data type TYPE. 1547 TYPE is null for libcalls where that information may not be available. */ 1548 1549 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1550 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) 1551 1552 /* Determine where to put an argument to a function. 1553 Value is zero to push the argument on the stack, 1554 or a hard register in which to store the argument. 1555 1556 MODE is the argument's machine mode. 1557 TYPE is the data type of the argument (as a tree). 1558 This is null for libcalls where that information may 1559 not be available. 1560 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1561 the preceding args and about the function being called. 1562 NAMED is nonzero if this argument is a named parameter 1563 (otherwise it is an extra parameter matching an ellipsis). */ 1564 1565 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1566 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) 1567 1568 /* Define where a function finds its arguments. 1569 This is different from FUNCTION_ARG because of register windows. */ 1570 1571 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1572 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) 1573 1574 /* If defined, a C expression which determines whether, and in which direction, 1575 to pad out an argument with extra space. The value should be of type 1576 `enum direction': either `upward' to pad above the argument, 1577 `downward' to pad below, or `none' to inhibit padding. */ 1578 1579 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1580 function_arg_padding ((MODE), (TYPE)) 1581 1582 /* If defined, a C expression that gives the alignment boundary, in bits, 1583 of an argument with the specified mode and type. If it is not defined, 1584 PARM_BOUNDARY is used for all arguments. 1585 For sparc64, objects requiring 16 byte alignment are passed that way. */ 1586 1587 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1588 ((TARGET_ARCH64 \ 1589 && (GET_MODE_ALIGNMENT (MODE) == 128 \ 1590 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ 1591 ? 128 : PARM_BOUNDARY) 1592 1593 /* Define the information needed to generate branch and scc insns. This is 1594 stored from the compare operation. Note that we can't use "rtx" here 1595 since it hasn't been defined! */ 1596 1597 extern GTY(()) rtx sparc_compare_op0; 1598 extern GTY(()) rtx sparc_compare_op1; 1599 extern GTY(()) rtx sparc_compare_emitted; 1600 1601 1602 /* Generate the special assembly code needed to tell the assembler whatever 1603 it might need to know about the return value of a function. 1604 1605 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1606 information to the assembler relating to peephole optimization (done in 1607 the assembler). */ 1608 1609 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1610 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1611 1612 /* Output the special assembly code needed to tell the assembler some 1613 register is used as global register variable. 1614 1615 SPARC 64bit psABI declares registers %g2 and %g3 as application 1616 registers and %g6 and %g7 as OS registers. Any object using them 1617 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1618 and how they are used (scratch or some global variable). 1619 Linker will then refuse to link together objects which use those 1620 registers incompatibly. 1621 1622 Unless the registers are used for scratch, two different global 1623 registers cannot be declared to the same name, so in the unlikely 1624 case of a global register variable occupying more than one register 1625 we prefix the second and following registers with .gnu.part1. etc. */ 1626 1627 extern GTY(()) char sparc_hard_reg_printed[8]; 1628 1629 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 1630 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1631 do { \ 1632 if (TARGET_ARCH64) \ 1633 { \ 1634 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ 1635 int reg; \ 1636 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1637 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1638 { \ 1639 if (reg == (REGNO)) \ 1640 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1641 else \ 1642 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1643 reg, reg - (REGNO), (NAME)); \ 1644 sparc_hard_reg_printed[reg] = 1; \ 1645 } \ 1646 } \ 1647 } while (0) 1648 #endif 1649 1650 1651 /* Emit rtl for profiling. */ 1652 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1653 1654 /* All the work done in PROFILE_HOOK, but still required. */ 1655 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1656 1657 /* Set the name of the mcount function for the system. */ 1658 #define MCOUNT_FUNCTION "*mcount" 1659 1660 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1661 the stack pointer does not matter. The value is tested only in 1662 functions that have frame pointers. 1663 No definition is equivalent to always zero. */ 1664 1665 #define EXIT_IGNORE_STACK \ 1666 (get_frame_size () != 0 \ 1667 || current_function_calls_alloca || current_function_outgoing_args_size) 1668 1669 /* Define registers used by the epilogue and return instruction. */ 1670 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \ 1671 || (current_function_calls_eh_return && (REGNO) == 1)) 1672 1673 /* Length in units of the trampoline for entering a nested function. */ 1674 1675 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1676 1677 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ 1678 1679 /* Emit RTL insns to initialize the variable parts of a trampoline. 1680 FNADDR is an RTX for the address of the function's pure code. 1681 CXT is an RTX for the static chain value for the function. */ 1682 1683 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1684 if (TARGET_ARCH64) \ 1685 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1686 else \ 1687 sparc_initialize_trampoline (TRAMP, FNADDR, CXT) 1688 1689 /* Implement `va_start' for varargs and stdarg. */ 1690 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1691 sparc_va_start (valist, nextarg) 1692 1693 /* Generate RTL to flush the register windows so as to make arbitrary frames 1694 available. */ 1695 #define SETUP_FRAME_ADDRESSES() \ 1696 emit_insn (gen_flush_register_windows ()) 1697 1698 /* Given an rtx for the address of a frame, 1699 return an rtx for the address of the word in the frame 1700 that holds the dynamic chain--the previous frame's address. */ 1701 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1702 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1703 1704 /* Given an rtx for the frame pointer, 1705 return an rtx for the address of the frame. */ 1706 #define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS) 1707 1708 /* The return address isn't on the stack, it is in a register, so we can't 1709 access it from the current frame pointer. We can access it from the 1710 previous frame pointer though by reading a value from the register window 1711 save area. */ 1712 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1713 1714 /* This is the offset of the return address to the true next instruction to be 1715 executed for the current function. */ 1716 #define RETURN_ADDR_OFFSET \ 1717 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) 1718 1719 /* The current return address is in %i7. The return address of anything 1720 farther back is in the register window save area at [%fp+60]. */ 1721 /* ??? This ignores the fact that the actual return address is +8 for normal 1722 returns, and +12 for structure returns. */ 1723 #define RETURN_ADDR_RTX(count, frame) \ 1724 ((count == -1) \ 1725 ? gen_rtx_REG (Pmode, 31) \ 1726 : gen_rtx_MEM (Pmode, \ 1727 memory_address (Pmode, plus_constant (frame, \ 1728 15 * UNITS_PER_WORD \ 1729 + SPARC_STACK_BIAS)))) 1730 1731 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1732 +12, but always using +8 is close enough for frame unwind purposes. 1733 Actually, just using %o7 is close enough for unwinding, but %o7+8 1734 is something you can return to. */ 1735 #define INCOMING_RETURN_ADDR_RTX \ 1736 plus_constant (gen_rtx_REG (word_mode, 15), 8) 1737 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15) 1738 1739 /* The offset from the incoming value of %sp to the top of the stack frame 1740 for the current function. On sparc64, we have to account for the stack 1741 bias if present. */ 1742 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1743 1744 /* Describe how we implement __builtin_eh_return. */ 1745 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1746 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */ 1747 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */ 1748 1749 /* Select a format to encode pointers in exception handling data. CODE 1750 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1751 true if the symbol may be affected by dynamic relocations. 1752 1753 If assembler and linker properly support .uaword %r_disp32(foo), 1754 then use PC relative 32-bit relocations instead of absolute relocs 1755 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1756 for binaries, to save memory. 1757 1758 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1759 symbol %r_disp32() is against was not local, but .hidden. In that 1760 case, we have to use DW_EH_PE_absptr for pic personality. */ 1761 #ifdef HAVE_AS_SPARC_UA_PCREL 1762 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1763 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1764 (flag_pic \ 1765 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1766 : ((TARGET_ARCH64 && ! GLOBAL) \ 1767 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1768 : DW_EH_PE_absptr)) 1769 #else 1770 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1771 (flag_pic \ 1772 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1773 : ((TARGET_ARCH64 && ! GLOBAL) \ 1774 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1775 : DW_EH_PE_absptr)) 1776 #endif 1777 1778 /* Emit a PC-relative relocation. */ 1779 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1780 do { \ 1781 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1782 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1783 assemble_name (FILE, LABEL); \ 1784 fputc (')', FILE); \ 1785 } while (0) 1786 #endif 1787 1788 /* Addressing modes, and classification of registers for them. */ 1789 1790 /* Macros to check register numbers against specific register classes. */ 1791 1792 /* These assume that REGNO is a hard or pseudo reg number. 1793 They give nonzero only if REGNO is a hard reg of the suitable class 1794 or a pseudo reg currently allocated to a suitable hard reg. 1795 Since they use reg_renumber, they are safe only once reg_renumber 1796 has been allocated, which happens in local-alloc.c. */ 1797 1798 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1799 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ 1800 || (REGNO) == FRAME_POINTER_REGNUM \ 1801 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1802 1803 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1804 1805 #define REGNO_OK_FOR_FP_P(REGNO) \ 1806 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1807 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1808 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1809 (TARGET_V9 \ 1810 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1811 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1812 1813 /* Now macros that check whether X is a register and also, 1814 strictly, whether it is in a specified class. 1815 1816 These macros are specific to the SPARC, and may be used only 1817 in code for printing assembler insns and in conditions for 1818 define_optimization. */ 1819 1820 /* 1 if X is an fp register. */ 1821 1822 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1823 1824 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ 1825 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) 1826 1827 /* Maximum number of registers that can appear in a valid memory address. */ 1828 1829 #define MAX_REGS_PER_ADDRESS 2 1830 1831 /* Recognize any constant value that is a valid address. 1832 When PIC, we do not accept an address that would require a scratch reg 1833 to load into a register. */ 1834 1835 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1836 1837 /* Define this, so that when PIC, reload won't try to reload invalid 1838 addresses which require two reload registers. */ 1839 1840 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1841 1842 /* Nonzero if the constant value X is a legitimate general operand. 1843 Anything can be made to work except floating point constants. 1844 If TARGET_VIS, 0.0 can be made to work as well. */ 1845 1846 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1847 1848 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1849 and check its validity for a certain class. 1850 We have two alternate definitions for each of them. 1851 The usual definition accepts all pseudo regs; the other rejects 1852 them unless they have been allocated suitable hard regs. 1853 The symbol REG_OK_STRICT causes the latter definition to be used. 1854 1855 Most source files want to accept pseudo regs in the hope that 1856 they will get allocated to the class that the insn wants them to be in. 1857 Source files for reload pass need to be strict. 1858 After reload, it makes no difference, since pseudo regs have 1859 been eliminated by then. */ 1860 1861 /* Optional extra constraints for this machine. 1862 1863 'Q' handles floating point constants which can be moved into 1864 an integer register with a single sethi instruction. 1865 1866 'R' handles floating point constants which can be moved into 1867 an integer register with a single mov instruction. 1868 1869 'S' handles floating point constants which can be moved into 1870 an integer register using a high/lo_sum sequence. 1871 1872 'T' handles memory addresses where the alignment is known to 1873 be at least 8 bytes. 1874 1875 `U' handles all pseudo registers or a hard even numbered 1876 integer register, needed for ldd/std instructions. 1877 1878 'W' handles the memory operand when moving operands in/out 1879 of 'e' constraint floating point registers. 1880 1881 'Y' handles the zero vector constant. */ 1882 1883 #ifndef REG_OK_STRICT 1884 1885 /* Nonzero if X is a hard reg that can be used as an index 1886 or if it is a pseudo reg. */ 1887 #define REG_OK_FOR_INDEX_P(X) \ 1888 (REGNO (X) < 32 \ 1889 || REGNO (X) == FRAME_POINTER_REGNUM \ 1890 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1891 1892 /* Nonzero if X is a hard reg that can be used as a base reg 1893 or if it is a pseudo reg. */ 1894 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) 1895 1896 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. 1897 'W' is like 'T' but is assumed true on arch64. 1898 1899 Remember to accept pseudo-registers for memory constraints if reload is 1900 in progress. */ 1901 1902 #define EXTRA_CONSTRAINT(OP, C) \ 1903 sparc_extra_constraint_check(OP, C, 0) 1904 1905 #else 1906 1907 /* Nonzero if X is a hard reg that can be used as an index. */ 1908 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1909 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1910 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1911 1912 #define EXTRA_CONSTRAINT(OP, C) \ 1913 sparc_extra_constraint_check(OP, C, 1) 1914 1915 #endif 1916 1917 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1918 1919 #ifdef HAVE_AS_OFFSETABLE_LO10 1920 #define USE_AS_OFFSETABLE_LO10 1 1921 #else 1922 #define USE_AS_OFFSETABLE_LO10 0 1923 #endif 1924 1925 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1926 that is a valid memory address for an instruction. 1927 The MODE argument is the machine mode for the MEM expression 1928 that wants to use this address. 1929 1930 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 1931 ordinarily. This changes a bit when generating PIC. 1932 1933 If you change this, execute "rm explow.o recog.o reload.o". */ 1934 1935 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) 1936 1937 #define RTX_OK_FOR_BASE_P(X) \ 1938 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1939 || (GET_CODE (X) == SUBREG \ 1940 && GET_CODE (SUBREG_REG (X)) == REG \ 1941 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1942 1943 #define RTX_OK_FOR_INDEX_P(X) \ 1944 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1945 || (GET_CODE (X) == SUBREG \ 1946 && GET_CODE (SUBREG_REG (X)) == REG \ 1947 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1948 1949 #define RTX_OK_FOR_OFFSET_P(X) \ 1950 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) 1951 1952 #define RTX_OK_FOR_OLO10_P(X) \ 1953 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) 1954 1955 #ifdef REG_OK_STRICT 1956 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1957 { \ 1958 if (legitimate_address_p (MODE, X, 1)) \ 1959 goto ADDR; \ 1960 } 1961 #else 1962 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1963 { \ 1964 if (legitimate_address_p (MODE, X, 0)) \ 1965 goto ADDR; \ 1966 } 1967 #endif 1968 1969 /* Go to LABEL if ADDR (a legitimate address expression) 1970 has an effect that depends on the machine mode it is used for. 1971 1972 In PIC mode, 1973 1974 (mem:HI [%l7+a]) 1975 1976 is not equivalent to 1977 1978 (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) 1979 1980 because [%l7+a+1] is interpreted as the address of (a+1). */ 1981 1982 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1983 { \ 1984 if (flag_pic == 1) \ 1985 { \ 1986 if (GET_CODE (ADDR) == PLUS) \ 1987 { \ 1988 rtx op0 = XEXP (ADDR, 0); \ 1989 rtx op1 = XEXP (ADDR, 1); \ 1990 if (op0 == pic_offset_table_rtx \ 1991 && SYMBOLIC_CONST (op1)) \ 1992 goto LABEL; \ 1993 } \ 1994 } \ 1995 } 1996 1997 /* Try machine-dependent ways of modifying an illegitimate address 1998 to be legitimate. If we find one, return the new, valid address. 1999 This macro is used in only one place: `memory_address' in explow.c. 2000 2001 OLDX is the address as it was before break_out_memory_refs was called. 2002 In some cases it is useful to look at this to decide what needs to be done. 2003 2004 MODE and WIN are passed so that this macro can use 2005 GO_IF_LEGITIMATE_ADDRESS. 2006 2007 It is always safe for this macro to do nothing. It exists to recognize 2008 opportunities to optimize the output. */ 2009 2010 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 2011 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2012 { \ 2013 (X) = legitimize_address (X, OLDX, MODE); \ 2014 if (memory_address_p (MODE, X)) \ 2015 goto WIN; \ 2016 } 2017 2018 /* Try a machine-dependent way of reloading an illegitimate address 2019 operand. If we find one, push the reload and jump to WIN. This 2020 macro is used in only one place: `find_reloads_address' in reload.c. 2021 2022 For SPARC 32, we wish to handle addresses by splitting them into 2023 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. 2024 This cuts the number of extra insns by one. 2025 2026 Do nothing when generating PIC code and the address is a 2027 symbolic operand or requires a scratch register. */ 2028 2029 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2030 do { \ 2031 /* Decompose SImode constants into hi+lo_sum. We do have to \ 2032 rerecognize what we produce, so be careful. */ \ 2033 if (CONSTANT_P (X) \ 2034 && (MODE != TFmode || TARGET_ARCH64) \ 2035 && GET_MODE (X) == SImode \ 2036 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ 2037 && ! (flag_pic \ 2038 && (symbolic_operand (X, Pmode) \ 2039 || pic_address_needs_scratch (X))) \ 2040 && sparc_cmodel <= CM_MEDLOW) \ 2041 { \ 2042 X = gen_rtx_LO_SUM (GET_MODE (X), \ 2043 gen_rtx_HIGH (GET_MODE (X), X), X); \ 2044 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 2045 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 2046 OPNUM, TYPE); \ 2047 goto WIN; \ 2048 } \ 2049 /* ??? 64-bit reloads. */ \ 2050 } while (0) 2051 2052 /* Specify the machine mode that this machine uses 2053 for the index in the tablejump instruction. */ 2054 /* If we ever implement any of the full models (such as CM_FULLANY), 2055 this has to be DImode in that case */ 2056 #ifdef HAVE_GAS_SUBSECTION_ORDERING 2057 #define CASE_VECTOR_MODE \ 2058 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 2059 #else 2060 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 2061 we have to sign extend which slows things down. */ 2062 #define CASE_VECTOR_MODE \ 2063 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 2064 #endif 2065 2066 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2067 #define DEFAULT_SIGNED_CHAR 1 2068 2069 /* Max number of bytes we can move from memory to memory 2070 in one reasonably fast instruction. */ 2071 #define MOVE_MAX 8 2072 2073 /* If a memory-to-memory move would take MOVE_RATIO or more simple 2074 move-instruction pairs, we will do a movmem or libcall instead. */ 2075 2076 #define MOVE_RATIO (optimize_size ? 3 : 8) 2077 2078 /* Define if operations between registers always perform the operation 2079 on the full register even if a narrower mode is specified. */ 2080 #define WORD_REGISTER_OPERATIONS 2081 2082 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2083 will either zero-extend or sign-extend. The value of this macro should 2084 be the code that says which one of the two operations is implicitly 2085 done, UNKNOWN if none. */ 2086 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2087 2088 /* Nonzero if access to memory by bytes is slow and undesirable. 2089 For RISC chips, it means that access to memory by bytes is no 2090 better than access by words when possible, so grab a whole word 2091 and maybe make use of that. */ 2092 #define SLOW_BYTE_ACCESS 1 2093 2094 /* Define this to be nonzero if shift instructions ignore all but the low-order 2095 few bits. */ 2096 #define SHIFT_COUNT_TRUNCATED 1 2097 2098 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2099 is done just by pretending it is already truncated. */ 2100 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2101 2102 /* Specify the machine mode used for addresses. */ 2103 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 2104 2105 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2106 return the mode to be used for the comparison. For floating-point, 2107 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2108 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2109 processing is needed. */ 2110 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 2111 2112 /* Return nonzero if MODE implies a floating point inequality can be 2113 reversed. For SPARC this is always true because we have a full 2114 compliment of ordered and unordered comparisons, but until generic 2115 code knows how to reverse it correctly we keep the old definition. */ 2116 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 2117 2118 /* A function address in a call instruction for indexing purposes. */ 2119 #define FUNCTION_MODE Pmode 2120 2121 /* Define this if addresses of constant functions 2122 shouldn't be put through pseudo regs where they can be cse'd. 2123 Desirable on machines where ordinary constants are expensive 2124 but a CALL with constant address is cheap. */ 2125 #define NO_FUNCTION_CSE 2126 2127 /* alloca should avoid clobbering the old register save area. */ 2128 #define SETJMP_VIA_SAVE_AREA 2129 2130 /* The _Q_* comparison libcalls return booleans. */ 2131 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 2132 2133 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 2134 that the inputs are fully consumed before the output memory is clobbered. */ 2135 2136 #define TARGET_BUGGY_QP_LIB 0 2137 2138 /* Assume by default that we do not have the Solaris-specific conversion 2139 routines nor 64-bit integer multiply and divide routines. */ 2140 2141 #define SUN_CONVERSION_LIBFUNCS 0 2142 #define DITF_CONVERSION_LIBFUNCS 0 2143 #define SUN_INTEGER_MULTIPLY_64 0 2144 2145 /* Compute extra cost of moving data between one register class 2146 and another. */ 2147 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) 2148 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2149 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ 2150 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ 2151 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ 2152 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2153 || sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2154 || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2) 2155 2156 /* Provide the cost of a branch. For pre-v9 processors we use 2157 a value of 3 to take into account the potential annulling of 2158 the delay slot (which ends up being a bubble in the pipeline slot) 2159 plus a cycle to take into consideration the instruction cache 2160 effects. 2161 2162 On v9 and later, which have branch prediction facilities, we set 2163 it to the depth of the pipeline as that is the cost of a 2164 mispredicted branch. 2165 2166 On Niagara, normal branches insert 3 bubbles into the pipe 2167 and annulled branches insert 4 bubbles. */ 2168 2169 #define BRANCH_COST \ 2170 ((sparc_cpu == PROCESSOR_V9 \ 2171 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 2172 ? 7 \ 2173 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2174 ? 9 \ 2175 : (sparc_cpu == PROCESSOR_NIAGARA \ 2176 ? 4 \ 2177 : 3))) 2178 2179 #define PREFETCH_BLOCK \ 2180 ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2181 || sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2182 || sparc_cpu == PROCESSOR_NIAGARA) \ 2183 ? 64 : 32) 2184 2185 #define SIMULTANEOUS_PREFETCHES \ 2186 ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2187 || sparc_cpu == PROCESSOR_NIAGARA) \ 2188 ? 2 \ 2189 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2190 ? 8 : 3)) 2191 2192 /* Control the assembler format that we output. */ 2193 2194 /* A C string constant describing how to begin a comment in the target 2195 assembler language. The compiler assumes that the comment will end at 2196 the end of the line. */ 2197 2198 #define ASM_COMMENT_START "!" 2199 2200 /* Output to assembler file text saying following lines 2201 may contain character constants, extra white space, comments, etc. */ 2202 2203 #define ASM_APP_ON "" 2204 2205 /* Output to assembler file text saying following lines 2206 no longer contain unusual constructs. */ 2207 2208 #define ASM_APP_OFF "" 2209 2210 /* How to refer to registers in assembler output. 2211 This sequence is indexed by compiler's hard-register-number (see above). */ 2212 2213 #define REGISTER_NAMES \ 2214 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2215 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2216 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2217 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2218 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2219 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2220 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2221 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 2222 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 2223 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 2224 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 2225 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 2226 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" } 2227 2228 /* Define additional names for use in asm clobbers and asm declarations. */ 2229 2230 #define ADDITIONAL_REGISTER_NAMES \ 2231 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 2232 2233 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 2234 can run past this up to a continuation point. Once we used 1500, but 2235 a single entry in C++ can run more than 500 bytes, due to the length of 2236 mangled symbol names. dbxout.c should really be fixed to do 2237 continuations when they are actually needed instead of trying to 2238 guess... */ 2239 #define DBX_CONTIN_LENGTH 1000 2240 2241 /* This is how to output a command to make the user-level label named NAME 2242 defined for reference from other files. */ 2243 2244 /* Globalizing directive for a label. */ 2245 #define GLOBAL_ASM_OP "\t.global " 2246 2247 /* The prefix to add to user-visible assembler symbols. */ 2248 2249 #define USER_LABEL_PREFIX "_" 2250 2251 /* This is how to store into the string LABEL 2252 the symbol_ref name of an internal numbered label where 2253 PREFIX is the class of label and NUM is the number within the class. 2254 This is suitable for output with `assemble_name'. */ 2255 2256 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2257 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 2258 2259 /* This is how we hook in and defer the case-vector until the end of 2260 the function. */ 2261 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 2262 sparc_defer_case_vector ((LAB),(VEC), 0) 2263 2264 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 2265 sparc_defer_case_vector ((LAB),(VEC), 1) 2266 2267 /* This is how to output an element of a case-vector that is absolute. */ 2268 2269 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2270 do { \ 2271 char label[30]; \ 2272 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 2273 if (CASE_VECTOR_MODE == SImode) \ 2274 fprintf (FILE, "\t.word\t"); \ 2275 else \ 2276 fprintf (FILE, "\t.xword\t"); \ 2277 assemble_name (FILE, label); \ 2278 fputc ('\n', FILE); \ 2279 } while (0) 2280 2281 /* This is how to output an element of a case-vector that is relative. 2282 (SPARC uses such vectors only when generating PIC.) */ 2283 2284 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2285 do { \ 2286 char label[30]; \ 2287 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 2288 if (CASE_VECTOR_MODE == SImode) \ 2289 fprintf (FILE, "\t.word\t"); \ 2290 else \ 2291 fprintf (FILE, "\t.xword\t"); \ 2292 assemble_name (FILE, label); \ 2293 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 2294 fputc ('-', FILE); \ 2295 assemble_name (FILE, label); \ 2296 fputc ('\n', FILE); \ 2297 } while (0) 2298 2299 /* This is what to output before and after case-vector (both 2300 relative and absolute). If .subsection -1 works, we put case-vectors 2301 at the beginning of the current section. */ 2302 2303 #ifdef HAVE_GAS_SUBSECTION_ORDERING 2304 2305 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 2306 fprintf(FILE, "\t.subsection\t-1\n") 2307 2308 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 2309 fprintf(FILE, "\t.previous\n") 2310 2311 #endif 2312 2313 /* This is how to output an assembler line 2314 that says to advance the location counter 2315 to a multiple of 2**LOG bytes. */ 2316 2317 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2318 if ((LOG) != 0) \ 2319 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2320 2321 /* This is how to output an assembler line that says to advance 2322 the location counter to a multiple of 2**LOG bytes using the 2323 "nop" instruction as padding. */ 2324 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ 2325 if ((LOG) != 0) \ 2326 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG))) 2327 2328 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2329 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2330 2331 /* This says how to output an assembler line 2332 to define a global common symbol. */ 2333 2334 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 2335 ( fputs ("\t.common ", (FILE)), \ 2336 assemble_name ((FILE), (NAME)), \ 2337 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 2338 2339 /* This says how to output an assembler line to define a local common 2340 symbol. */ 2341 2342 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 2343 ( fputs ("\t.reserve ", (FILE)), \ 2344 assemble_name ((FILE), (NAME)), \ 2345 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 2346 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 2347 2348 /* A C statement (sans semicolon) to output to the stdio stream 2349 FILE the assembler definition of uninitialized global DECL named 2350 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 2351 Try to use asm_output_aligned_bss to implement this macro. */ 2352 2353 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 2354 do { \ 2355 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 2356 } while (0) 2357 2358 #define IDENT_ASM_OP "\t.ident\t" 2359 2360 /* Output #ident as a .ident. */ 2361 2362 #define ASM_OUTPUT_IDENT(FILE, NAME) \ 2363 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); 2364 2365 /* Prettify the assembly. */ 2366 2367 extern int sparc_indent_opcode; 2368 2369 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 2370 do { \ 2371 if (sparc_indent_opcode) \ 2372 { \ 2373 putc (' ', FILE); \ 2374 sparc_indent_opcode = 0; \ 2375 } \ 2376 } while (0) 2377 2378 #define SPARC_SYMBOL_REF_TLS_P(RTX) \ 2379 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 2380 2381 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2382 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \ 2383 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&') 2384 2385 /* Print operand X (an rtx) in assembler syntax to file FILE. 2386 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2387 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2388 2389 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2390 2391 /* Print a memory address as an operand to reference that memory location. */ 2392 2393 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2394 { register rtx base, index = 0; \ 2395 int offset = 0; \ 2396 register rtx addr = ADDR; \ 2397 if (GET_CODE (addr) == REG) \ 2398 fputs (reg_names[REGNO (addr)], FILE); \ 2399 else if (GET_CODE (addr) == PLUS) \ 2400 { \ 2401 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2402 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2403 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2404 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2405 else \ 2406 base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2407 if (GET_CODE (base) == LO_SUM) \ 2408 { \ 2409 gcc_assert (USE_AS_OFFSETABLE_LO10 \ 2410 && TARGET_ARCH64 \ 2411 && ! TARGET_CM_MEDMID); \ 2412 output_operand (XEXP (base, 0), 0); \ 2413 fputs ("+%lo(", FILE); \ 2414 output_address (XEXP (base, 1)); \ 2415 fprintf (FILE, ")+%d", offset); \ 2416 } \ 2417 else \ 2418 { \ 2419 fputs (reg_names[REGNO (base)], FILE); \ 2420 if (index == 0) \ 2421 fprintf (FILE, "%+d", offset); \ 2422 else if (GET_CODE (index) == REG) \ 2423 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 2424 else if (GET_CODE (index) == SYMBOL_REF \ 2425 || GET_CODE (index) == CONST) \ 2426 fputc ('+', FILE), output_addr_const (FILE, index); \ 2427 else gcc_unreachable (); \ 2428 } \ 2429 } \ 2430 else if (GET_CODE (addr) == MINUS \ 2431 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2432 { \ 2433 output_addr_const (FILE, XEXP (addr, 0)); \ 2434 fputs ("-(", FILE); \ 2435 output_addr_const (FILE, XEXP (addr, 1)); \ 2436 fputs ("-.)", FILE); \ 2437 } \ 2438 else if (GET_CODE (addr) == LO_SUM) \ 2439 { \ 2440 output_operand (XEXP (addr, 0), 0); \ 2441 if (TARGET_CM_MEDMID) \ 2442 fputs ("+%l44(", FILE); \ 2443 else \ 2444 fputs ("+%lo(", FILE); \ 2445 output_address (XEXP (addr, 1)); \ 2446 fputc (')', FILE); \ 2447 } \ 2448 else if (flag_pic && GET_CODE (addr) == CONST \ 2449 && GET_CODE (XEXP (addr, 0)) == MINUS \ 2450 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2451 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2452 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 2453 { \ 2454 addr = XEXP (addr, 0); \ 2455 output_addr_const (FILE, XEXP (addr, 0)); \ 2456 /* Group the args of the second CONST in parenthesis. */ \ 2457 fputs ("-(", FILE); \ 2458 /* Skip past the second CONST--it does nothing for us. */\ 2459 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 2460 /* Close the parenthesis. */ \ 2461 fputc (')', FILE); \ 2462 } \ 2463 else \ 2464 { \ 2465 output_addr_const (FILE, addr); \ 2466 } \ 2467 } 2468 2469 /* TLS support defaulting to original Sun flavor. GNU extensions 2470 must be activated in separate configuration files. */ 2471 #ifdef HAVE_AS_TLS 2472 #define TARGET_TLS 1 2473 #else 2474 #define TARGET_TLS 0 2475 #endif 2476 2477 #define TARGET_SUN_TLS TARGET_TLS 2478 #define TARGET_GNU_TLS 0 2479 2480 /* The number of Pmode words for the setjmp buffer. */ 2481 #define JMP_BUF_SIZE 12 2482