1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #ifndef _ROC_CPT_H_
6 #define _ROC_CPT_H_
7
8 #include "roc_api.h"
9
10 #define ROC_AE_CPT_BLOCK_TYPE1 0
11 #define ROC_AE_CPT_BLOCK_TYPE2 1
12
13 /* Default engine groups */
14 #define ROC_CPT_DFLT_ENG_GRP_SE 0UL
15 #define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL
16 #define ROC_CPT_DFLT_ENG_GRP_AE 2UL
17
18 #define ROC_CPT_MAX_LFS 64
19 #define ROC_CPT_MAX_BLKS 2
20 #define ROC_CN10K_CPT_INST_DW_M1 \
21 ((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7))
22 #define ROC_CN10K_TWO_CPT_INST_DW_M1 \
23 ((uint64_t)(((sizeof(struct cpt_inst_s) * 2 / 16) - 1) & 0x7))
24
25 /* Vector of sizes in the burst of 16 CPT inst except first in 63:19 of
26 * APT_LMT_ARG_S
27 */
28 #define ROC_CN10K_CPT_LMT_ARG \
29 (ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 0) | \
30 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 1) | \
31 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 2) | \
32 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 3) | \
33 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 4) | \
34 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 5) | \
35 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 6) | \
36 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 7) | \
37 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 8) | \
38 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 9) | \
39 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 10) | \
40 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 11) | \
41 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 12) | \
42 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 13) | \
43 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 14))
44
45 /* CPT helper macros */
46 #define ROC_CPT_AH_HDR_LEN 12
47 #define ROC_CPT_AES_GCM_IV_LEN 8
48 #define ROC_CPT_AES_GCM_MAC_LEN 16
49 #define ROC_CPT_AES_CBC_IV_LEN 16
50 #define ROC_CPT_SHA1_HMAC_LEN 12
51 #define ROC_CPT_SHA2_HMAC_LEN 16
52
53 #define ROC_CPT_DES3_KEY_LEN 24
54 #define ROC_CPT_AES128_KEY_LEN 16
55 #define ROC_CPT_AES192_KEY_LEN 24
56 #define ROC_CPT_AES256_KEY_LEN 32
57 #define ROC_CPT_MD5_KEY_LENGTH 16
58 #define ROC_CPT_SHA1_KEY_LENGTH 20
59 #define ROC_CPT_SHA256_KEY_LENGTH 32
60 #define ROC_CPT_SHA384_KEY_LENGTH 48
61 #define ROC_CPT_SHA512_KEY_LENGTH 64
62 #define ROC_CPT_AES_XCBC_KEY_LENGTH 16
63 #define ROC_CPT_AUTH_KEY_LEN_MAX 64
64
65 #define ROC_CPT_DES_BLOCK_LENGTH 8
66 #define ROC_CPT_AES_BLOCK_LENGTH 16
67
68 #define ROC_CPT_AES_GCM_ROUNDUP_BYTE_LEN 4
69 #define ROC_CPT_AES_CBC_ROUNDUP_BYTE_LEN 16
70
71 /* Salt length for AES-CTR/GCM/CCM and AES-GMAC */
72 #define ROC_CPT_SALT_LEN 4
73
74 #define ROC_CPT_ESP_HDR_LEN 8
75 #define ROC_CPT_ESP_TRL_LEN 2
76 #define ROC_CPT_AH_HDR_LEN 12
77 #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20
78 #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40
79
80 #define ROC_CPT_CCM_AAD_DATA 1
81 #define ROC_CPT_CCM_MSG_LEN 4
82 #define ROC_CPT_CCM_ICV_LEN 16
83 #define ROC_CPT_CCM_FLAGS \
84 ((ROC_CPT_CCM_AAD_DATA << 6) | \
85 (((ROC_CPT_CCM_ICV_LEN - 2) / 2) << 3) | (ROC_CPT_CCM_MSG_LEN - 1))
86 #define ROC_CPT_CCM_SALT_LEN 3
87
88 #define ROC_CPT_RES_ALIGN 16
89
90 enum {
91 ROC_CPT_REVISION_ID_83XX = 0,
92 ROC_CPT_REVISION_ID_96XX_B0 = 1,
93 ROC_CPT_REVISION_ID_96XX_C0 = 2,
94 ROC_CPT_REVISION_ID_98XX = 3,
95 ROC_CPT_REVISION_ID_106XX = 4,
96 };
97
98 struct roc_cpt_lmtline {
99 uint64_t io_addr;
100 uint64_t *fc_addr;
101 uintptr_t lmt_base;
102 };
103
104 struct roc_cpt_lf {
105 /* Input parameters */
106 uint16_t lf_id;
107 uint32_t nb_desc;
108 /* End of Input parameters */
109 struct plt_pci_device *pci_dev;
110 struct dev *dev;
111 struct roc_cpt *roc_cpt;
112 uintptr_t rbase;
113 uintptr_t lmt_base;
114 uint16_t msixoff;
115 uint16_t pf_func;
116 uint64_t *fc_addr;
117 uint32_t fc_hyst_bits;
118 uint64_t fc_thresh;
119 uint64_t io_addr;
120 uint8_t *iq_vaddr;
121 struct roc_nix *inl_outb_nix;
122 } __plt_cache_aligned;
123
124 struct roc_cpt {
125 struct plt_pci_device *pci_dev;
126 struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];
127 uint16_t nb_lf;
128 uint16_t nb_lf_avail;
129 uintptr_t lmt_base;
130 /**< CPT device capabilities */
131 union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
132 uint8_t eng_grp[CPT_MAX_ENG_TYPES];
133 uint8_t cpt_revision;
134
135 #define ROC_CPT_MEM_SZ (6 * 1024)
136 uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
137 } __plt_cache_aligned;
138
139 struct roc_cpt_rxc_time_cfg {
140 uint32_t step;
141 uint16_t active_limit;
142 uint16_t active_thres;
143 uint16_t zombie_limit;
144 uint16_t zombie_thres;
145 };
146
147 static inline int
roc_cpt_is_iq_full(struct roc_cpt_lf * lf)148 roc_cpt_is_iq_full(struct roc_cpt_lf *lf)
149 {
150 if (*lf->fc_addr < lf->fc_thresh)
151 return 0;
152
153 return 1;
154 }
155
156 int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
157 struct roc_cpt_rxc_time_cfg *cfg);
158 int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
159 int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
160 int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
161 enum cpt_eng_type eng_type);
162 int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
163 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
164 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
165 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
166 int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr,
167 bool inval);
168 int __roc_api roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr);
169 int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot,
170 struct roc_nix *nix);
171 int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,
172 uint16_t param1, uint16_t param2);
173 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
174 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
175 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
176 void __roc_api roc_cpt_iq_enable(struct roc_cpt_lf *lf);
177 int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt,
178 struct roc_cpt_lmtline *lmtline, int lf_id);
179
180 void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth);
181 int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
182 void *sa_cptr, uint16_t sa_len);
183
184 #endif /* _ROC_CPT_H_ */
185