1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (C) 2012-2014 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #ifndef __NVME_PRIVATE_H__
32 #define __NVME_PRIVATE_H__
33
34 #include <sys/param.h>
35 #include <sys/bio.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43 #include <sys/systm.h>
44 #include <sys/taskqueue.h>
45
46 #include <vm/uma.h>
47
48 #include <machine/bus.h>
49
50 #include "nvme.h"
51
52 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
53
54 MALLOC_DECLARE(M_NVME);
55
56 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
57 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
58
59 #define NVME_ADMIN_TRACKERS (16)
60 #define NVME_ADMIN_ENTRIES (128)
61 /* min and max are defined in admin queue attributes section of spec */
62 #define NVME_MIN_ADMIN_ENTRIES (2)
63 #define NVME_MAX_ADMIN_ENTRIES (4096)
64
65 /*
66 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
67 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
68 * will allow outstanding on an I/O qpair at any time. The only advantage in
69 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
70 * the contents of the submission and completion queues, it will show a longer
71 * history of data.
72 */
73 #define NVME_IO_ENTRIES (256)
74 #define NVME_IO_TRACKERS (128)
75 #define NVME_MIN_IO_TRACKERS (4)
76 #define NVME_MAX_IO_TRACKERS (1024)
77
78 /*
79 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
80 * for each controller.
81 */
82
83 #define NVME_INT_COAL_TIME (0) /* disabled */
84 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
85
86 #define NVME_MAX_NAMESPACES (16)
87 #define NVME_MAX_CONSUMERS (2)
88 #define NVME_MAX_ASYNC_EVENTS (8)
89
90 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */
91 #define NVME_MIN_TIMEOUT_PERIOD (5)
92 #define NVME_MAX_TIMEOUT_PERIOD (120)
93
94 #define NVME_DEFAULT_RETRY_COUNT (4)
95
96 /* Maximum log page size to fetch for AERs. */
97 #define NVME_MAX_AER_LOG_SIZE (4096)
98
99 /*
100 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
101 * it.
102 */
103 #ifndef CACHE_LINE_SIZE
104 #define CACHE_LINE_SIZE (64)
105 #endif
106
107 #define NVME_GONE 0xfffffffful
108
109 extern int32_t nvme_retry_count;
110 extern bool nvme_verbose_cmd_dump;
111
112 struct nvme_completion_poll_status {
113 struct nvme_completion cpl;
114 int done;
115 };
116
117 extern devclass_t nvme_devclass;
118
119 #define NVME_REQUEST_VADDR 1
120 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */
121 #define NVME_REQUEST_UIO 3
122 #define NVME_REQUEST_BIO 4
123 #define NVME_REQUEST_CCB 5
124
125 struct nvme_request {
126 struct nvme_command cmd;
127 struct nvme_qpair *qpair;
128 union {
129 void *payload;
130 struct bio *bio;
131 } u;
132 uint32_t type;
133 uint32_t payload_size;
134 bool timeout;
135 nvme_cb_fn_t cb_fn;
136 void *cb_arg;
137 int32_t retries;
138 STAILQ_ENTRY(nvme_request) stailq;
139 };
140
141 struct nvme_async_event_request {
142 struct nvme_controller *ctrlr;
143 struct nvme_request *req;
144 struct nvme_completion cpl;
145 uint32_t log_page_id;
146 uint32_t log_page_size;
147 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE];
148 };
149
150 struct nvme_tracker {
151 TAILQ_ENTRY(nvme_tracker) tailq;
152 struct nvme_request *req;
153 struct nvme_qpair *qpair;
154 sbintime_t deadline;
155 bus_dmamap_t payload_dma_map;
156 uint16_t cid;
157
158 uint64_t *prp;
159 bus_addr_t prp_bus_addr;
160 };
161
162 enum nvme_recovery {
163 RECOVERY_NONE = 0, /* Normal operations */
164 RECOVERY_START, /* Deadline has passed, start recovering */
165 RECOVERY_RESET, /* This pass, initiate reset of controller */
166 RECOVERY_WAITING, /* waiting for the reset to complete */
167 };
168 struct nvme_qpair {
169 struct nvme_controller *ctrlr;
170 uint32_t id;
171 int domain;
172 int cpu;
173
174 uint16_t vector;
175 int rid;
176 struct resource *res;
177 void *tag;
178
179 struct callout timer;
180 sbintime_t deadline;
181 bool timer_armed;
182 enum nvme_recovery recovery_state;
183
184 uint32_t num_entries;
185 uint32_t num_trackers;
186 uint32_t sq_tdbl_off;
187 uint32_t cq_hdbl_off;
188
189 uint32_t phase;
190 uint32_t sq_head;
191 uint32_t sq_tail;
192 uint32_t cq_head;
193
194 int64_t num_cmds;
195 int64_t num_intr_handler_calls;
196 int64_t num_retries;
197 int64_t num_failures;
198 int64_t num_ignored;
199
200 struct nvme_command *cmd;
201 struct nvme_completion *cpl;
202
203 bus_dma_tag_t dma_tag;
204 bus_dma_tag_t dma_tag_payload;
205
206 bus_dmamap_t queuemem_map;
207 uint64_t cmd_bus_addr;
208 uint64_t cpl_bus_addr;
209
210 TAILQ_HEAD(, nvme_tracker) free_tr;
211 TAILQ_HEAD(, nvme_tracker) outstanding_tr;
212 STAILQ_HEAD(, nvme_request) queued_req;
213
214 struct nvme_tracker **act_tr;
215
216 struct mtx lock __aligned(CACHE_LINE_SIZE);
217
218 } __aligned(CACHE_LINE_SIZE);
219
220 struct nvme_namespace {
221 struct nvme_controller *ctrlr;
222 struct nvme_namespace_data data;
223 uint32_t id;
224 uint32_t flags;
225 struct cdev *cdev;
226 void *cons_cookie[NVME_MAX_CONSUMERS];
227 uint32_t boundary;
228 struct mtx lock;
229 };
230
231 /*
232 * One of these per allocated PCI device.
233 */
234 struct nvme_controller {
235 device_t dev;
236
237 struct mtx lock;
238 int domain;
239 uint32_t ready_timeout_in_ms;
240 uint32_t quirks;
241 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */
242 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */
243 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */
244 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */
245
246 bus_space_tag_t bus_tag;
247 bus_space_handle_t bus_handle;
248 int resource_id;
249 struct resource *resource;
250
251 /*
252 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
253 * separate from the control registers which are in BAR 0/1. These
254 * members track the mapping of BAR 4/5 for that reason.
255 */
256 int bar4_resource_id;
257 struct resource *bar4_resource;
258
259 int msi_count;
260 uint32_t enable_aborts;
261
262 uint32_t num_io_queues;
263 uint32_t max_hw_pend_io;
264
265 /* Fields for tracking progress during controller initialization. */
266 struct intr_config_hook config_hook;
267 uint32_t ns_identified;
268 uint32_t queues_created;
269
270 struct task reset_task;
271 struct task fail_req_task;
272 struct taskqueue *taskqueue;
273
274 /* For shared legacy interrupt. */
275 int rid;
276 struct resource *res;
277 void *tag;
278
279 /** maximum i/o size in bytes */
280 uint32_t max_xfer_size;
281
282 /** minimum page size supported by this controller in bytes */
283 uint32_t min_page_size;
284
285 /** interrupt coalescing time period (in microseconds) */
286 uint32_t int_coal_time;
287
288 /** interrupt coalescing threshold */
289 uint32_t int_coal_threshold;
290
291 /** timeout period in seconds */
292 uint32_t timeout_period;
293
294 /** doorbell stride */
295 uint32_t dstrd;
296
297 struct nvme_qpair adminq;
298 struct nvme_qpair *ioq;
299
300 struct nvme_registers *regs;
301
302 struct nvme_controller_data cdata;
303 struct nvme_namespace ns[NVME_MAX_NAMESPACES];
304
305 struct cdev *cdev;
306
307 /** bit mask of event types currently enabled for async events */
308 uint32_t async_event_config;
309
310 uint32_t num_aers;
311 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
312
313 void *cons_cookie[NVME_MAX_CONSUMERS];
314
315 uint32_t is_resetting;
316 uint32_t is_initialized;
317 uint32_t notification_sent;
318
319 bool is_failed;
320 bool is_dying;
321 STAILQ_HEAD(, nvme_request) fail_req;
322
323 /* Host Memory Buffer */
324 int hmb_nchunks;
325 size_t hmb_chunk;
326 bus_dma_tag_t hmb_tag;
327 struct nvme_hmb_chunk {
328 bus_dmamap_t hmbc_map;
329 void *hmbc_vaddr;
330 uint64_t hmbc_paddr;
331 } *hmb_chunks;
332 bus_dma_tag_t hmb_desc_tag;
333 bus_dmamap_t hmb_desc_map;
334 struct nvme_hmb_desc *hmb_desc_vaddr;
335 uint64_t hmb_desc_paddr;
336 };
337
338 #define nvme_mmio_offsetof(reg) \
339 offsetof(struct nvme_registers, reg)
340
341 #define nvme_mmio_read_4(sc, reg) \
342 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
343 nvme_mmio_offsetof(reg))
344
345 #define nvme_mmio_write_4(sc, reg, val) \
346 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
347 nvme_mmio_offsetof(reg), val)
348
349 #define nvme_mmio_write_8(sc, reg, val) \
350 do { \
351 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
352 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
353 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
354 nvme_mmio_offsetof(reg)+4, \
355 (val & 0xFFFFFFFF00000000ULL) >> 32); \
356 } while (0);
357
358 #define nvme_printf(ctrlr, fmt, args...) \
359 device_printf(ctrlr->dev, fmt, ##args)
360
361 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
362
363 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
364 void *payload,
365 nvme_cb_fn_t cb_fn, void *cb_arg);
366 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
367 uint32_t nsid, void *payload,
368 nvme_cb_fn_t cb_fn, void *cb_arg);
369 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
370 uint32_t microseconds,
371 uint32_t threshold,
372 nvme_cb_fn_t cb_fn,
373 void *cb_arg);
374 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
375 struct nvme_error_information_entry *payload,
376 uint32_t num_entries, /* 0 = max */
377 nvme_cb_fn_t cb_fn,
378 void *cb_arg);
379 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
380 uint32_t nsid,
381 struct nvme_health_information_page *payload,
382 nvme_cb_fn_t cb_fn,
383 void *cb_arg);
384 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
385 struct nvme_firmware_page *payload,
386 nvme_cb_fn_t cb_fn,
387 void *cb_arg);
388 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
389 struct nvme_qpair *io_que,
390 nvme_cb_fn_t cb_fn, void *cb_arg);
391 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
392 struct nvme_qpair *io_que,
393 nvme_cb_fn_t cb_fn, void *cb_arg);
394 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
395 struct nvme_qpair *io_que,
396 nvme_cb_fn_t cb_fn, void *cb_arg);
397 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
398 struct nvme_qpair *io_que,
399 nvme_cb_fn_t cb_fn, void *cb_arg);
400 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
401 uint32_t num_queues, nvme_cb_fn_t cb_fn,
402 void *cb_arg);
403 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
404 uint32_t state,
405 nvme_cb_fn_t cb_fn, void *cb_arg);
406 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
407 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
408
409 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
410
411 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
412 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
413 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
414 void nvme_ctrlr_reset(struct nvme_controller *ctrlr);
415 /* ctrlr defined as void * to allow use with config_intrhook. */
416 void nvme_ctrlr_start_config_hook(void *ctrlr_arg);
417 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
418 struct nvme_request *req);
419 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
420 struct nvme_request *req);
421 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
422 struct nvme_request *req);
423
424 int nvme_qpair_construct(struct nvme_qpair *qpair,
425 uint32_t num_entries, uint32_t num_trackers,
426 struct nvme_controller *ctrlr);
427 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
428 struct nvme_tracker *tr);
429 bool nvme_qpair_process_completions(struct nvme_qpair *qpair);
430 void nvme_qpair_submit_request(struct nvme_qpair *qpair,
431 struct nvme_request *req);
432 void nvme_qpair_reset(struct nvme_qpair *qpair);
433 void nvme_qpair_fail(struct nvme_qpair *qpair);
434 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
435 struct nvme_request *req,
436 uint32_t sct, uint32_t sc);
437
438 void nvme_admin_qpair_enable(struct nvme_qpair *qpair);
439 void nvme_admin_qpair_disable(struct nvme_qpair *qpair);
440 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
441
442 void nvme_io_qpair_enable(struct nvme_qpair *qpair);
443 void nvme_io_qpair_disable(struct nvme_qpair *qpair);
444 void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
445
446 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id,
447 struct nvme_controller *ctrlr);
448 void nvme_ns_destruct(struct nvme_namespace *ns);
449
450 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
451
452 void nvme_dump_command(struct nvme_command *cmd);
453 void nvme_dump_completion(struct nvme_completion *cpl);
454
455 int nvme_attach(device_t dev);
456 int nvme_shutdown(device_t dev);
457 int nvme_detach(device_t dev);
458
459 /*
460 * Wait for a command to complete using the nvme_completion_poll_cb. Used in
461 * limited contexts where the caller knows it's OK to block briefly while the
462 * command runs. The ISR will run the callback which will set status->done to
463 * true, usually within microseconds. If not, then after one second timeout
464 * handler should reset the controller and abort all outstanding requests
465 * including this polled one. If still not after ten seconds, then something is
466 * wrong with the driver, and panic is the only way to recover.
467 *
468 * Most commands using this interface aren't actual I/O to the drive's media so
469 * complete within a few microseconds. Adaptively spin for one tick to catch the
470 * vast majority of these without waiting for a tick plus scheduling delays. Since
471 * these are on startup, this drastically reduces startup time.
472 */
473 static __inline
474 void
nvme_completion_poll(struct nvme_completion_poll_status * status)475 nvme_completion_poll(struct nvme_completion_poll_status *status)
476 {
477 int timeout = ticks + 10 * hz;
478 sbintime_t delta_t = SBT_1US;
479
480 while (!atomic_load_acq_int(&status->done)) {
481 if (timeout - ticks < 0)
482 panic("NVME polled command failed to complete within 10s.");
483 pause_sbt("nvme", delta_t, 0, C_PREL(1));
484 delta_t = min(SBT_1MS, delta_t * 3 / 2);
485 }
486 }
487
488 static __inline void
nvme_single_map(void * arg,bus_dma_segment_t * seg,int nseg,int error)489 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
490 {
491 uint64_t *bus_addr = (uint64_t *)arg;
492
493 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg));
494 if (error != 0)
495 printf("nvme_single_map err %d\n", error);
496 *bus_addr = seg[0].ds_addr;
497 }
498
499 static __inline struct nvme_request *
_nvme_allocate_request(nvme_cb_fn_t cb_fn,void * cb_arg)500 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg)
501 {
502 struct nvme_request *req;
503
504 req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO);
505 if (req != NULL) {
506 req->cb_fn = cb_fn;
507 req->cb_arg = cb_arg;
508 req->timeout = true;
509 }
510 return (req);
511 }
512
513 static __inline struct nvme_request *
nvme_allocate_request_vaddr(void * payload,uint32_t payload_size,nvme_cb_fn_t cb_fn,void * cb_arg)514 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
515 nvme_cb_fn_t cb_fn, void *cb_arg)
516 {
517 struct nvme_request *req;
518
519 req = _nvme_allocate_request(cb_fn, cb_arg);
520 if (req != NULL) {
521 req->type = NVME_REQUEST_VADDR;
522 req->u.payload = payload;
523 req->payload_size = payload_size;
524 }
525 return (req);
526 }
527
528 static __inline struct nvme_request *
nvme_allocate_request_null(nvme_cb_fn_t cb_fn,void * cb_arg)529 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
530 {
531 struct nvme_request *req;
532
533 req = _nvme_allocate_request(cb_fn, cb_arg);
534 if (req != NULL)
535 req->type = NVME_REQUEST_NULL;
536 return (req);
537 }
538
539 static __inline struct nvme_request *
nvme_allocate_request_bio(struct bio * bio,nvme_cb_fn_t cb_fn,void * cb_arg)540 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg)
541 {
542 struct nvme_request *req;
543
544 req = _nvme_allocate_request(cb_fn, cb_arg);
545 if (req != NULL) {
546 req->type = NVME_REQUEST_BIO;
547 req->u.bio = bio;
548 }
549 return (req);
550 }
551
552 static __inline struct nvme_request *
nvme_allocate_request_ccb(union ccb * ccb,nvme_cb_fn_t cb_fn,void * cb_arg)553 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg)
554 {
555 struct nvme_request *req;
556
557 req = _nvme_allocate_request(cb_fn, cb_arg);
558 if (req != NULL) {
559 req->type = NVME_REQUEST_CCB;
560 req->u.payload = ccb;
561 }
562
563 return (req);
564 }
565
566 #define nvme_free_request(req) free(req, M_NVME)
567
568 void nvme_notify_async_consumers(struct nvme_controller *ctrlr,
569 const struct nvme_completion *async_cpl,
570 uint32_t log_page_id, void *log_page_buffer,
571 uint32_t log_page_size);
572 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr);
573 void nvme_notify_new_controller(struct nvme_controller *ctrlr);
574 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid);
575
576 void nvme_ctrlr_shared_handler(void *arg);
577 void nvme_ctrlr_poll(struct nvme_controller *ctrlr);
578
579 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr);
580 int nvme_ctrlr_resume(struct nvme_controller *ctrlr);
581
582 #endif /* __NVME_PRIVATE_H__ */
583