1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2019 NXP 5 * 6 */ 7 8 #ifndef _DPAA2_HW_DPIO_H_ 9 #define _DPAA2_HW_DPIO_H_ 10 11 #include <mc/fsl_dpio.h> 12 #include <mc/fsl_mc_sys.h> 13 14 struct dpaa2_io_portal_t { 15 struct dpaa2_dpio_dev *dpio_dev; 16 struct dpaa2_dpio_dev *ethrx_dpio_dev; 17 }; 18 19 /*! Global per thread DPIO portal */ 20 RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); 21 22 #define DPAA2_PER_LCORE_DPIO RTE_PER_LCORE(_dpaa2_io).dpio_dev 23 #define DPAA2_PER_LCORE_PORTAL DPAA2_PER_LCORE_DPIO->sw_portal 24 25 #define DPAA2_PER_LCORE_ETHRX_DPIO RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev 26 #define DPAA2_PER_LCORE_ETHRX_PORTAL DPAA2_PER_LCORE_ETHRX_DPIO->sw_portal 27 28 #define DPAA2_PER_LCORE_DQRR_SIZE \ 29 RTE_PER_LCORE(_dpaa2_io).dpio_dev->dpaa2_held_bufs.dqrr_size 30 #define DPAA2_PER_LCORE_DQRR_HELD \ 31 RTE_PER_LCORE(_dpaa2_io).dpio_dev->dpaa2_held_bufs.dqrr_held 32 #define DPAA2_PER_LCORE_DQRR_MBUF(i) \ 33 RTE_PER_LCORE(_dpaa2_io).dpio_dev->dpaa2_held_bufs.mbuf[i] 34 35 /* Variable to store DPAA2 DQRR size */ 36 extern uint8_t dpaa2_dqrr_size; 37 /* Variable to store DPAA2 EQCR size */ 38 extern uint8_t dpaa2_eqcr_size; 39 40 extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE]; 41 42 /* Affine a DPIO portal to current processing thread */ 43 __rte_internal 44 int dpaa2_affine_qbman_swp(void); 45 46 /* Affine additional DPIO portal to current crypto processing thread */ 47 __rte_internal 48 int dpaa2_affine_qbman_ethrx_swp(void); 49 50 /* allocate memory for FQ - dq storage */ 51 __rte_internal 52 int 53 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage); 54 55 /* free memory for FQ- dq storage */ 56 __rte_internal 57 void 58 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage); 59 60 /* free the enqueue response descriptors */ 61 __rte_internal 62 uint32_t 63 dpaa2_free_eq_descriptors(void); 64 65 #endif /* _DPAA2_HW_DPIO_H_ */ 66