1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
3 */
4
5 #include <sys/queue.h>
6
7 #include <stdio.h>
8 #include <stdlib.h>
9 #include <string.h>
10 #include <errno.h>
11 #include <stdint.h>
12 #include <stdarg.h>
13 #include <inttypes.h>
14
15 #include <rte_interrupts.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_log.h>
19 #include <rte_debug.h>
20 #include <rte_pci.h>
21 #include <rte_bus_pci.h>
22 #include <rte_memory.h>
23 #include <rte_memcpy.h>
24 #include <rte_memzone.h>
25 #include <rte_launch.h>
26 #include <rte_eal.h>
27 #include <rte_per_lcore.h>
28 #include <rte_lcore.h>
29 #include <rte_atomic.h>
30 #include <rte_branch_prediction.h>
31 #include <rte_mempool.h>
32 #include <rte_malloc.h>
33 #include <rte_mbuf.h>
34 #include <rte_ether.h>
35 #include <ethdev_driver.h>
36 #include <rte_prefetch.h>
37 #include <rte_ip.h>
38 #include <rte_udp.h>
39 #include <rte_tcp.h>
40 #include <rte_sctp.h>
41 #include <rte_net.h>
42 #include <rte_string_fns.h>
43
44 #include "e1000_logs.h"
45 #include "base/e1000_api.h"
46 #include "e1000_ethdev.h"
47 #include "base/e1000_osdep.h"
48
49 #define E1000_TXD_VLAN_SHIFT 16
50
51 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
52
53 #define E1000_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_IPV6 | \
54 RTE_MBUF_F_TX_IPV4 | \
55 RTE_MBUF_F_TX_IP_CKSUM | \
56 RTE_MBUF_F_TX_L4_MASK | \
57 RTE_MBUF_F_TX_VLAN)
58
59 #define E1000_TX_OFFLOAD_NOTSUP_MASK \
60 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ E1000_TX_OFFLOAD_MASK)
61
62 /* PCI offset for querying configuration status register */
63 #define PCI_CFG_STATUS_REG 0x06
64 #define FLUSH_DESC_REQUIRED 0x100
65
66
67 /**
68 * Structure associated with each descriptor of the RX ring of a RX queue.
69 */
70 struct em_rx_entry {
71 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
72 };
73
74 /**
75 * Structure associated with each descriptor of the TX ring of a TX queue.
76 */
77 struct em_tx_entry {
78 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
79 uint16_t next_id; /**< Index of next descriptor in ring. */
80 uint16_t last_id; /**< Index of last scattered descriptor. */
81 };
82
83 /**
84 * Structure associated with each RX queue.
85 */
86 struct em_rx_queue {
87 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
88 volatile struct e1000_rx_desc *rx_ring; /**< RX ring virtual address. */
89 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
90 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
91 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
92 struct em_rx_entry *sw_ring; /**< address of RX software ring. */
93 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
94 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
95 uint64_t offloads; /**< Offloads of RTE_ETH_RX_OFFLOAD_* */
96 uint16_t nb_rx_desc; /**< number of RX descriptors. */
97 uint16_t rx_tail; /**< current value of RDT register. */
98 uint16_t nb_rx_hold; /**< number of held free RX desc. */
99 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
100 uint16_t queue_id; /**< RX queue index. */
101 uint16_t port_id; /**< Device port identifier. */
102 uint8_t pthresh; /**< Prefetch threshold register. */
103 uint8_t hthresh; /**< Host threshold register. */
104 uint8_t wthresh; /**< Write-back threshold register. */
105 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
106 const struct rte_memzone *mz;
107 };
108
109 /**
110 * Hardware context number
111 */
112 enum {
113 EM_CTX_0 = 0, /**< CTX0 */
114 EM_CTX_NUM = 1, /**< CTX NUM */
115 };
116
117 /** Offload features */
118 union em_vlan_macip {
119 uint32_t data;
120 struct {
121 uint16_t l3_len:9; /**< L3 (IP) Header Length. */
122 uint16_t l2_len:7; /**< L2 (MAC) Header Length. */
123 uint16_t vlan_tci;
124 /**< VLAN Tag Control Identifier (CPU order). */
125 } f;
126 };
127
128 /*
129 * Compare mask for vlan_macip_len.data,
130 * should be in sync with em_vlan_macip.f layout.
131 * */
132 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
133 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
134 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
135 /** MAC+IP length. */
136 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
137
138 /**
139 * Structure to check if new context need be built
140 */
141 struct em_ctx_info {
142 uint64_t flags; /**< ol_flags related to context build. */
143 uint32_t cmp_mask; /**< compare mask */
144 union em_vlan_macip hdrlen; /**< L2 and L3 header lengths */
145 };
146
147 /**
148 * Structure associated with each TX queue.
149 */
150 struct em_tx_queue {
151 volatile struct e1000_data_desc *tx_ring; /**< TX ring address */
152 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
153 struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */
154 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
155 uint16_t nb_tx_desc; /**< number of TX descriptors. */
156 uint16_t tx_tail; /**< Current value of TDT register. */
157 /**< Start freeing TX buffers if there are less free descriptors than
158 this value. */
159 uint16_t tx_free_thresh;
160 /**< Number of TX descriptors to use before RS bit is set. */
161 uint16_t tx_rs_thresh;
162 /** Number of TX descriptors used since RS bit was set. */
163 uint16_t nb_tx_used;
164 /** Index to last TX descriptor to have been cleaned. */
165 uint16_t last_desc_cleaned;
166 /** Total number of TX descriptors ready to be allocated. */
167 uint16_t nb_tx_free;
168 uint16_t queue_id; /**< TX queue index. */
169 uint16_t port_id; /**< Device port identifier. */
170 uint8_t pthresh; /**< Prefetch threshold register. */
171 uint8_t hthresh; /**< Host threshold register. */
172 uint8_t wthresh; /**< Write-back threshold register. */
173 struct em_ctx_info ctx_cache;
174 /**< Hardware context history.*/
175 uint64_t offloads; /**< offloads of RTE_ETH_TX_OFFLOAD_* */
176 const struct rte_memzone *mz;
177 };
178
179 #if 1
180 #define RTE_PMD_USE_PREFETCH
181 #endif
182
183 #ifdef RTE_PMD_USE_PREFETCH
184 #define rte_em_prefetch(p) rte_prefetch0(p)
185 #else
186 #define rte_em_prefetch(p) do {} while(0)
187 #endif
188
189 #ifdef RTE_PMD_PACKET_PREFETCH
190 #define rte_packet_prefetch(p) rte_prefetch1(p)
191 #else
192 #define rte_packet_prefetch(p) do {} while(0)
193 #endif
194
195 #ifndef DEFAULT_TX_FREE_THRESH
196 #define DEFAULT_TX_FREE_THRESH 32
197 #endif /* DEFAULT_TX_FREE_THRESH */
198
199 #ifndef DEFAULT_TX_RS_THRESH
200 #define DEFAULT_TX_RS_THRESH 32
201 #endif /* DEFAULT_TX_RS_THRESH */
202
203
204 /*********************************************************************
205 *
206 * TX function
207 *
208 **********************************************************************/
209
210 /*
211 * Populates TX context descriptor.
212 */
213 static inline void
em_set_xmit_ctx(struct em_tx_queue * txq,volatile struct e1000_context_desc * ctx_txd,uint64_t flags,union em_vlan_macip hdrlen)214 em_set_xmit_ctx(struct em_tx_queue* txq,
215 volatile struct e1000_context_desc *ctx_txd,
216 uint64_t flags,
217 union em_vlan_macip hdrlen)
218 {
219 uint32_t cmp_mask, cmd_len;
220 uint16_t ipcse, l2len;
221 struct e1000_context_desc ctx;
222
223 cmp_mask = 0;
224 cmd_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C;
225
226 l2len = hdrlen.f.l2_len;
227 ipcse = (uint16_t)(l2len + hdrlen.f.l3_len);
228
229 /* setup IPCS* fields */
230 ctx.lower_setup.ip_fields.ipcss = (uint8_t)l2len;
231 ctx.lower_setup.ip_fields.ipcso = (uint8_t)(l2len +
232 offsetof(struct rte_ipv4_hdr, hdr_checksum));
233
234 /*
235 * When doing checksum or TCP segmentation with IPv6 headers,
236 * IPCSE field should be set t0 0.
237 */
238 if (flags & RTE_MBUF_F_TX_IP_CKSUM) {
239 ctx.lower_setup.ip_fields.ipcse =
240 (uint16_t)rte_cpu_to_le_16(ipcse - 1);
241 cmd_len |= E1000_TXD_CMD_IP;
242 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
243 } else {
244 ctx.lower_setup.ip_fields.ipcse = 0;
245 }
246
247 /* setup TUCS* fields */
248 ctx.upper_setup.tcp_fields.tucss = (uint8_t)ipcse;
249 ctx.upper_setup.tcp_fields.tucse = 0;
250
251 switch (flags & RTE_MBUF_F_TX_L4_MASK) {
252 case RTE_MBUF_F_TX_UDP_CKSUM:
253 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
254 offsetof(struct rte_udp_hdr, dgram_cksum));
255 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
256 break;
257 case RTE_MBUF_F_TX_TCP_CKSUM:
258 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
259 offsetof(struct rte_tcp_hdr, cksum));
260 cmd_len |= E1000_TXD_CMD_TCP;
261 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
262 break;
263 default:
264 ctx.upper_setup.tcp_fields.tucso = 0;
265 }
266
267 ctx.cmd_and_length = rte_cpu_to_le_32(cmd_len);
268 ctx.tcp_seg_setup.data = 0;
269
270 *ctx_txd = ctx;
271
272 txq->ctx_cache.flags = flags;
273 txq->ctx_cache.cmp_mask = cmp_mask;
274 txq->ctx_cache.hdrlen = hdrlen;
275 }
276
277 /*
278 * Check which hardware context can be used. Use the existing match
279 * or create a new context descriptor.
280 */
281 static inline uint32_t
what_ctx_update(struct em_tx_queue * txq,uint64_t flags,union em_vlan_macip hdrlen)282 what_ctx_update(struct em_tx_queue *txq, uint64_t flags,
283 union em_vlan_macip hdrlen)
284 {
285 /* If match with the current context */
286 if (likely (txq->ctx_cache.flags == flags &&
287 ((txq->ctx_cache.hdrlen.data ^ hdrlen.data) &
288 txq->ctx_cache.cmp_mask) == 0))
289 return EM_CTX_0;
290
291 /* Mismatch */
292 return EM_CTX_NUM;
293 }
294
295 /* Reset transmit descriptors after they have been used */
296 static inline int
em_xmit_cleanup(struct em_tx_queue * txq)297 em_xmit_cleanup(struct em_tx_queue *txq)
298 {
299 struct em_tx_entry *sw_ring = txq->sw_ring;
300 volatile struct e1000_data_desc *txr = txq->tx_ring;
301 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
302 uint16_t nb_tx_desc = txq->nb_tx_desc;
303 uint16_t desc_to_clean_to;
304 uint16_t nb_tx_to_clean;
305
306 /* Determine the last descriptor needing to be cleaned */
307 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
308 if (desc_to_clean_to >= nb_tx_desc)
309 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
310
311 /* Check to make sure the last descriptor to clean is done */
312 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
313 if (! (txr[desc_to_clean_to].upper.fields.status & E1000_TXD_STAT_DD))
314 {
315 PMD_TX_LOG(DEBUG,
316 "TX descriptor %4u is not done"
317 "(port=%d queue=%d)", desc_to_clean_to,
318 txq->port_id, txq->queue_id);
319 /* Failed to clean any descriptors, better luck next time */
320 return -(1);
321 }
322
323 /* Figure out how many descriptors will be cleaned */
324 if (last_desc_cleaned > desc_to_clean_to)
325 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
326 desc_to_clean_to);
327 else
328 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
329 last_desc_cleaned);
330
331 PMD_TX_LOG(DEBUG,
332 "Cleaning %4u TX descriptors: %4u to %4u "
333 "(port=%d queue=%d)", nb_tx_to_clean,
334 last_desc_cleaned, desc_to_clean_to, txq->port_id,
335 txq->queue_id);
336
337 /*
338 * The last descriptor to clean is done, so that means all the
339 * descriptors from the last descriptor that was cleaned
340 * up to the last descriptor with the RS bit set
341 * are done. Only reset the threshold descriptor.
342 */
343 txr[desc_to_clean_to].upper.fields.status = 0;
344
345 /* Update the txq to reflect the last descriptor that was cleaned */
346 txq->last_desc_cleaned = desc_to_clean_to;
347 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
348
349 /* No Error */
350 return 0;
351 }
352
353 static inline uint32_t
tx_desc_cksum_flags_to_upper(uint64_t ol_flags)354 tx_desc_cksum_flags_to_upper(uint64_t ol_flags)
355 {
356 static const uint32_t l4_olinfo[2] = {0, E1000_TXD_POPTS_TXSM << 8};
357 static const uint32_t l3_olinfo[2] = {0, E1000_TXD_POPTS_IXSM << 8};
358 uint32_t tmp;
359
360 tmp = l4_olinfo[(ol_flags & RTE_MBUF_F_TX_L4_MASK) != RTE_MBUF_F_TX_L4_NO_CKSUM];
361 tmp |= l3_olinfo[(ol_flags & RTE_MBUF_F_TX_IP_CKSUM) != 0];
362 return tmp;
363 }
364
365 uint16_t
eth_em_xmit_pkts(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)366 eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
367 uint16_t nb_pkts)
368 {
369 struct em_tx_queue *txq;
370 struct em_tx_entry *sw_ring;
371 struct em_tx_entry *txe, *txn;
372 volatile struct e1000_data_desc *txr;
373 volatile struct e1000_data_desc *txd;
374 struct rte_mbuf *tx_pkt;
375 struct rte_mbuf *m_seg;
376 uint64_t buf_dma_addr;
377 uint32_t popts_spec;
378 uint32_t cmd_type_len;
379 uint16_t slen;
380 uint64_t ol_flags;
381 uint16_t tx_id;
382 uint16_t tx_last;
383 uint16_t nb_tx;
384 uint16_t nb_used;
385 uint64_t tx_ol_req;
386 uint32_t ctx;
387 uint32_t new_ctx;
388 union em_vlan_macip hdrlen;
389
390 txq = tx_queue;
391 sw_ring = txq->sw_ring;
392 txr = txq->tx_ring;
393 tx_id = txq->tx_tail;
394 txe = &sw_ring[tx_id];
395
396 /* Determine if the descriptor ring needs to be cleaned. */
397 if (txq->nb_tx_free < txq->tx_free_thresh)
398 em_xmit_cleanup(txq);
399
400 /* TX loop */
401 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
402 new_ctx = 0;
403 tx_pkt = *tx_pkts++;
404
405 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
406
407 /*
408 * Determine how many (if any) context descriptors
409 * are needed for offload functionality.
410 */
411 ol_flags = tx_pkt->ol_flags;
412
413 /* If hardware offload required */
414 tx_ol_req = (ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK));
415 if (tx_ol_req) {
416 hdrlen.f.vlan_tci = tx_pkt->vlan_tci;
417 hdrlen.f.l2_len = tx_pkt->l2_len;
418 hdrlen.f.l3_len = tx_pkt->l3_len;
419 /* If new context to be built or reuse the exist ctx. */
420 ctx = what_ctx_update(txq, tx_ol_req, hdrlen);
421
422 /* Only allocate context descriptor if required*/
423 new_ctx = (ctx == EM_CTX_NUM);
424 }
425
426 /*
427 * Keep track of how many descriptors are used this loop
428 * This will always be the number of segments + the number of
429 * Context descriptors required to transmit the packet
430 */
431 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
432
433 /*
434 * The number of descriptors that must be allocated for a
435 * packet is the number of segments of that packet, plus 1
436 * Context Descriptor for the hardware offload, if any.
437 * Determine the last TX descriptor to allocate in the TX ring
438 * for the packet, starting from the current position (tx_id)
439 * in the ring.
440 */
441 tx_last = (uint16_t) (tx_id + nb_used - 1);
442
443 /* Circular ring */
444 if (tx_last >= txq->nb_tx_desc)
445 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
446
447 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
448 " tx_first=%u tx_last=%u",
449 (unsigned) txq->port_id,
450 (unsigned) txq->queue_id,
451 (unsigned) tx_pkt->pkt_len,
452 (unsigned) tx_id,
453 (unsigned) tx_last);
454
455 /*
456 * Make sure there are enough TX descriptors available to
457 * transmit the entire packet.
458 * nb_used better be less than or equal to txq->tx_rs_thresh
459 */
460 while (unlikely (nb_used > txq->nb_tx_free)) {
461 PMD_TX_LOG(DEBUG, "Not enough free TX descriptors "
462 "nb_used=%4u nb_free=%4u "
463 "(port=%d queue=%d)",
464 nb_used, txq->nb_tx_free,
465 txq->port_id, txq->queue_id);
466
467 if (em_xmit_cleanup(txq) != 0) {
468 /* Could not clean any descriptors */
469 if (nb_tx == 0)
470 return 0;
471 goto end_of_tx;
472 }
473 }
474
475 /*
476 * By now there are enough free TX descriptors to transmit
477 * the packet.
478 */
479
480 /*
481 * Set common flags of all TX Data Descriptors.
482 *
483 * The following bits must be set in all Data Descriptors:
484 * - E1000_TXD_DTYP_DATA
485 * - E1000_TXD_DTYP_DEXT
486 *
487 * The following bits must be set in the first Data Descriptor
488 * and are ignored in the other ones:
489 * - E1000_TXD_POPTS_IXSM
490 * - E1000_TXD_POPTS_TXSM
491 *
492 * The following bits must be set in the last Data Descriptor
493 * and are ignored in the other ones:
494 * - E1000_TXD_CMD_VLE
495 * - E1000_TXD_CMD_IFCS
496 *
497 * The following bits must only be set in the last Data
498 * Descriptor:
499 * - E1000_TXD_CMD_EOP
500 *
501 * The following bits can be set in any Data Descriptor, but
502 * are only set in the last Data Descriptor:
503 * - E1000_TXD_CMD_RS
504 */
505 cmd_type_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
506 E1000_TXD_CMD_IFCS;
507 popts_spec = 0;
508
509 /* Set VLAN Tag offload fields. */
510 if (ol_flags & RTE_MBUF_F_TX_VLAN) {
511 cmd_type_len |= E1000_TXD_CMD_VLE;
512 popts_spec = tx_pkt->vlan_tci << E1000_TXD_VLAN_SHIFT;
513 }
514
515 if (tx_ol_req) {
516 /*
517 * Setup the TX Context Descriptor if required
518 */
519 if (new_ctx) {
520 volatile struct e1000_context_desc *ctx_txd;
521
522 ctx_txd = (volatile struct e1000_context_desc *)
523 &txr[tx_id];
524
525 txn = &sw_ring[txe->next_id];
526 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
527
528 if (txe->mbuf != NULL) {
529 rte_pktmbuf_free_seg(txe->mbuf);
530 txe->mbuf = NULL;
531 }
532
533 em_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
534 hdrlen);
535
536 txe->last_id = tx_last;
537 tx_id = txe->next_id;
538 txe = txn;
539 }
540
541 /*
542 * Setup the TX Data Descriptor,
543 * This path will go through
544 * whatever new/reuse the context descriptor
545 */
546 popts_spec |= tx_desc_cksum_flags_to_upper(ol_flags);
547 }
548
549 m_seg = tx_pkt;
550 do {
551 txd = &txr[tx_id];
552 txn = &sw_ring[txe->next_id];
553
554 if (txe->mbuf != NULL)
555 rte_pktmbuf_free_seg(txe->mbuf);
556 txe->mbuf = m_seg;
557
558 /*
559 * Set up Transmit Data Descriptor.
560 */
561 slen = m_seg->data_len;
562 buf_dma_addr = rte_mbuf_data_iova(m_seg);
563
564 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
565 txd->lower.data = rte_cpu_to_le_32(cmd_type_len | slen);
566 txd->upper.data = rte_cpu_to_le_32(popts_spec);
567
568 txe->last_id = tx_last;
569 tx_id = txe->next_id;
570 txe = txn;
571 m_seg = m_seg->next;
572 } while (m_seg != NULL);
573
574 /*
575 * The last packet data descriptor needs End Of Packet (EOP)
576 */
577 cmd_type_len |= E1000_TXD_CMD_EOP;
578 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
579 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
580
581 /* Set RS bit only on threshold packets' last descriptor */
582 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
583 PMD_TX_LOG(DEBUG,
584 "Setting RS bit on TXD id=%4u "
585 "(port=%d queue=%d)",
586 tx_last, txq->port_id, txq->queue_id);
587
588 cmd_type_len |= E1000_TXD_CMD_RS;
589
590 /* Update txq RS bit counters */
591 txq->nb_tx_used = 0;
592 }
593 txd->lower.data |= rte_cpu_to_le_32(cmd_type_len);
594 }
595 end_of_tx:
596 rte_wmb();
597
598 /*
599 * Set the Transmit Descriptor Tail (TDT)
600 */
601 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
602 (unsigned) txq->port_id, (unsigned) txq->queue_id,
603 (unsigned) tx_id, (unsigned) nb_tx);
604 E1000_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
605 txq->tx_tail = tx_id;
606
607 return nb_tx;
608 }
609
610 /*********************************************************************
611 *
612 * TX prep functions
613 *
614 **********************************************************************/
615 uint16_t
eth_em_prep_pkts(__rte_unused void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)616 eth_em_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
617 uint16_t nb_pkts)
618 {
619 int i, ret;
620 struct rte_mbuf *m;
621
622 for (i = 0; i < nb_pkts; i++) {
623 m = tx_pkts[i];
624
625 if (m->ol_flags & E1000_TX_OFFLOAD_NOTSUP_MASK) {
626 rte_errno = ENOTSUP;
627 return i;
628 }
629
630 #ifdef RTE_ETHDEV_DEBUG_TX
631 ret = rte_validate_tx_offload(m);
632 if (ret != 0) {
633 rte_errno = -ret;
634 return i;
635 }
636 #endif
637 ret = rte_net_intel_cksum_prepare(m);
638 if (ret != 0) {
639 rte_errno = -ret;
640 return i;
641 }
642 }
643
644 return i;
645 }
646
647 /*********************************************************************
648 *
649 * RX functions
650 *
651 **********************************************************************/
652
653 static inline uint64_t
rx_desc_status_to_pkt_flags(uint32_t rx_status)654 rx_desc_status_to_pkt_flags(uint32_t rx_status)
655 {
656 uint64_t pkt_flags;
657
658 /* Check if VLAN present */
659 pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ?
660 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED : 0);
661
662 return pkt_flags;
663 }
664
665 static inline uint64_t
rx_desc_error_to_pkt_flags(uint32_t rx_error)666 rx_desc_error_to_pkt_flags(uint32_t rx_error)
667 {
668 uint64_t pkt_flags = 0;
669
670 if (rx_error & E1000_RXD_ERR_IPE)
671 pkt_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
672 if (rx_error & E1000_RXD_ERR_TCPE)
673 pkt_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
674 return pkt_flags;
675 }
676
677 uint16_t
eth_em_recv_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)678 eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
679 uint16_t nb_pkts)
680 {
681 volatile struct e1000_rx_desc *rx_ring;
682 volatile struct e1000_rx_desc *rxdp;
683 struct em_rx_queue *rxq;
684 struct em_rx_entry *sw_ring;
685 struct em_rx_entry *rxe;
686 struct rte_mbuf *rxm;
687 struct rte_mbuf *nmb;
688 struct e1000_rx_desc rxd;
689 uint64_t dma_addr;
690 uint16_t pkt_len;
691 uint16_t rx_id;
692 uint16_t nb_rx;
693 uint16_t nb_hold;
694 uint8_t status;
695
696 rxq = rx_queue;
697
698 nb_rx = 0;
699 nb_hold = 0;
700 rx_id = rxq->rx_tail;
701 rx_ring = rxq->rx_ring;
702 sw_ring = rxq->sw_ring;
703 while (nb_rx < nb_pkts) {
704 /*
705 * The order of operations here is important as the DD status
706 * bit must not be read after any other descriptor fields.
707 * rx_ring and rxdp are pointing to volatile data so the order
708 * of accesses cannot be reordered by the compiler. If they were
709 * not volatile, they could be reordered which could lead to
710 * using invalid descriptor fields when read from rxd.
711 */
712 rxdp = &rx_ring[rx_id];
713 status = rxdp->status;
714 if (! (status & E1000_RXD_STAT_DD))
715 break;
716 rxd = *rxdp;
717
718 /*
719 * End of packet.
720 *
721 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
722 * likely to be invalid and to be dropped by the various
723 * validation checks performed by the network stack.
724 *
725 * Allocate a new mbuf to replenish the RX ring descriptor.
726 * If the allocation fails:
727 * - arrange for that RX descriptor to be the first one
728 * being parsed the next time the receive function is
729 * invoked [on the same queue].
730 *
731 * - Stop parsing the RX ring and return immediately.
732 *
733 * This policy do not drop the packet received in the RX
734 * descriptor for which the allocation of a new mbuf failed.
735 * Thus, it allows that packet to be later retrieved if
736 * mbuf have been freed in the mean time.
737 * As a side effect, holding RX descriptors instead of
738 * systematically giving them back to the NIC may lead to
739 * RX ring exhaustion situations.
740 * However, the NIC can gracefully prevent such situations
741 * to happen by sending specific "back-pressure" flow control
742 * frames to its peer(s).
743 */
744 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
745 "status=0x%x pkt_len=%u",
746 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
747 (unsigned) rx_id, (unsigned) status,
748 (unsigned) rte_le_to_cpu_16(rxd.length));
749
750 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
751 if (nmb == NULL) {
752 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
753 "queue_id=%u",
754 (unsigned) rxq->port_id,
755 (unsigned) rxq->queue_id);
756 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
757 break;
758 }
759
760 nb_hold++;
761 rxe = &sw_ring[rx_id];
762 rx_id++;
763 if (rx_id == rxq->nb_rx_desc)
764 rx_id = 0;
765
766 /* Prefetch next mbuf while processing current one. */
767 rte_em_prefetch(sw_ring[rx_id].mbuf);
768
769 /*
770 * When next RX descriptor is on a cache-line boundary,
771 * prefetch the next 4 RX descriptors and the next 8 pointers
772 * to mbufs.
773 */
774 if ((rx_id & 0x3) == 0) {
775 rte_em_prefetch(&rx_ring[rx_id]);
776 rte_em_prefetch(&sw_ring[rx_id]);
777 }
778
779 /* Rearm RXD: attach new mbuf and reset status to zero. */
780
781 rxm = rxe->mbuf;
782 rxe->mbuf = nmb;
783 dma_addr =
784 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
785 rxdp->buffer_addr = dma_addr;
786 rxdp->status = 0;
787
788 /*
789 * Initialize the returned mbuf.
790 * 1) setup generic mbuf fields:
791 * - number of segments,
792 * - next segment,
793 * - packet length,
794 * - RX port identifier.
795 * 2) integrate hardware offload data, if any:
796 * - RSS flag & hash,
797 * - IP checksum flag,
798 * - VLAN TCI, if any,
799 * - error flags.
800 */
801 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.length) -
802 rxq->crc_len);
803 rxm->data_off = RTE_PKTMBUF_HEADROOM;
804 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
805 rxm->nb_segs = 1;
806 rxm->next = NULL;
807 rxm->pkt_len = pkt_len;
808 rxm->data_len = pkt_len;
809 rxm->port = rxq->port_id;
810
811 rxm->ol_flags = rx_desc_status_to_pkt_flags(status);
812 rxm->ol_flags = rxm->ol_flags |
813 rx_desc_error_to_pkt_flags(rxd.errors);
814
815 /* Only valid if RTE_MBUF_F_RX_VLAN set in pkt_flags */
816 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
817
818 /*
819 * Store the mbuf address into the next entry of the array
820 * of returned packets.
821 */
822 rx_pkts[nb_rx++] = rxm;
823 }
824 rxq->rx_tail = rx_id;
825
826 /*
827 * If the number of free RX descriptors is greater than the RX free
828 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
829 * register.
830 * Update the RDT with the value of the last processed RX descriptor
831 * minus 1, to guarantee that the RDT register is never equal to the
832 * RDH register, which creates a "full" ring situation from the
833 * hardware point of view...
834 */
835 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
836 if (nb_hold > rxq->rx_free_thresh) {
837 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
838 "nb_hold=%u nb_rx=%u",
839 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
840 (unsigned) rx_id, (unsigned) nb_hold,
841 (unsigned) nb_rx);
842 rx_id = (uint16_t) ((rx_id == 0) ?
843 (rxq->nb_rx_desc - 1) : (rx_id - 1));
844 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
845 nb_hold = 0;
846 }
847 rxq->nb_rx_hold = nb_hold;
848 return nb_rx;
849 }
850
851 uint16_t
eth_em_recv_scattered_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)852 eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
853 uint16_t nb_pkts)
854 {
855 struct em_rx_queue *rxq;
856 volatile struct e1000_rx_desc *rx_ring;
857 volatile struct e1000_rx_desc *rxdp;
858 struct em_rx_entry *sw_ring;
859 struct em_rx_entry *rxe;
860 struct rte_mbuf *first_seg;
861 struct rte_mbuf *last_seg;
862 struct rte_mbuf *rxm;
863 struct rte_mbuf *nmb;
864 struct e1000_rx_desc rxd;
865 uint64_t dma; /* Physical address of mbuf data buffer */
866 uint16_t rx_id;
867 uint16_t nb_rx;
868 uint16_t nb_hold;
869 uint16_t data_len;
870 uint8_t status;
871
872 rxq = rx_queue;
873
874 nb_rx = 0;
875 nb_hold = 0;
876 rx_id = rxq->rx_tail;
877 rx_ring = rxq->rx_ring;
878 sw_ring = rxq->sw_ring;
879
880 /*
881 * Retrieve RX context of current packet, if any.
882 */
883 first_seg = rxq->pkt_first_seg;
884 last_seg = rxq->pkt_last_seg;
885
886 while (nb_rx < nb_pkts) {
887 next_desc:
888 /*
889 * The order of operations here is important as the DD status
890 * bit must not be read after any other descriptor fields.
891 * rx_ring and rxdp are pointing to volatile data so the order
892 * of accesses cannot be reordered by the compiler. If they were
893 * not volatile, they could be reordered which could lead to
894 * using invalid descriptor fields when read from rxd.
895 */
896 rxdp = &rx_ring[rx_id];
897 status = rxdp->status;
898 if (! (status & E1000_RXD_STAT_DD))
899 break;
900 rxd = *rxdp;
901
902 /*
903 * Descriptor done.
904 *
905 * Allocate a new mbuf to replenish the RX ring descriptor.
906 * If the allocation fails:
907 * - arrange for that RX descriptor to be the first one
908 * being parsed the next time the receive function is
909 * invoked [on the same queue].
910 *
911 * - Stop parsing the RX ring and return immediately.
912 *
913 * This policy does not drop the packet received in the RX
914 * descriptor for which the allocation of a new mbuf failed.
915 * Thus, it allows that packet to be later retrieved if
916 * mbuf have been freed in the mean time.
917 * As a side effect, holding RX descriptors instead of
918 * systematically giving them back to the NIC may lead to
919 * RX ring exhaustion situations.
920 * However, the NIC can gracefully prevent such situations
921 * to happen by sending specific "back-pressure" flow control
922 * frames to its peer(s).
923 */
924 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
925 "status=0x%x data_len=%u",
926 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
927 (unsigned) rx_id, (unsigned) status,
928 (unsigned) rte_le_to_cpu_16(rxd.length));
929
930 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
931 if (nmb == NULL) {
932 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
933 "queue_id=%u", (unsigned) rxq->port_id,
934 (unsigned) rxq->queue_id);
935 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
936 break;
937 }
938
939 nb_hold++;
940 rxe = &sw_ring[rx_id];
941 rx_id++;
942 if (rx_id == rxq->nb_rx_desc)
943 rx_id = 0;
944
945 /* Prefetch next mbuf while processing current one. */
946 rte_em_prefetch(sw_ring[rx_id].mbuf);
947
948 /*
949 * When next RX descriptor is on a cache-line boundary,
950 * prefetch the next 4 RX descriptors and the next 8 pointers
951 * to mbufs.
952 */
953 if ((rx_id & 0x3) == 0) {
954 rte_em_prefetch(&rx_ring[rx_id]);
955 rte_em_prefetch(&sw_ring[rx_id]);
956 }
957
958 /*
959 * Update RX descriptor with the physical address of the new
960 * data buffer of the new allocated mbuf.
961 */
962 rxm = rxe->mbuf;
963 rxe->mbuf = nmb;
964 dma = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
965 rxdp->buffer_addr = dma;
966 rxdp->status = 0;
967
968 /*
969 * Set data length & data buffer address of mbuf.
970 */
971 data_len = rte_le_to_cpu_16(rxd.length);
972 rxm->data_len = data_len;
973 rxm->data_off = RTE_PKTMBUF_HEADROOM;
974
975 /*
976 * If this is the first buffer of the received packet,
977 * set the pointer to the first mbuf of the packet and
978 * initialize its context.
979 * Otherwise, update the total length and the number of segments
980 * of the current scattered packet, and update the pointer to
981 * the last mbuf of the current packet.
982 */
983 if (first_seg == NULL) {
984 first_seg = rxm;
985 first_seg->pkt_len = data_len;
986 first_seg->nb_segs = 1;
987 } else {
988 first_seg->pkt_len += data_len;
989 first_seg->nb_segs++;
990 last_seg->next = rxm;
991 }
992
993 /*
994 * If this is not the last buffer of the received packet,
995 * update the pointer to the last mbuf of the current scattered
996 * packet and continue to parse the RX ring.
997 */
998 if (! (status & E1000_RXD_STAT_EOP)) {
999 last_seg = rxm;
1000 goto next_desc;
1001 }
1002
1003 /*
1004 * This is the last buffer of the received packet.
1005 * If the CRC is not stripped by the hardware:
1006 * - Subtract the CRC length from the total packet length.
1007 * - If the last buffer only contains the whole CRC or a part
1008 * of it, free the mbuf associated to the last buffer.
1009 * If part of the CRC is also contained in the previous
1010 * mbuf, subtract the length of that CRC part from the
1011 * data length of the previous mbuf.
1012 */
1013 rxm->next = NULL;
1014 if (unlikely(rxq->crc_len > 0)) {
1015 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1016 if (data_len <= RTE_ETHER_CRC_LEN) {
1017 rte_pktmbuf_free_seg(rxm);
1018 first_seg->nb_segs--;
1019 last_seg->data_len = (uint16_t)
1020 (last_seg->data_len -
1021 (RTE_ETHER_CRC_LEN - data_len));
1022 last_seg->next = NULL;
1023 } else
1024 rxm->data_len = (uint16_t)
1025 (data_len - RTE_ETHER_CRC_LEN);
1026 }
1027
1028 /*
1029 * Initialize the first mbuf of the returned packet:
1030 * - RX port identifier,
1031 * - hardware offload data, if any:
1032 * - IP checksum flag,
1033 * - error flags.
1034 */
1035 first_seg->port = rxq->port_id;
1036
1037 first_seg->ol_flags = rx_desc_status_to_pkt_flags(status);
1038 first_seg->ol_flags = first_seg->ol_flags |
1039 rx_desc_error_to_pkt_flags(rxd.errors);
1040
1041 /* Only valid if RTE_MBUF_F_RX_VLAN set in pkt_flags */
1042 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
1043
1044 /* Prefetch data of first segment, if configured to do so. */
1045 rte_packet_prefetch((char *)first_seg->buf_addr +
1046 first_seg->data_off);
1047
1048 /*
1049 * Store the mbuf address into the next entry of the array
1050 * of returned packets.
1051 */
1052 rx_pkts[nb_rx++] = first_seg;
1053
1054 /*
1055 * Setup receipt context for a new packet.
1056 */
1057 first_seg = NULL;
1058 }
1059
1060 /*
1061 * Record index of the next RX descriptor to probe.
1062 */
1063 rxq->rx_tail = rx_id;
1064
1065 /*
1066 * Save receive context.
1067 */
1068 rxq->pkt_first_seg = first_seg;
1069 rxq->pkt_last_seg = last_seg;
1070
1071 /*
1072 * If the number of free RX descriptors is greater than the RX free
1073 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1074 * register.
1075 * Update the RDT with the value of the last processed RX descriptor
1076 * minus 1, to guarantee that the RDT register is never equal to the
1077 * RDH register, which creates a "full" ring situation from the
1078 * hardware point of view...
1079 */
1080 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1081 if (nb_hold > rxq->rx_free_thresh) {
1082 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1083 "nb_hold=%u nb_rx=%u",
1084 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1085 (unsigned) rx_id, (unsigned) nb_hold,
1086 (unsigned) nb_rx);
1087 rx_id = (uint16_t) ((rx_id == 0) ?
1088 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1089 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1090 nb_hold = 0;
1091 }
1092 rxq->nb_rx_hold = nb_hold;
1093 return nb_rx;
1094 }
1095
1096 #define EM_MAX_BUF_SIZE 16384
1097 #define EM_RCTL_FLXBUF_STEP 1024
1098
1099 static void
em_tx_queue_release_mbufs(struct em_tx_queue * txq)1100 em_tx_queue_release_mbufs(struct em_tx_queue *txq)
1101 {
1102 unsigned i;
1103
1104 if (txq->sw_ring != NULL) {
1105 for (i = 0; i != txq->nb_tx_desc; i++) {
1106 if (txq->sw_ring[i].mbuf != NULL) {
1107 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1108 txq->sw_ring[i].mbuf = NULL;
1109 }
1110 }
1111 }
1112 }
1113
1114 static void
em_tx_queue_release(struct em_tx_queue * txq)1115 em_tx_queue_release(struct em_tx_queue *txq)
1116 {
1117 if (txq != NULL) {
1118 em_tx_queue_release_mbufs(txq);
1119 rte_free(txq->sw_ring);
1120 rte_memzone_free(txq->mz);
1121 rte_free(txq);
1122 }
1123 }
1124
1125 void
eth_em_tx_queue_release(struct rte_eth_dev * dev,uint16_t qid)1126 eth_em_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1127 {
1128 em_tx_queue_release(dev->data->tx_queues[qid]);
1129 }
1130
1131 /* (Re)set dynamic em_tx_queue fields to defaults */
1132 static void
em_reset_tx_queue(struct em_tx_queue * txq)1133 em_reset_tx_queue(struct em_tx_queue *txq)
1134 {
1135 uint16_t i, nb_desc, prev;
1136 static const struct e1000_data_desc txd_init = {
1137 .upper.fields = {.status = E1000_TXD_STAT_DD},
1138 };
1139
1140 nb_desc = txq->nb_tx_desc;
1141
1142 /* Initialize ring entries */
1143
1144 prev = (uint16_t) (nb_desc - 1);
1145
1146 for (i = 0; i < nb_desc; i++) {
1147 txq->tx_ring[i] = txd_init;
1148 txq->sw_ring[i].mbuf = NULL;
1149 txq->sw_ring[i].last_id = i;
1150 txq->sw_ring[prev].next_id = i;
1151 prev = i;
1152 }
1153
1154 /*
1155 * Always allow 1 descriptor to be un-allocated to avoid
1156 * a H/W race condition
1157 */
1158 txq->nb_tx_free = (uint16_t)(nb_desc - 1);
1159 txq->last_desc_cleaned = (uint16_t)(nb_desc - 1);
1160 txq->nb_tx_used = 0;
1161 txq->tx_tail = 0;
1162
1163 memset((void*)&txq->ctx_cache, 0, sizeof (txq->ctx_cache));
1164 }
1165
1166 uint64_t
em_get_tx_port_offloads_capa(struct rte_eth_dev * dev)1167 em_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1168 {
1169 uint64_t tx_offload_capa;
1170
1171 RTE_SET_USED(dev);
1172 tx_offload_capa =
1173 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
1174 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
1175 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
1176 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
1177 RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
1178
1179 return tx_offload_capa;
1180 }
1181
1182 uint64_t
em_get_tx_queue_offloads_capa(struct rte_eth_dev * dev)1183 em_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1184 {
1185 uint64_t tx_queue_offload_capa;
1186
1187 /*
1188 * As only one Tx queue can be used, let per queue offloading
1189 * capability be same to per port queue offloading capability
1190 * for better convenience.
1191 */
1192 tx_queue_offload_capa = em_get_tx_port_offloads_capa(dev);
1193
1194 return tx_queue_offload_capa;
1195 }
1196
1197 int
eth_em_tx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_txconf * tx_conf)1198 eth_em_tx_queue_setup(struct rte_eth_dev *dev,
1199 uint16_t queue_idx,
1200 uint16_t nb_desc,
1201 unsigned int socket_id,
1202 const struct rte_eth_txconf *tx_conf)
1203 {
1204 const struct rte_memzone *tz;
1205 struct em_tx_queue *txq;
1206 struct e1000_hw *hw;
1207 uint32_t tsize;
1208 uint16_t tx_rs_thresh, tx_free_thresh;
1209 uint64_t offloads;
1210
1211 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212
1213 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1214
1215 /*
1216 * Validate number of transmit descriptors.
1217 * It must not exceed hardware maximum, and must be multiple
1218 * of E1000_ALIGN.
1219 */
1220 if (nb_desc % EM_TXD_ALIGN != 0 ||
1221 (nb_desc > E1000_MAX_RING_DESC) ||
1222 (nb_desc < E1000_MIN_RING_DESC)) {
1223 return -(EINVAL);
1224 }
1225
1226 tx_free_thresh = tx_conf->tx_free_thresh;
1227 if (tx_free_thresh == 0)
1228 tx_free_thresh = (uint16_t)RTE_MIN(nb_desc / 4,
1229 DEFAULT_TX_FREE_THRESH);
1230
1231 tx_rs_thresh = tx_conf->tx_rs_thresh;
1232 if (tx_rs_thresh == 0)
1233 tx_rs_thresh = (uint16_t)RTE_MIN(tx_free_thresh,
1234 DEFAULT_TX_RS_THRESH);
1235
1236 if (tx_free_thresh >= (nb_desc - 3)) {
1237 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1238 "number of TX descriptors minus 3. "
1239 "(tx_free_thresh=%u port=%d queue=%d)",
1240 (unsigned int)tx_free_thresh,
1241 (int)dev->data->port_id, (int)queue_idx);
1242 return -(EINVAL);
1243 }
1244 if (tx_rs_thresh > tx_free_thresh) {
1245 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1246 "tx_free_thresh. (tx_free_thresh=%u "
1247 "tx_rs_thresh=%u port=%d queue=%d)",
1248 (unsigned int)tx_free_thresh,
1249 (unsigned int)tx_rs_thresh,
1250 (int)dev->data->port_id,
1251 (int)queue_idx);
1252 return -(EINVAL);
1253 }
1254
1255 /*
1256 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1257 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1258 * by the NIC and all descriptors are written back after the NIC
1259 * accumulates WTHRESH descriptors.
1260 */
1261 if (tx_conf->tx_thresh.wthresh != 0 && tx_rs_thresh != 1) {
1262 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1263 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1264 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1265 (int)dev->data->port_id, (int)queue_idx);
1266 return -(EINVAL);
1267 }
1268
1269 /* Free memory prior to re-allocation if needed... */
1270 if (dev->data->tx_queues[queue_idx] != NULL) {
1271 em_tx_queue_release(dev->data->tx_queues[queue_idx]);
1272 dev->data->tx_queues[queue_idx] = NULL;
1273 }
1274
1275 /*
1276 * Allocate TX ring hardware descriptors. A memzone large enough to
1277 * handle the maximum ring size is allocated in order to allow for
1278 * resizing in later calls to the queue setup function.
1279 */
1280 tsize = sizeof(txq->tx_ring[0]) * E1000_MAX_RING_DESC;
1281 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, tsize,
1282 RTE_CACHE_LINE_SIZE, socket_id);
1283 if (tz == NULL)
1284 return -ENOMEM;
1285
1286 /* Allocate the tx queue data structure. */
1287 if ((txq = rte_zmalloc("ethdev TX queue", sizeof(*txq),
1288 RTE_CACHE_LINE_SIZE)) == NULL)
1289 return -ENOMEM;
1290
1291 txq->mz = tz;
1292 /* Allocate software ring */
1293 if ((txq->sw_ring = rte_zmalloc("txq->sw_ring",
1294 sizeof(txq->sw_ring[0]) * nb_desc,
1295 RTE_CACHE_LINE_SIZE)) == NULL) {
1296 em_tx_queue_release(txq);
1297 return -ENOMEM;
1298 }
1299
1300 txq->nb_tx_desc = nb_desc;
1301 txq->tx_free_thresh = tx_free_thresh;
1302 txq->tx_rs_thresh = tx_rs_thresh;
1303 txq->pthresh = tx_conf->tx_thresh.pthresh;
1304 txq->hthresh = tx_conf->tx_thresh.hthresh;
1305 txq->wthresh = tx_conf->tx_thresh.wthresh;
1306 txq->queue_id = queue_idx;
1307 txq->port_id = dev->data->port_id;
1308
1309 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
1310 txq->tx_ring_phys_addr = tz->iova;
1311 txq->tx_ring = (struct e1000_data_desc *) tz->addr;
1312
1313 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1314 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1315
1316 em_reset_tx_queue(txq);
1317
1318 dev->data->tx_queues[queue_idx] = txq;
1319 txq->offloads = offloads;
1320 return 0;
1321 }
1322
1323 static void
em_rx_queue_release_mbufs(struct em_rx_queue * rxq)1324 em_rx_queue_release_mbufs(struct em_rx_queue *rxq)
1325 {
1326 unsigned i;
1327
1328 if (rxq->sw_ring != NULL) {
1329 for (i = 0; i != rxq->nb_rx_desc; i++) {
1330 if (rxq->sw_ring[i].mbuf != NULL) {
1331 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1332 rxq->sw_ring[i].mbuf = NULL;
1333 }
1334 }
1335 }
1336 }
1337
1338 static void
em_rx_queue_release(struct em_rx_queue * rxq)1339 em_rx_queue_release(struct em_rx_queue *rxq)
1340 {
1341 if (rxq != NULL) {
1342 em_rx_queue_release_mbufs(rxq);
1343 rte_free(rxq->sw_ring);
1344 rte_memzone_free(rxq->mz);
1345 rte_free(rxq);
1346 }
1347 }
1348
1349 void
eth_em_rx_queue_release(struct rte_eth_dev * dev,uint16_t qid)1350 eth_em_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1351 {
1352 em_rx_queue_release(dev->data->rx_queues[qid]);
1353 }
1354
1355 /* Reset dynamic em_rx_queue fields back to defaults */
1356 static void
em_reset_rx_queue(struct em_rx_queue * rxq)1357 em_reset_rx_queue(struct em_rx_queue *rxq)
1358 {
1359 rxq->rx_tail = 0;
1360 rxq->nb_rx_hold = 0;
1361 rxq->pkt_first_seg = NULL;
1362 rxq->pkt_last_seg = NULL;
1363 }
1364
1365 uint64_t
em_get_rx_port_offloads_capa(void)1366 em_get_rx_port_offloads_capa(void)
1367 {
1368 uint64_t rx_offload_capa;
1369
1370 rx_offload_capa =
1371 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1372 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
1373 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1374 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1375 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1376 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
1377 RTE_ETH_RX_OFFLOAD_SCATTER;
1378
1379 return rx_offload_capa;
1380 }
1381
1382 uint64_t
em_get_rx_queue_offloads_capa(void)1383 em_get_rx_queue_offloads_capa(void)
1384 {
1385 uint64_t rx_queue_offload_capa;
1386
1387 /*
1388 * As only one Rx queue can be used, let per queue offloading
1389 * capability be same to per port queue offloading capability
1390 * for better convenience.
1391 */
1392 rx_queue_offload_capa = em_get_rx_port_offloads_capa();
1393
1394 return rx_queue_offload_capa;
1395 }
1396
1397 int
eth_em_rx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_rxconf * rx_conf,struct rte_mempool * mp)1398 eth_em_rx_queue_setup(struct rte_eth_dev *dev,
1399 uint16_t queue_idx,
1400 uint16_t nb_desc,
1401 unsigned int socket_id,
1402 const struct rte_eth_rxconf *rx_conf,
1403 struct rte_mempool *mp)
1404 {
1405 const struct rte_memzone *rz;
1406 struct em_rx_queue *rxq;
1407 struct e1000_hw *hw;
1408 uint32_t rsize;
1409 uint64_t offloads;
1410
1411 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412
1413 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1414
1415 /*
1416 * Validate number of receive descriptors.
1417 * It must not exceed hardware maximum, and must be multiple
1418 * of E1000_ALIGN.
1419 */
1420 if (nb_desc % EM_RXD_ALIGN != 0 ||
1421 (nb_desc > E1000_MAX_RING_DESC) ||
1422 (nb_desc < E1000_MIN_RING_DESC)) {
1423 return -EINVAL;
1424 }
1425
1426 /*
1427 * EM devices don't support drop_en functionality.
1428 * It's an optimization that does nothing on single-queue devices,
1429 * so just log the issue and carry on.
1430 */
1431 if (rx_conf->rx_drop_en) {
1432 PMD_INIT_LOG(NOTICE, "drop_en functionality not supported by "
1433 "device");
1434 }
1435
1436 /* Free memory prior to re-allocation if needed. */
1437 if (dev->data->rx_queues[queue_idx] != NULL) {
1438 em_rx_queue_release(dev->data->rx_queues[queue_idx]);
1439 dev->data->rx_queues[queue_idx] = NULL;
1440 }
1441
1442 /* Allocate RX ring for max possible mumber of hardware descriptors. */
1443 rsize = sizeof(rxq->rx_ring[0]) * E1000_MAX_RING_DESC;
1444 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, rsize,
1445 RTE_CACHE_LINE_SIZE, socket_id);
1446 if (rz == NULL)
1447 return -ENOMEM;
1448
1449 /* Allocate the RX queue data structure. */
1450 if ((rxq = rte_zmalloc("ethdev RX queue", sizeof(*rxq),
1451 RTE_CACHE_LINE_SIZE)) == NULL)
1452 return -ENOMEM;
1453
1454 rxq->mz = rz;
1455 /* Allocate software ring. */
1456 if ((rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1457 sizeof (rxq->sw_ring[0]) * nb_desc,
1458 RTE_CACHE_LINE_SIZE)) == NULL) {
1459 em_rx_queue_release(rxq);
1460 return -ENOMEM;
1461 }
1462
1463 rxq->mb_pool = mp;
1464 rxq->nb_rx_desc = nb_desc;
1465 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1466 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1467 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1468 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1469 rxq->queue_id = queue_idx;
1470 rxq->port_id = dev->data->port_id;
1471 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1472 rxq->crc_len = RTE_ETHER_CRC_LEN;
1473 else
1474 rxq->crc_len = 0;
1475
1476 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
1477 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));
1478 rxq->rx_ring_phys_addr = rz->iova;
1479 rxq->rx_ring = (struct e1000_rx_desc *) rz->addr;
1480
1481 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1482 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1483
1484 dev->data->rx_queues[queue_idx] = rxq;
1485 em_reset_rx_queue(rxq);
1486 rxq->offloads = offloads;
1487
1488 return 0;
1489 }
1490
1491 uint32_t
eth_em_rx_queue_count(void * rx_queue)1492 eth_em_rx_queue_count(void *rx_queue)
1493 {
1494 #define EM_RXQ_SCAN_INTERVAL 4
1495 volatile struct e1000_rx_desc *rxdp;
1496 struct em_rx_queue *rxq;
1497 uint32_t desc = 0;
1498
1499 rxq = rx_queue;
1500 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1501
1502 while ((desc < rxq->nb_rx_desc) &&
1503 (rxdp->status & E1000_RXD_STAT_DD)) {
1504 desc += EM_RXQ_SCAN_INTERVAL;
1505 rxdp += EM_RXQ_SCAN_INTERVAL;
1506 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1507 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1508 desc - rxq->nb_rx_desc]);
1509 }
1510
1511 return desc;
1512 }
1513
1514 int
eth_em_rx_descriptor_status(void * rx_queue,uint16_t offset)1515 eth_em_rx_descriptor_status(void *rx_queue, uint16_t offset)
1516 {
1517 struct em_rx_queue *rxq = rx_queue;
1518 volatile uint8_t *status;
1519 uint32_t desc;
1520
1521 if (unlikely(offset >= rxq->nb_rx_desc))
1522 return -EINVAL;
1523
1524 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1525 return RTE_ETH_RX_DESC_UNAVAIL;
1526
1527 desc = rxq->rx_tail + offset;
1528 if (desc >= rxq->nb_rx_desc)
1529 desc -= rxq->nb_rx_desc;
1530
1531 status = &rxq->rx_ring[desc].status;
1532 if (*status & E1000_RXD_STAT_DD)
1533 return RTE_ETH_RX_DESC_DONE;
1534
1535 return RTE_ETH_RX_DESC_AVAIL;
1536 }
1537
1538 int
eth_em_tx_descriptor_status(void * tx_queue,uint16_t offset)1539 eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset)
1540 {
1541 struct em_tx_queue *txq = tx_queue;
1542 volatile uint8_t *status;
1543 uint32_t desc;
1544
1545 if (unlikely(offset >= txq->nb_tx_desc))
1546 return -EINVAL;
1547
1548 desc = txq->tx_tail + offset;
1549 /* go to next desc that has the RS bit */
1550 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1551 txq->tx_rs_thresh;
1552 if (desc >= txq->nb_tx_desc) {
1553 desc -= txq->nb_tx_desc;
1554 if (desc >= txq->nb_tx_desc)
1555 desc -= txq->nb_tx_desc;
1556 }
1557
1558 status = &txq->tx_ring[desc].upper.fields.status;
1559 if (*status & E1000_TXD_STAT_DD)
1560 return RTE_ETH_TX_DESC_DONE;
1561
1562 return RTE_ETH_TX_DESC_FULL;
1563 }
1564
1565 void
em_dev_clear_queues(struct rte_eth_dev * dev)1566 em_dev_clear_queues(struct rte_eth_dev *dev)
1567 {
1568 uint16_t i;
1569 struct em_tx_queue *txq;
1570 struct em_rx_queue *rxq;
1571
1572 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1573 txq = dev->data->tx_queues[i];
1574 if (txq != NULL) {
1575 em_tx_queue_release_mbufs(txq);
1576 em_reset_tx_queue(txq);
1577 }
1578 }
1579
1580 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1581 rxq = dev->data->rx_queues[i];
1582 if (rxq != NULL) {
1583 em_rx_queue_release_mbufs(rxq);
1584 em_reset_rx_queue(rxq);
1585 }
1586 }
1587 }
1588
1589 void
em_dev_free_queues(struct rte_eth_dev * dev)1590 em_dev_free_queues(struct rte_eth_dev *dev)
1591 {
1592 uint16_t i;
1593
1594 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1595 eth_em_rx_queue_release(dev, i);
1596 dev->data->rx_queues[i] = NULL;
1597 }
1598 dev->data->nb_rx_queues = 0;
1599
1600 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1601 eth_em_tx_queue_release(dev, i);
1602 dev->data->tx_queues[i] = NULL;
1603 }
1604 dev->data->nb_tx_queues = 0;
1605 }
1606
1607 /*
1608 * Takes as input/output parameter RX buffer size.
1609 * Returns (BSIZE | BSEX | FLXBUF) fields of RCTL register.
1610 */
1611 static uint32_t
em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp,uint32_t * bufsz)1612 em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp, uint32_t *bufsz)
1613 {
1614 /*
1615 * For BSIZE & BSEX all configurable sizes are:
1616 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1617 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1618 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1619 * 2048: rctl |= E1000_RCTL_SZ_2048;
1620 * 1024: rctl |= E1000_RCTL_SZ_1024;
1621 * 512: rctl |= E1000_RCTL_SZ_512;
1622 * 256: rctl |= E1000_RCTL_SZ_256;
1623 */
1624 static const struct {
1625 uint32_t bufsz;
1626 uint32_t rctl;
1627 } bufsz_to_rctl[] = {
1628 {16384, (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX)},
1629 {8192, (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX)},
1630 {4096, (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX)},
1631 {2048, E1000_RCTL_SZ_2048},
1632 {1024, E1000_RCTL_SZ_1024},
1633 {512, E1000_RCTL_SZ_512},
1634 {256, E1000_RCTL_SZ_256},
1635 };
1636
1637 int i;
1638 uint32_t rctl_bsize;
1639
1640 rctl_bsize = *bufsz;
1641
1642 /*
1643 * Starting from 82571 it is possible to specify RX buffer size
1644 * by RCTL.FLXBUF. When this field is different from zero, the
1645 * RX buffer size = RCTL.FLXBUF * 1K
1646 * (e.g. t is possible to specify RX buffer size 1,2,...,15KB).
1647 * It is working ok on real HW, but by some reason doesn't work
1648 * on VMware emulated 82574L.
1649 * So for now, always use BSIZE/BSEX to setup RX buffer size.
1650 * If you don't plan to use it on VMware emulated 82574L and
1651 * would like to specify RX buffer size in 1K granularity,
1652 * uncomment the following lines:
1653 * ***************************************************************
1654 * if (hwtyp >= e1000_82571 && hwtyp <= e1000_82574 &&
1655 * rctl_bsize >= EM_RCTL_FLXBUF_STEP) {
1656 * rctl_bsize /= EM_RCTL_FLXBUF_STEP;
1657 * *bufsz = rctl_bsize;
1658 * return (rctl_bsize << E1000_RCTL_FLXBUF_SHIFT &
1659 * E1000_RCTL_FLXBUF_MASK);
1660 * }
1661 * ***************************************************************
1662 */
1663
1664 for (i = 0; i != sizeof(bufsz_to_rctl) / sizeof(bufsz_to_rctl[0]);
1665 i++) {
1666 if (rctl_bsize >= bufsz_to_rctl[i].bufsz) {
1667 *bufsz = bufsz_to_rctl[i].bufsz;
1668 return bufsz_to_rctl[i].rctl;
1669 }
1670 }
1671
1672 /* Should never happen. */
1673 return -EINVAL;
1674 }
1675
1676 static int
em_alloc_rx_queue_mbufs(struct em_rx_queue * rxq)1677 em_alloc_rx_queue_mbufs(struct em_rx_queue *rxq)
1678 {
1679 struct em_rx_entry *rxe = rxq->sw_ring;
1680 uint64_t dma_addr;
1681 unsigned i;
1682 static const struct e1000_rx_desc rxd_init = {
1683 .buffer_addr = 0,
1684 };
1685
1686 /* Initialize software ring entries */
1687 for (i = 0; i < rxq->nb_rx_desc; i++) {
1688 volatile struct e1000_rx_desc *rxd;
1689 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
1690
1691 if (mbuf == NULL) {
1692 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1693 "queue_id=%hu", rxq->queue_id);
1694 return -ENOMEM;
1695 }
1696
1697 dma_addr =
1698 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
1699
1700 /* Clear HW ring memory */
1701 rxq->rx_ring[i] = rxd_init;
1702
1703 rxd = &rxq->rx_ring[i];
1704 rxd->buffer_addr = dma_addr;
1705 rxe[i].mbuf = mbuf;
1706 }
1707
1708 return 0;
1709 }
1710
1711 /*********************************************************************
1712 *
1713 * Enable receive unit.
1714 *
1715 **********************************************************************/
1716 int
eth_em_rx_init(struct rte_eth_dev * dev)1717 eth_em_rx_init(struct rte_eth_dev *dev)
1718 {
1719 struct e1000_hw *hw;
1720 struct em_rx_queue *rxq;
1721 struct rte_eth_rxmode *rxmode;
1722 uint32_t rctl;
1723 uint32_t rfctl;
1724 uint32_t rxcsum;
1725 uint32_t rctl_bsize;
1726 uint16_t i;
1727 int ret;
1728
1729 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1730 rxmode = &dev->data->dev_conf.rxmode;
1731
1732 /*
1733 * Make sure receives are disabled while setting
1734 * up the descriptor ring.
1735 */
1736 rctl = E1000_READ_REG(hw, E1000_RCTL);
1737 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1738
1739 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1740
1741 /* Disable extended descriptor type. */
1742 rfctl &= ~E1000_RFCTL_EXTEN;
1743 /* Disable accelerated acknowledge */
1744 if (hw->mac.type == e1000_82574)
1745 rfctl |= E1000_RFCTL_ACK_DIS;
1746
1747 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1748
1749 /*
1750 * XXX TEMPORARY WORKAROUND: on some systems with 82573
1751 * long latencies are observed, like Lenovo X60. This
1752 * change eliminates the problem, but since having positive
1753 * values in RDTR is a known source of problems on other
1754 * platforms another solution is being sought.
1755 */
1756 if (hw->mac.type == e1000_82573)
1757 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
1758
1759 dev->rx_pkt_burst = (eth_rx_burst_t)eth_em_recv_pkts;
1760
1761 /* Determine RX bufsize. */
1762 rctl_bsize = EM_MAX_BUF_SIZE;
1763 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1764 uint32_t buf_size;
1765
1766 rxq = dev->data->rx_queues[i];
1767 buf_size = rte_pktmbuf_data_room_size(rxq->mb_pool) -
1768 RTE_PKTMBUF_HEADROOM;
1769 rctl_bsize = RTE_MIN(rctl_bsize, buf_size);
1770 }
1771
1772 rctl |= em_rctl_bsize(hw->mac.type, &rctl_bsize);
1773
1774 /* Configure and enable each RX queue. */
1775 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1776 uint64_t bus_addr;
1777 uint32_t rxdctl;
1778
1779 rxq = dev->data->rx_queues[i];
1780
1781 /* Allocate buffers for descriptor rings and setup queue */
1782 ret = em_alloc_rx_queue_mbufs(rxq);
1783 if (ret)
1784 return ret;
1785
1786 /*
1787 * Reset crc_len in case it was changed after queue setup by a
1788 * call to configure
1789 */
1790 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1791 rxq->crc_len = RTE_ETHER_CRC_LEN;
1792 else
1793 rxq->crc_len = 0;
1794
1795 bus_addr = rxq->rx_ring_phys_addr;
1796 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1797 rxq->nb_rx_desc *
1798 sizeof(*rxq->rx_ring));
1799 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1800 (uint32_t)(bus_addr >> 32));
1801 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1802
1803 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1804 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1805
1806 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1807 rxdctl &= 0xFE000000;
1808 rxdctl |= rxq->pthresh & 0x3F;
1809 rxdctl |= (rxq->hthresh & 0x3F) << 8;
1810 rxdctl |= (rxq->wthresh & 0x3F) << 16;
1811 rxdctl |= E1000_RXDCTL_GRAN;
1812 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1813
1814 /*
1815 * Due to EM devices not having any sort of hardware
1816 * limit for packet length, jumbo frame of any size
1817 * can be accepted, thus we have to enable scattered
1818 * rx if jumbo frames are enabled (or if buffer size
1819 * is too small to accommodate non-jumbo packets)
1820 * to avoid splitting packets that don't fit into
1821 * one buffer.
1822 */
1823 if (dev->data->mtu > RTE_ETHER_MTU ||
1824 rctl_bsize < RTE_ETHER_MAX_LEN) {
1825 if (!dev->data->scattered_rx)
1826 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1827 dev->rx_pkt_burst =
1828 (eth_rx_burst_t)eth_em_recv_scattered_pkts;
1829 dev->data->scattered_rx = 1;
1830 }
1831 }
1832
1833 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {
1834 if (!dev->data->scattered_rx)
1835 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1836 dev->rx_pkt_burst = eth_em_recv_scattered_pkts;
1837 dev->data->scattered_rx = 1;
1838 }
1839
1840 /*
1841 * Setup the Checksum Register.
1842 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1843 */
1844 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1845
1846 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM)
1847 rxcsum |= E1000_RXCSUM_IPOFL;
1848 else
1849 rxcsum &= ~E1000_RXCSUM_IPOFL;
1850 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1851
1852 /* No MRQ or RSS support for now */
1853
1854 /* Set early receive threshold on appropriate hw */
1855 if ((hw->mac.type == e1000_ich9lan ||
1856 hw->mac.type == e1000_pch2lan ||
1857 hw->mac.type == e1000_ich10lan) &&
1858 dev->data->mtu > RTE_ETHER_MTU) {
1859 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1860 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
1861 E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
1862 }
1863
1864 if (hw->mac.type == e1000_pch2lan) {
1865 if (dev->data->mtu > RTE_ETHER_MTU)
1866 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
1867 else
1868 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
1869 }
1870
1871 /* Setup the Receive Control Register. */
1872 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1873 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1874 else
1875 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1876
1877 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1878 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1879 E1000_RCTL_RDMTS_HALF |
1880 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1881
1882 /* Make sure VLAN Filters are off. */
1883 rctl &= ~E1000_RCTL_VFE;
1884 /* Don't store bad packets. */
1885 rctl &= ~E1000_RCTL_SBP;
1886 /* Legacy descriptor type. */
1887 rctl &= ~E1000_RCTL_DTYP_MASK;
1888
1889 /*
1890 * Configure support of jumbo frames, if any.
1891 */
1892 if (dev->data->mtu > RTE_ETHER_MTU)
1893 rctl |= E1000_RCTL_LPE;
1894 else
1895 rctl &= ~E1000_RCTL_LPE;
1896
1897 /* Enable Receives. */
1898 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1899
1900 return 0;
1901 }
1902
1903 /*********************************************************************
1904 *
1905 * Enable transmit unit.
1906 *
1907 **********************************************************************/
1908 void
eth_em_tx_init(struct rte_eth_dev * dev)1909 eth_em_tx_init(struct rte_eth_dev *dev)
1910 {
1911 struct e1000_hw *hw;
1912 struct em_tx_queue *txq;
1913 uint32_t tctl;
1914 uint32_t txdctl;
1915 uint16_t i;
1916
1917 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918
1919 /* Setup the Base and Length of the Tx Descriptor Rings. */
1920 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1921 uint64_t bus_addr;
1922
1923 txq = dev->data->tx_queues[i];
1924 bus_addr = txq->tx_ring_phys_addr;
1925 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1926 txq->nb_tx_desc *
1927 sizeof(*txq->tx_ring));
1928 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1929 (uint32_t)(bus_addr >> 32));
1930 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1931
1932 /* Setup the HW Tx Head and Tail descriptor pointers. */
1933 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1934 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1935
1936 /* Setup Transmit threshold registers. */
1937 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1938 /*
1939 * bit 22 is reserved, on some models should always be 0,
1940 * on others - always 1.
1941 */
1942 txdctl &= E1000_TXDCTL_COUNT_DESC;
1943 txdctl |= txq->pthresh & 0x3F;
1944 txdctl |= (txq->hthresh & 0x3F) << 8;
1945 txdctl |= (txq->wthresh & 0x3F) << 16;
1946 txdctl |= E1000_TXDCTL_GRAN;
1947 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1948 }
1949
1950 /* Program the Transmit Control Register. */
1951 tctl = E1000_READ_REG(hw, E1000_TCTL);
1952 tctl &= ~E1000_TCTL_CT;
1953 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1954 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1955
1956 /* SPT and CNP Si errata workaround to avoid data corruption */
1957 if (hw->mac.type == e1000_pch_spt) {
1958 uint32_t reg_val;
1959 reg_val = E1000_READ_REG(hw, E1000_IOSFPC);
1960 reg_val |= E1000_RCTL_RDMTS_HEX;
1961 E1000_WRITE_REG(hw, E1000_IOSFPC, reg_val);
1962
1963 /* Dropping the number of outstanding requests from
1964 * 3 to 2 in order to avoid a buffer overrun.
1965 */
1966 reg_val = E1000_READ_REG(hw, E1000_TARC(0));
1967 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
1968 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
1969 E1000_WRITE_REG(hw, E1000_TARC(0), reg_val);
1970 }
1971
1972 /* This write will effectively turn on the transmit unit. */
1973 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1974 }
1975
1976 void
em_rxq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_rxq_info * qinfo)1977 em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1978 struct rte_eth_rxq_info *qinfo)
1979 {
1980 struct em_rx_queue *rxq;
1981
1982 rxq = dev->data->rx_queues[queue_id];
1983
1984 qinfo->mp = rxq->mb_pool;
1985 qinfo->scattered_rx = dev->data->scattered_rx;
1986 qinfo->nb_desc = rxq->nb_rx_desc;
1987 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1988 qinfo->conf.offloads = rxq->offloads;
1989 }
1990
1991 void
em_txq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_txq_info * qinfo)1992 em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1993 struct rte_eth_txq_info *qinfo)
1994 {
1995 struct em_tx_queue *txq;
1996
1997 txq = dev->data->tx_queues[queue_id];
1998
1999 qinfo->nb_desc = txq->nb_tx_desc;
2000
2001 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2002 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2003 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2004 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2005 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2006 qinfo->conf.offloads = txq->offloads;
2007 }
2008
2009 static void
e1000_flush_tx_ring(struct rte_eth_dev * dev)2010 e1000_flush_tx_ring(struct rte_eth_dev *dev)
2011 {
2012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013 volatile struct e1000_data_desc *tx_desc;
2014 volatile uint32_t *tdt_reg_addr;
2015 uint32_t tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
2016 uint16_t size = 512;
2017 struct em_tx_queue *txq;
2018 int i;
2019
2020 if (dev->data->tx_queues == NULL)
2021 return;
2022 tctl = E1000_READ_REG(hw, E1000_TCTL);
2023 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
2024 for (i = 0; i < dev->data->nb_tx_queues &&
2025 i < E1000_I219_MAX_TX_QUEUE_NUM; i++) {
2026 txq = dev->data->tx_queues[i];
2027 tdt = E1000_READ_REG(hw, E1000_TDT(i));
2028 if (tdt != txq->tx_tail)
2029 return;
2030 tx_desc = &txq->tx_ring[txq->tx_tail];
2031 tx_desc->buffer_addr = rte_cpu_to_le_64(txq->tx_ring_phys_addr);
2032 tx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);
2033 tx_desc->upper.data = 0;
2034
2035 rte_io_wmb();
2036 txq->tx_tail++;
2037 if (txq->tx_tail == txq->nb_tx_desc)
2038 txq->tx_tail = 0;
2039 tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));
2040 E1000_PCI_REG_WRITE(tdt_reg_addr, txq->tx_tail);
2041 usec_delay(250);
2042 }
2043 }
2044
2045 static void
e1000_flush_rx_ring(struct rte_eth_dev * dev)2046 e1000_flush_rx_ring(struct rte_eth_dev *dev)
2047 {
2048 uint32_t rctl, rxdctl;
2049 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050 int i;
2051
2052 rctl = E1000_READ_REG(hw, E1000_RCTL);
2053 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2054 E1000_WRITE_FLUSH(hw);
2055 usec_delay(150);
2056
2057 for (i = 0; i < dev->data->nb_rx_queues &&
2058 i < E1000_I219_MAX_RX_QUEUE_NUM; i++) {
2059 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2060 /* zero the lower 14 bits (prefetch and host thresholds) */
2061 rxdctl &= 0xffffc000;
2062
2063 /* update thresholds: prefetch threshold to 31,
2064 * host threshold to 1 and make sure the granularity
2065 * is "descriptors" and not "cache lines"
2066 */
2067 rxdctl |= (0x1F | (1UL << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
2068
2069 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2070 }
2071 /* momentarily enable the RX ring for the changes to take effect */
2072 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
2073 E1000_WRITE_FLUSH(hw);
2074 usec_delay(150);
2075 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2076 }
2077
2078 /**
2079 * em_flush_desc_rings - remove all descriptors from the descriptor rings
2080 *
2081 * In i219, the descriptor rings must be emptied before resetting/closing the
2082 * HW. Failure to do this will cause the HW to enter a unit hang state which
2083 * can only be released by PCI reset on the device
2084 *
2085 */
2086
2087 void
em_flush_desc_rings(struct rte_eth_dev * dev)2088 em_flush_desc_rings(struct rte_eth_dev *dev)
2089 {
2090 uint32_t fextnvm11, tdlen;
2091 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2093 uint16_t pci_cfg_status = 0;
2094 int ret;
2095
2096 fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
2097 E1000_WRITE_REG(hw, E1000_FEXTNVM11,
2098 fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
2099 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
2100 ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
2101 sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
2102 if (ret < 0) {
2103 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
2104 PCI_CFG_STATUS_REG);
2105 return;
2106 }
2107
2108 /* do nothing if we're not in faulty state, or if the queue is empty */
2109 if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
2110 /* flush desc ring */
2111 e1000_flush_tx_ring(dev);
2112 ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
2113 sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
2114 if (ret < 0) {
2115 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
2116 PCI_CFG_STATUS_REG);
2117 return;
2118 }
2119
2120 if (pci_cfg_status & FLUSH_DESC_REQUIRED)
2121 e1000_flush_rx_ring(dev);
2122 }
2123 }
2124