1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
3 * All rights reserved.
4 */
5
6 #include <rte_string_fns.h>
7 #include <rte_ether.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_ethdev_pci.h>
10 #include <rte_tcp.h>
11 #include <rte_atomic.h>
12 #include <rte_dev.h>
13 #include <rte_errno.h>
14 #include <rte_version.h>
15 #include <rte_net.h>
16 #include <rte_kvargs.h>
17
18 #include "ena_ethdev.h"
19 #include "ena_logs.h"
20 #include "ena_platform.h"
21 #include "ena_com.h"
22 #include "ena_eth_com.h"
23
24 #include <ena_common_defs.h>
25 #include <ena_regs_defs.h>
26 #include <ena_admin_defs.h>
27 #include <ena_eth_io_defs.h>
28
29 #define DRV_MODULE_VER_MAJOR 2
30 #define DRV_MODULE_VER_MINOR 2
31 #define DRV_MODULE_VER_SUBMINOR 0
32
33 #define ENA_IO_TXQ_IDX(q) (2 * (q))
34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
35 /*reverse version of ENA_IO_RXQ_IDX*/
36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
37
38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
40
41 #define GET_L4_HDR_LEN(mbuf) \
42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
44
45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
47 #define ENA_HASH_KEY_SIZE 40
48 #define ETH_GSTRING_LEN 32
49
50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
51
52 #define ENA_MIN_RING_DESC 128
53
54 enum ethtool_stringset {
55 ETH_SS_TEST = 0,
56 ETH_SS_STATS,
57 };
58
59 struct ena_stats {
60 char name[ETH_GSTRING_LEN];
61 int stat_offset;
62 };
63
64 #define ENA_STAT_ENTRY(stat, stat_type) { \
65 .name = #stat, \
66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
67 }
68
69 #define ENA_STAT_RX_ENTRY(stat) \
70 ENA_STAT_ENTRY(stat, rx)
71
72 #define ENA_STAT_TX_ENTRY(stat) \
73 ENA_STAT_ENTRY(stat, tx)
74
75 #define ENA_STAT_ENI_ENTRY(stat) \
76 ENA_STAT_ENTRY(stat, eni)
77
78 #define ENA_STAT_GLOBAL_ENTRY(stat) \
79 ENA_STAT_ENTRY(stat, dev)
80
81 /* Device arguments */
82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
83
84 /*
85 * Each rte_memzone should have unique name.
86 * To satisfy it, count number of allocation and add it to name.
87 */
88 rte_atomic32_t ena_alloc_cnt;
89
90 static const struct ena_stats ena_stats_global_strings[] = {
91 ENA_STAT_GLOBAL_ENTRY(wd_expired),
92 ENA_STAT_GLOBAL_ENTRY(dev_start),
93 ENA_STAT_GLOBAL_ENTRY(dev_stop),
94 ENA_STAT_GLOBAL_ENTRY(tx_drops),
95 };
96
97 static const struct ena_stats ena_stats_eni_strings[] = {
98 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
99 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
100 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
101 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
102 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
103 };
104
105 static const struct ena_stats ena_stats_tx_strings[] = {
106 ENA_STAT_TX_ENTRY(cnt),
107 ENA_STAT_TX_ENTRY(bytes),
108 ENA_STAT_TX_ENTRY(prepare_ctx_err),
109 ENA_STAT_TX_ENTRY(linearize),
110 ENA_STAT_TX_ENTRY(linearize_failed),
111 ENA_STAT_TX_ENTRY(tx_poll),
112 ENA_STAT_TX_ENTRY(doorbells),
113 ENA_STAT_TX_ENTRY(bad_req_id),
114 ENA_STAT_TX_ENTRY(available_desc),
115 };
116
117 static const struct ena_stats ena_stats_rx_strings[] = {
118 ENA_STAT_RX_ENTRY(cnt),
119 ENA_STAT_RX_ENTRY(bytes),
120 ENA_STAT_RX_ENTRY(refill_partial),
121 ENA_STAT_RX_ENTRY(bad_csum),
122 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
123 ENA_STAT_RX_ENTRY(bad_desc_num),
124 ENA_STAT_RX_ENTRY(bad_req_id),
125 };
126
127 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
128 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings)
129 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
130 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
131
132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
133 DEV_TX_OFFLOAD_UDP_CKSUM |\
134 DEV_TX_OFFLOAD_IPV4_CKSUM |\
135 DEV_TX_OFFLOAD_TCP_TSO)
136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
137 PKT_TX_IP_CKSUM |\
138 PKT_TX_TCP_SEG)
139
140 /** Vendor ID used by Amazon devices */
141 #define PCI_VENDOR_ID_AMAZON 0x1D0F
142 /** Amazon devices */
143 #define PCI_DEVICE_ID_ENA_VF 0xEC20
144 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21
145
146 #define ENA_TX_OFFLOAD_MASK (\
147 PKT_TX_L4_MASK | \
148 PKT_TX_IPV6 | \
149 PKT_TX_IPV4 | \
150 PKT_TX_IP_CKSUM | \
151 PKT_TX_TCP_SEG)
152
153 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
154 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
155
156 static const struct rte_pci_id pci_id_ena_map[] = {
157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
158 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
159 { .device_id = 0 },
160 };
161
162 static struct ena_aenq_handlers aenq_handlers;
163
164 static int ena_device_init(struct ena_com_dev *ena_dev,
165 struct ena_com_dev_get_features_ctx *get_feat_ctx,
166 bool *wd_state);
167 static int ena_dev_configure(struct rte_eth_dev *dev);
168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
169 struct ena_tx_buffer *tx_info,
170 struct rte_mbuf *mbuf,
171 void **push_header,
172 uint16_t *header_len);
173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
174 static void ena_tx_cleanup(struct ena_ring *tx_ring);
175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
176 uint16_t nb_pkts);
177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
178 uint16_t nb_pkts);
179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
180 uint16_t nb_desc, unsigned int socket_id,
181 const struct rte_eth_txconf *tx_conf);
182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
183 uint16_t nb_desc, unsigned int socket_id,
184 const struct rte_eth_rxconf *rx_conf,
185 struct rte_mempool *mp);
186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
188 struct ena_com_rx_buf_info *ena_bufs,
189 uint32_t descs,
190 uint16_t *next_to_clean,
191 uint8_t offset);
192 static uint16_t eth_ena_recv_pkts(void *rx_queue,
193 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
195 struct rte_mbuf *mbuf, uint16_t id);
196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
197 static void ena_init_rings(struct ena_adapter *adapter,
198 bool disable_meta_caching);
199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
200 static int ena_start(struct rte_eth_dev *dev);
201 static int ena_stop(struct rte_eth_dev *dev);
202 static int ena_close(struct rte_eth_dev *dev);
203 static int ena_dev_reset(struct rte_eth_dev *dev);
204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
207 static void ena_rx_queue_release(void *queue);
208 static void ena_tx_queue_release(void *queue);
209 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
210 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
211 static int ena_link_update(struct rte_eth_dev *dev,
212 int wait_to_complete);
213 static int ena_create_io_queue(struct ena_ring *ring);
214 static void ena_queue_stop(struct ena_ring *ring);
215 static void ena_queue_stop_all(struct rte_eth_dev *dev,
216 enum ena_ring_type ring_type);
217 static int ena_queue_start(struct ena_ring *ring);
218 static int ena_queue_start_all(struct rte_eth_dev *dev,
219 enum ena_ring_type ring_type);
220 static void ena_stats_restart(struct rte_eth_dev *dev);
221 static int ena_infos_get(struct rte_eth_dev *dev,
222 struct rte_eth_dev_info *dev_info);
223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
224 struct rte_eth_rss_reta_entry64 *reta_conf,
225 uint16_t reta_size);
226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
227 struct rte_eth_rss_reta_entry64 *reta_conf,
228 uint16_t reta_size);
229 static void ena_interrupt_handler_rte(void *cb_arg);
230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
231 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
233 static int ena_xstats_get_names(struct rte_eth_dev *dev,
234 struct rte_eth_xstat_name *xstats_names,
235 unsigned int n);
236 static int ena_xstats_get(struct rte_eth_dev *dev,
237 struct rte_eth_xstat *stats,
238 unsigned int n);
239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
240 const uint64_t *ids,
241 uint64_t *values,
242 unsigned int n);
243 static int ena_process_bool_devarg(const char *key,
244 const char *value,
245 void *opaque);
246 static int ena_parse_devargs(struct ena_adapter *adapter,
247 struct rte_devargs *devargs);
248 static int ena_copy_eni_stats(struct ena_adapter *adapter);
249
250 static const struct eth_dev_ops ena_dev_ops = {
251 .dev_configure = ena_dev_configure,
252 .dev_infos_get = ena_infos_get,
253 .rx_queue_setup = ena_rx_queue_setup,
254 .tx_queue_setup = ena_tx_queue_setup,
255 .dev_start = ena_start,
256 .dev_stop = ena_stop,
257 .link_update = ena_link_update,
258 .stats_get = ena_stats_get,
259 .xstats_get_names = ena_xstats_get_names,
260 .xstats_get = ena_xstats_get,
261 .xstats_get_by_id = ena_xstats_get_by_id,
262 .mtu_set = ena_mtu_set,
263 .rx_queue_release = ena_rx_queue_release,
264 .tx_queue_release = ena_tx_queue_release,
265 .dev_close = ena_close,
266 .dev_reset = ena_dev_reset,
267 .reta_update = ena_rss_reta_update,
268 .reta_query = ena_rss_reta_query,
269 };
270
ena_rss_key_fill(void * key,size_t size)271 void ena_rss_key_fill(void *key, size_t size)
272 {
273 static bool key_generated;
274 static uint8_t default_key[ENA_HASH_KEY_SIZE];
275 size_t i;
276
277 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
278
279 if (!key_generated) {
280 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
281 default_key[i] = rte_rand() & 0xff;
282 key_generated = true;
283 }
284
285 rte_memcpy(key, default_key, size);
286 }
287
ena_rx_mbuf_prepare(struct rte_mbuf * mbuf,struct ena_com_rx_ctx * ena_rx_ctx)288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
289 struct ena_com_rx_ctx *ena_rx_ctx)
290 {
291 uint64_t ol_flags = 0;
292 uint32_t packet_type = 0;
293
294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
295 packet_type |= RTE_PTYPE_L4_TCP;
296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
297 packet_type |= RTE_PTYPE_L4_UDP;
298
299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
300 packet_type |= RTE_PTYPE_L3_IPV4;
301 if (unlikely(ena_rx_ctx->l3_csum_err))
302 ol_flags |= PKT_RX_IP_CKSUM_BAD;
303 else
304 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
305 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
306 packet_type |= RTE_PTYPE_L3_IPV6;
307 }
308
309 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
310 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
311 else
312 if (unlikely(ena_rx_ctx->l4_csum_err))
313 ol_flags |= PKT_RX_L4_CKSUM_BAD;
314 else
315 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
316
317 mbuf->ol_flags = ol_flags;
318 mbuf->packet_type = packet_type;
319 }
320
ena_tx_mbuf_prepare(struct rte_mbuf * mbuf,struct ena_com_tx_ctx * ena_tx_ctx,uint64_t queue_offloads,bool disable_meta_caching)321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
322 struct ena_com_tx_ctx *ena_tx_ctx,
323 uint64_t queue_offloads,
324 bool disable_meta_caching)
325 {
326 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
327
328 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
329 (queue_offloads & QUEUE_OFFLOADS)) {
330 /* check if TSO is required */
331 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
332 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
333 ena_tx_ctx->tso_enable = true;
334
335 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
336 }
337
338 /* check if L3 checksum is needed */
339 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
340 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
341 ena_tx_ctx->l3_csum_enable = true;
342
343 if (mbuf->ol_flags & PKT_TX_IPV6) {
344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
345 } else {
346 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
347
348 /* set don't fragment (DF) flag */
349 if (mbuf->packet_type &
350 (RTE_PTYPE_L4_NONFRAG
351 | RTE_PTYPE_INNER_L4_NONFRAG))
352 ena_tx_ctx->df = true;
353 }
354
355 /* check if L4 checksum is needed */
356 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
357 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
358 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
359 ena_tx_ctx->l4_csum_enable = true;
360 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
361 PKT_TX_UDP_CKSUM) &&
362 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
363 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
364 ena_tx_ctx->l4_csum_enable = true;
365 } else {
366 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
367 ena_tx_ctx->l4_csum_enable = false;
368 }
369
370 ena_meta->mss = mbuf->tso_segsz;
371 ena_meta->l3_hdr_len = mbuf->l3_len;
372 ena_meta->l3_hdr_offset = mbuf->l2_len;
373
374 ena_tx_ctx->meta_valid = true;
375 } else if (disable_meta_caching) {
376 memset(ena_meta, 0, sizeof(*ena_meta));
377 ena_tx_ctx->meta_valid = true;
378 } else {
379 ena_tx_ctx->meta_valid = false;
380 }
381 }
382
validate_rx_req_id(struct ena_ring * rx_ring,uint16_t req_id)383 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
384 {
385 if (likely(req_id < rx_ring->ring_size))
386 return 0;
387
388 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
389
390 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
391 rx_ring->adapter->trigger_reset = true;
392 ++rx_ring->rx_stats.bad_req_id;
393
394 return -EFAULT;
395 }
396
validate_tx_req_id(struct ena_ring * tx_ring,u16 req_id)397 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
398 {
399 struct ena_tx_buffer *tx_info = NULL;
400
401 if (likely(req_id < tx_ring->ring_size)) {
402 tx_info = &tx_ring->tx_buffer_info[req_id];
403 if (likely(tx_info->mbuf))
404 return 0;
405 }
406
407 if (tx_info)
408 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
409 else
410 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
411
412 /* Trigger device reset */
413 ++tx_ring->tx_stats.bad_req_id;
414 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
415 tx_ring->adapter->trigger_reset = true;
416 return -EFAULT;
417 }
418
ena_config_host_info(struct ena_com_dev * ena_dev)419 static void ena_config_host_info(struct ena_com_dev *ena_dev)
420 {
421 struct ena_admin_host_info *host_info;
422 int rc;
423
424 /* Allocate only the host info */
425 rc = ena_com_allocate_host_info(ena_dev);
426 if (rc) {
427 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
428 return;
429 }
430
431 host_info = ena_dev->host_attr.host_info;
432
433 host_info->os_type = ENA_ADMIN_OS_DPDK;
434 host_info->kernel_ver = RTE_VERSION;
435 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
436 sizeof(host_info->kernel_ver_str));
437 host_info->os_dist = RTE_VERSION;
438 strlcpy((char *)host_info->os_dist_str, rte_version(),
439 sizeof(host_info->os_dist_str));
440 host_info->driver_version =
441 (DRV_MODULE_VER_MAJOR) |
442 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
443 (DRV_MODULE_VER_SUBMINOR <<
444 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
445 host_info->num_cpus = rte_lcore_count();
446
447 host_info->driver_supported_features =
448 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
449
450 rc = ena_com_set_host_attributes(ena_dev);
451 if (rc) {
452 if (rc == -ENA_COM_UNSUPPORTED)
453 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
454 else
455 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
456
457 goto err;
458 }
459
460 return;
461
462 err:
463 ena_com_delete_host_info(ena_dev);
464 }
465
466 /* This function calculates the number of xstats based on the current config */
ena_xstats_calc_num(struct rte_eth_dev * dev)467 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
468 {
469 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
470 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
471 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
472 }
473
ena_config_debug_area(struct ena_adapter * adapter)474 static void ena_config_debug_area(struct ena_adapter *adapter)
475 {
476 u32 debug_area_size;
477 int rc, ss_count;
478
479 ss_count = ena_xstats_calc_num(adapter->rte_dev);
480
481 /* allocate 32 bytes for each string and 64bit for the value */
482 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
483
484 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
485 if (rc) {
486 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
487 return;
488 }
489
490 rc = ena_com_set_host_attributes(&adapter->ena_dev);
491 if (rc) {
492 if (rc == -ENA_COM_UNSUPPORTED)
493 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
494 else
495 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
496
497 goto err;
498 }
499
500 return;
501 err:
502 ena_com_delete_debug_area(&adapter->ena_dev);
503 }
504
ena_close(struct rte_eth_dev * dev)505 static int ena_close(struct rte_eth_dev *dev)
506 {
507 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
508 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
509 struct ena_adapter *adapter = dev->data->dev_private;
510 int ret = 0;
511
512 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
513 return 0;
514
515 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
516 ret = ena_stop(dev);
517 adapter->state = ENA_ADAPTER_STATE_CLOSED;
518
519 ena_rx_queue_release_all(dev);
520 ena_tx_queue_release_all(dev);
521
522 rte_free(adapter->drv_stats);
523 adapter->drv_stats = NULL;
524
525 rte_intr_disable(intr_handle);
526 rte_intr_callback_unregister(intr_handle,
527 ena_interrupt_handler_rte,
528 adapter);
529
530 /*
531 * MAC is not allocated dynamically. Setting NULL should prevent from
532 * release of the resource in the rte_eth_dev_release_port().
533 */
534 dev->data->mac_addrs = NULL;
535
536 return ret;
537 }
538
539 static int
ena_dev_reset(struct rte_eth_dev * dev)540 ena_dev_reset(struct rte_eth_dev *dev)
541 {
542 int rc = 0;
543
544 ena_destroy_device(dev);
545 rc = eth_ena_dev_init(dev);
546 if (rc)
547 PMD_INIT_LOG(CRIT, "Cannot initialize device");
548
549 return rc;
550 }
551
ena_rss_reta_update(struct rte_eth_dev * dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)552 static int ena_rss_reta_update(struct rte_eth_dev *dev,
553 struct rte_eth_rss_reta_entry64 *reta_conf,
554 uint16_t reta_size)
555 {
556 struct ena_adapter *adapter = dev->data->dev_private;
557 struct ena_com_dev *ena_dev = &adapter->ena_dev;
558 int rc, i;
559 u16 entry_value;
560 int conf_idx;
561 int idx;
562
563 if ((reta_size == 0) || (reta_conf == NULL))
564 return -EINVAL;
565
566 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
567 PMD_DRV_LOG(WARNING,
568 "indirection table %d is bigger than supported (%d)\n",
569 reta_size, ENA_RX_RSS_TABLE_SIZE);
570 return -EINVAL;
571 }
572
573 for (i = 0 ; i < reta_size ; i++) {
574 /* each reta_conf is for 64 entries.
575 * to support 128 we use 2 conf of 64
576 */
577 conf_idx = i / RTE_RETA_GROUP_SIZE;
578 idx = i % RTE_RETA_GROUP_SIZE;
579 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
580 entry_value =
581 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
582
583 rc = ena_com_indirect_table_fill_entry(ena_dev,
584 i,
585 entry_value);
586 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
587 PMD_DRV_LOG(ERR,
588 "Cannot fill indirect table\n");
589 return rc;
590 }
591 }
592 }
593
594 rte_spinlock_lock(&adapter->admin_lock);
595 rc = ena_com_indirect_table_set(ena_dev);
596 rte_spinlock_unlock(&adapter->admin_lock);
597 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
598 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
599 return rc;
600 }
601
602 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n",
603 __func__, reta_size, adapter->rte_dev->data->port_id);
604
605 return 0;
606 }
607
608 /* Query redirection table. */
ena_rss_reta_query(struct rte_eth_dev * dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)609 static int ena_rss_reta_query(struct rte_eth_dev *dev,
610 struct rte_eth_rss_reta_entry64 *reta_conf,
611 uint16_t reta_size)
612 {
613 struct ena_adapter *adapter = dev->data->dev_private;
614 struct ena_com_dev *ena_dev = &adapter->ena_dev;
615 int rc;
616 int i;
617 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
618 int reta_conf_idx;
619 int reta_idx;
620
621 if (reta_size == 0 || reta_conf == NULL ||
622 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
623 return -EINVAL;
624
625 rte_spinlock_lock(&adapter->admin_lock);
626 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
627 rte_spinlock_unlock(&adapter->admin_lock);
628 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
629 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
630 return -ENOTSUP;
631 }
632
633 for (i = 0 ; i < reta_size ; i++) {
634 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
635 reta_idx = i % RTE_RETA_GROUP_SIZE;
636 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
637 reta_conf[reta_conf_idx].reta[reta_idx] =
638 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
639 }
640
641 return 0;
642 }
643
ena_rss_init_default(struct ena_adapter * adapter)644 static int ena_rss_init_default(struct ena_adapter *adapter)
645 {
646 struct ena_com_dev *ena_dev = &adapter->ena_dev;
647 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
648 int rc, i;
649 u32 val;
650
651 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
652 if (unlikely(rc)) {
653 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
654 goto err_rss_init;
655 }
656
657 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
658 val = i % nb_rx_queues;
659 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
660 ENA_IO_RXQ_IDX(val));
661 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
662 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
663 goto err_fill_indir;
664 }
665 }
666
667 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
668 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
669 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
670 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
671 goto err_fill_indir;
672 }
673
674 rc = ena_com_set_default_hash_ctrl(ena_dev);
675 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
676 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
677 goto err_fill_indir;
678 }
679
680 rc = ena_com_indirect_table_set(ena_dev);
681 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
682 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
683 goto err_fill_indir;
684 }
685 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
686 adapter->rte_dev->data->port_id);
687
688 return 0;
689
690 err_fill_indir:
691 ena_com_rss_destroy(ena_dev);
692 err_rss_init:
693
694 return rc;
695 }
696
ena_rx_queue_release_all(struct rte_eth_dev * dev)697 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
698 {
699 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
700 int nb_queues = dev->data->nb_rx_queues;
701 int i;
702
703 for (i = 0; i < nb_queues; i++)
704 ena_rx_queue_release(queues[i]);
705 }
706
ena_tx_queue_release_all(struct rte_eth_dev * dev)707 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
708 {
709 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
710 int nb_queues = dev->data->nb_tx_queues;
711 int i;
712
713 for (i = 0; i < nb_queues; i++)
714 ena_tx_queue_release(queues[i]);
715 }
716
ena_rx_queue_release(void * queue)717 static void ena_rx_queue_release(void *queue)
718 {
719 struct ena_ring *ring = (struct ena_ring *)queue;
720
721 /* Free ring resources */
722 if (ring->rx_buffer_info)
723 rte_free(ring->rx_buffer_info);
724 ring->rx_buffer_info = NULL;
725
726 if (ring->rx_refill_buffer)
727 rte_free(ring->rx_refill_buffer);
728 ring->rx_refill_buffer = NULL;
729
730 if (ring->empty_rx_reqs)
731 rte_free(ring->empty_rx_reqs);
732 ring->empty_rx_reqs = NULL;
733
734 ring->configured = 0;
735
736 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
737 ring->port_id, ring->id);
738 }
739
ena_tx_queue_release(void * queue)740 static void ena_tx_queue_release(void *queue)
741 {
742 struct ena_ring *ring = (struct ena_ring *)queue;
743
744 /* Free ring resources */
745 if (ring->push_buf_intermediate_buf)
746 rte_free(ring->push_buf_intermediate_buf);
747
748 if (ring->tx_buffer_info)
749 rte_free(ring->tx_buffer_info);
750
751 if (ring->empty_tx_reqs)
752 rte_free(ring->empty_tx_reqs);
753
754 ring->empty_tx_reqs = NULL;
755 ring->tx_buffer_info = NULL;
756 ring->push_buf_intermediate_buf = NULL;
757
758 ring->configured = 0;
759
760 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
761 ring->port_id, ring->id);
762 }
763
ena_rx_queue_release_bufs(struct ena_ring * ring)764 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
765 {
766 unsigned int i;
767
768 for (i = 0; i < ring->ring_size; ++i) {
769 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
770 if (rx_info->mbuf) {
771 rte_mbuf_raw_free(rx_info->mbuf);
772 rx_info->mbuf = NULL;
773 }
774 }
775 }
776
ena_tx_queue_release_bufs(struct ena_ring * ring)777 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
778 {
779 unsigned int i;
780
781 for (i = 0; i < ring->ring_size; ++i) {
782 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
783
784 if (tx_buf->mbuf)
785 rte_pktmbuf_free(tx_buf->mbuf);
786 }
787 }
788
ena_link_update(struct rte_eth_dev * dev,__rte_unused int wait_to_complete)789 static int ena_link_update(struct rte_eth_dev *dev,
790 __rte_unused int wait_to_complete)
791 {
792 struct rte_eth_link *link = &dev->data->dev_link;
793 struct ena_adapter *adapter = dev->data->dev_private;
794
795 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
796 link->link_speed = ETH_SPEED_NUM_NONE;
797 link->link_duplex = ETH_LINK_FULL_DUPLEX;
798
799 return 0;
800 }
801
ena_queue_start_all(struct rte_eth_dev * dev,enum ena_ring_type ring_type)802 static int ena_queue_start_all(struct rte_eth_dev *dev,
803 enum ena_ring_type ring_type)
804 {
805 struct ena_adapter *adapter = dev->data->dev_private;
806 struct ena_ring *queues = NULL;
807 int nb_queues;
808 int i = 0;
809 int rc = 0;
810
811 if (ring_type == ENA_RING_TYPE_RX) {
812 queues = adapter->rx_ring;
813 nb_queues = dev->data->nb_rx_queues;
814 } else {
815 queues = adapter->tx_ring;
816 nb_queues = dev->data->nb_tx_queues;
817 }
818 for (i = 0; i < nb_queues; i++) {
819 if (queues[i].configured) {
820 if (ring_type == ENA_RING_TYPE_RX) {
821 ena_assert_msg(
822 dev->data->rx_queues[i] == &queues[i],
823 "Inconsistent state of rx queues\n");
824 } else {
825 ena_assert_msg(
826 dev->data->tx_queues[i] == &queues[i],
827 "Inconsistent state of tx queues\n");
828 }
829
830 rc = ena_queue_start(&queues[i]);
831
832 if (rc) {
833 PMD_INIT_LOG(ERR,
834 "failed to start queue %d type(%d)",
835 i, ring_type);
836 goto err;
837 }
838 }
839 }
840
841 return 0;
842
843 err:
844 while (i--)
845 if (queues[i].configured)
846 ena_queue_stop(&queues[i]);
847
848 return rc;
849 }
850
ena_get_mtu_conf(struct ena_adapter * adapter)851 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
852 {
853 uint32_t max_frame_len = adapter->max_mtu;
854
855 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
856 DEV_RX_OFFLOAD_JUMBO_FRAME)
857 max_frame_len =
858 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
859
860 return max_frame_len;
861 }
862
ena_check_valid_conf(struct ena_adapter * adapter)863 static int ena_check_valid_conf(struct ena_adapter *adapter)
864 {
865 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
866
867 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
868 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
869 "max mtu: %d, min mtu: %d",
870 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
871 return ENA_COM_UNSUPPORTED;
872 }
873
874 return 0;
875 }
876
877 static int
ena_calc_io_queue_size(struct ena_calc_queue_size_ctx * ctx,bool use_large_llq_hdr)878 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
879 bool use_large_llq_hdr)
880 {
881 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
882 struct ena_com_dev *ena_dev = ctx->ena_dev;
883 uint32_t max_tx_queue_size;
884 uint32_t max_rx_queue_size;
885
886 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
887 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
888 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
889 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
890 max_queue_ext->max_rx_sq_depth);
891 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
892
893 if (ena_dev->tx_mem_queue_type ==
894 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
895 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
896 llq->max_llq_depth);
897 } else {
898 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
899 max_queue_ext->max_tx_sq_depth);
900 }
901
902 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
903 max_queue_ext->max_per_packet_rx_descs);
904 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
905 max_queue_ext->max_per_packet_tx_descs);
906 } else {
907 struct ena_admin_queue_feature_desc *max_queues =
908 &ctx->get_feat_ctx->max_queues;
909 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
910 max_queues->max_sq_depth);
911 max_tx_queue_size = max_queues->max_cq_depth;
912
913 if (ena_dev->tx_mem_queue_type ==
914 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
915 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
916 llq->max_llq_depth);
917 } else {
918 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
919 max_queues->max_sq_depth);
920 }
921
922 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
923 max_queues->max_packet_rx_descs);
924 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
925 max_queues->max_packet_tx_descs);
926 }
927
928 /* Round down to the nearest power of 2 */
929 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
930 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
931
932 if (use_large_llq_hdr) {
933 if ((llq->entry_size_ctrl_supported &
934 ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
935 (ena_dev->tx_mem_queue_type ==
936 ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
937 max_tx_queue_size /= 2;
938 PMD_INIT_LOG(INFO,
939 "Forcing large headers and decreasing maximum TX queue size to %d\n",
940 max_tx_queue_size);
941 } else {
942 PMD_INIT_LOG(ERR,
943 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
944 }
945 }
946
947 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
948 PMD_INIT_LOG(ERR, "Invalid queue size");
949 return -EFAULT;
950 }
951
952 ctx->max_tx_queue_size = max_tx_queue_size;
953 ctx->max_rx_queue_size = max_rx_queue_size;
954
955 return 0;
956 }
957
ena_stats_restart(struct rte_eth_dev * dev)958 static void ena_stats_restart(struct rte_eth_dev *dev)
959 {
960 struct ena_adapter *adapter = dev->data->dev_private;
961
962 rte_atomic64_init(&adapter->drv_stats->ierrors);
963 rte_atomic64_init(&adapter->drv_stats->oerrors);
964 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
965 adapter->drv_stats->rx_drops = 0;
966 }
967
ena_stats_get(struct rte_eth_dev * dev,struct rte_eth_stats * stats)968 static int ena_stats_get(struct rte_eth_dev *dev,
969 struct rte_eth_stats *stats)
970 {
971 struct ena_admin_basic_stats ena_stats;
972 struct ena_adapter *adapter = dev->data->dev_private;
973 struct ena_com_dev *ena_dev = &adapter->ena_dev;
974 int rc;
975 int i;
976 int max_rings_stats;
977
978 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
979 return -ENOTSUP;
980
981 memset(&ena_stats, 0, sizeof(ena_stats));
982
983 rte_spinlock_lock(&adapter->admin_lock);
984 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
985 rte_spinlock_unlock(&adapter->admin_lock);
986 if (unlikely(rc)) {
987 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
988 return rc;
989 }
990
991 /* Set of basic statistics from ENA */
992 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
993 ena_stats.rx_pkts_low);
994 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
995 ena_stats.tx_pkts_low);
996 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
997 ena_stats.rx_bytes_low);
998 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
999 ena_stats.tx_bytes_low);
1000
1001 /* Driver related stats */
1002 stats->imissed = adapter->drv_stats->rx_drops;
1003 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1004 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1005 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1006
1007 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1008 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1009 for (i = 0; i < max_rings_stats; ++i) {
1010 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1011
1012 stats->q_ibytes[i] = rx_stats->bytes;
1013 stats->q_ipackets[i] = rx_stats->cnt;
1014 stats->q_errors[i] = rx_stats->bad_desc_num +
1015 rx_stats->bad_req_id;
1016 }
1017
1018 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1019 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1020 for (i = 0; i < max_rings_stats; ++i) {
1021 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1022
1023 stats->q_obytes[i] = tx_stats->bytes;
1024 stats->q_opackets[i] = tx_stats->cnt;
1025 }
1026
1027 return 0;
1028 }
1029
ena_mtu_set(struct rte_eth_dev * dev,uint16_t mtu)1030 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1031 {
1032 struct ena_adapter *adapter;
1033 struct ena_com_dev *ena_dev;
1034 int rc = 0;
1035
1036 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1037 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1038 adapter = dev->data->dev_private;
1039
1040 ena_dev = &adapter->ena_dev;
1041 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1042
1043 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1044 PMD_DRV_LOG(ERR,
1045 "Invalid MTU setting. new_mtu: %d "
1046 "max mtu: %d min mtu: %d\n",
1047 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1048 return -EINVAL;
1049 }
1050
1051 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1052 if (rc)
1053 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1054 else
1055 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1056
1057 return rc;
1058 }
1059
ena_start(struct rte_eth_dev * dev)1060 static int ena_start(struct rte_eth_dev *dev)
1061 {
1062 struct ena_adapter *adapter = dev->data->dev_private;
1063 uint64_t ticks;
1064 int rc = 0;
1065
1066 rc = ena_check_valid_conf(adapter);
1067 if (rc)
1068 return rc;
1069
1070 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1071 if (rc)
1072 return rc;
1073
1074 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1075 if (rc)
1076 goto err_start_tx;
1077
1078 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1079 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1080 rc = ena_rss_init_default(adapter);
1081 if (rc)
1082 goto err_rss_init;
1083 }
1084
1085 ena_stats_restart(dev);
1086
1087 adapter->timestamp_wd = rte_get_timer_cycles();
1088 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1089
1090 ticks = rte_get_timer_hz();
1091 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1092 ena_timer_wd_callback, adapter);
1093
1094 ++adapter->dev_stats.dev_start;
1095 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1096
1097 return 0;
1098
1099 err_rss_init:
1100 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1101 err_start_tx:
1102 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1103 return rc;
1104 }
1105
ena_stop(struct rte_eth_dev * dev)1106 static int ena_stop(struct rte_eth_dev *dev)
1107 {
1108 struct ena_adapter *adapter = dev->data->dev_private;
1109 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1110 int rc;
1111
1112 rte_timer_stop_sync(&adapter->timer_wd);
1113 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1114 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1115
1116 if (adapter->trigger_reset) {
1117 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1118 if (rc)
1119 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1120 }
1121
1122 ++adapter->dev_stats.dev_stop;
1123 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1124 dev->data->dev_started = 0;
1125
1126 return 0;
1127 }
1128
ena_create_io_queue(struct ena_ring * ring)1129 static int ena_create_io_queue(struct ena_ring *ring)
1130 {
1131 struct ena_adapter *adapter;
1132 struct ena_com_dev *ena_dev;
1133 struct ena_com_create_io_ctx ctx =
1134 /* policy set to _HOST just to satisfy icc compiler */
1135 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1136 0, 0, 0, 0, 0 };
1137 uint16_t ena_qid;
1138 unsigned int i;
1139 int rc;
1140
1141 adapter = ring->adapter;
1142 ena_dev = &adapter->ena_dev;
1143
1144 if (ring->type == ENA_RING_TYPE_TX) {
1145 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1146 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1147 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1148 for (i = 0; i < ring->ring_size; i++)
1149 ring->empty_tx_reqs[i] = i;
1150 } else {
1151 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1152 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1153 for (i = 0; i < ring->ring_size; i++)
1154 ring->empty_rx_reqs[i] = i;
1155 }
1156 ctx.queue_size = ring->ring_size;
1157 ctx.qid = ena_qid;
1158 ctx.msix_vector = -1; /* interrupts not used */
1159 ctx.numa_node = ring->numa_socket_id;
1160
1161 rc = ena_com_create_io_queue(ena_dev, &ctx);
1162 if (rc) {
1163 PMD_DRV_LOG(ERR,
1164 "failed to create io queue #%d (qid:%d) rc: %d\n",
1165 ring->id, ena_qid, rc);
1166 return rc;
1167 }
1168
1169 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1170 &ring->ena_com_io_sq,
1171 &ring->ena_com_io_cq);
1172 if (rc) {
1173 PMD_DRV_LOG(ERR,
1174 "Failed to get io queue handlers. queue num %d rc: %d\n",
1175 ring->id, rc);
1176 ena_com_destroy_io_queue(ena_dev, ena_qid);
1177 return rc;
1178 }
1179
1180 if (ring->type == ENA_RING_TYPE_TX)
1181 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1182
1183 return 0;
1184 }
1185
ena_queue_stop(struct ena_ring * ring)1186 static void ena_queue_stop(struct ena_ring *ring)
1187 {
1188 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1189
1190 if (ring->type == ENA_RING_TYPE_RX) {
1191 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1192 ena_rx_queue_release_bufs(ring);
1193 } else {
1194 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1195 ena_tx_queue_release_bufs(ring);
1196 }
1197 }
1198
ena_queue_stop_all(struct rte_eth_dev * dev,enum ena_ring_type ring_type)1199 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1200 enum ena_ring_type ring_type)
1201 {
1202 struct ena_adapter *adapter = dev->data->dev_private;
1203 struct ena_ring *queues = NULL;
1204 uint16_t nb_queues, i;
1205
1206 if (ring_type == ENA_RING_TYPE_RX) {
1207 queues = adapter->rx_ring;
1208 nb_queues = dev->data->nb_rx_queues;
1209 } else {
1210 queues = adapter->tx_ring;
1211 nb_queues = dev->data->nb_tx_queues;
1212 }
1213
1214 for (i = 0; i < nb_queues; ++i)
1215 if (queues[i].configured)
1216 ena_queue_stop(&queues[i]);
1217 }
1218
ena_queue_start(struct ena_ring * ring)1219 static int ena_queue_start(struct ena_ring *ring)
1220 {
1221 int rc, bufs_num;
1222
1223 ena_assert_msg(ring->configured == 1,
1224 "Trying to start unconfigured queue\n");
1225
1226 rc = ena_create_io_queue(ring);
1227 if (rc) {
1228 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1229 return rc;
1230 }
1231
1232 ring->next_to_clean = 0;
1233 ring->next_to_use = 0;
1234
1235 if (ring->type == ENA_RING_TYPE_TX) {
1236 ring->tx_stats.available_desc =
1237 ena_com_free_q_entries(ring->ena_com_io_sq);
1238 return 0;
1239 }
1240
1241 bufs_num = ring->ring_size - 1;
1242 rc = ena_populate_rx_queue(ring, bufs_num);
1243 if (rc != bufs_num) {
1244 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1245 ENA_IO_RXQ_IDX(ring->id));
1246 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1247 return ENA_COM_FAULT;
1248 }
1249
1250 return 0;
1251 }
1252
ena_tx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_txconf * tx_conf)1253 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1254 uint16_t queue_idx,
1255 uint16_t nb_desc,
1256 unsigned int socket_id,
1257 const struct rte_eth_txconf *tx_conf)
1258 {
1259 struct ena_ring *txq = NULL;
1260 struct ena_adapter *adapter = dev->data->dev_private;
1261 unsigned int i;
1262
1263 txq = &adapter->tx_ring[queue_idx];
1264
1265 if (txq->configured) {
1266 PMD_DRV_LOG(CRIT,
1267 "API violation. Queue %d is already configured\n",
1268 queue_idx);
1269 return ENA_COM_FAULT;
1270 }
1271
1272 if (!rte_is_power_of_2(nb_desc)) {
1273 PMD_DRV_LOG(ERR,
1274 "Unsupported size of TX queue: %d is not a power of 2.\n",
1275 nb_desc);
1276 return -EINVAL;
1277 }
1278
1279 if (nb_desc > adapter->max_tx_ring_size) {
1280 PMD_DRV_LOG(ERR,
1281 "Unsupported size of TX queue (max size: %d)\n",
1282 adapter->max_tx_ring_size);
1283 return -EINVAL;
1284 }
1285
1286 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1287 nb_desc = adapter->max_tx_ring_size;
1288
1289 txq->port_id = dev->data->port_id;
1290 txq->next_to_clean = 0;
1291 txq->next_to_use = 0;
1292 txq->ring_size = nb_desc;
1293 txq->size_mask = nb_desc - 1;
1294 txq->numa_socket_id = socket_id;
1295
1296 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1297 sizeof(struct ena_tx_buffer) *
1298 txq->ring_size,
1299 RTE_CACHE_LINE_SIZE);
1300 if (!txq->tx_buffer_info) {
1301 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1302 return -ENOMEM;
1303 }
1304
1305 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1306 sizeof(u16) * txq->ring_size,
1307 RTE_CACHE_LINE_SIZE);
1308 if (!txq->empty_tx_reqs) {
1309 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1310 rte_free(txq->tx_buffer_info);
1311 return -ENOMEM;
1312 }
1313
1314 txq->push_buf_intermediate_buf =
1315 rte_zmalloc("txq->push_buf_intermediate_buf",
1316 txq->tx_max_header_size,
1317 RTE_CACHE_LINE_SIZE);
1318 if (!txq->push_buf_intermediate_buf) {
1319 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1320 rte_free(txq->tx_buffer_info);
1321 rte_free(txq->empty_tx_reqs);
1322 return -ENOMEM;
1323 }
1324
1325 for (i = 0; i < txq->ring_size; i++)
1326 txq->empty_tx_reqs[i] = i;
1327
1328 if (tx_conf != NULL) {
1329 txq->offloads =
1330 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1331 }
1332 /* Store pointer to this queue in upper layer */
1333 txq->configured = 1;
1334 dev->data->tx_queues[queue_idx] = txq;
1335
1336 return 0;
1337 }
1338
ena_rx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,__rte_unused const struct rte_eth_rxconf * rx_conf,struct rte_mempool * mp)1339 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1340 uint16_t queue_idx,
1341 uint16_t nb_desc,
1342 unsigned int socket_id,
1343 __rte_unused const struct rte_eth_rxconf *rx_conf,
1344 struct rte_mempool *mp)
1345 {
1346 struct ena_adapter *adapter = dev->data->dev_private;
1347 struct ena_ring *rxq = NULL;
1348 size_t buffer_size;
1349 int i;
1350
1351 rxq = &adapter->rx_ring[queue_idx];
1352 if (rxq->configured) {
1353 PMD_DRV_LOG(CRIT,
1354 "API violation. Queue %d is already configured\n",
1355 queue_idx);
1356 return ENA_COM_FAULT;
1357 }
1358
1359 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1360 nb_desc = adapter->max_rx_ring_size;
1361
1362 if (!rte_is_power_of_2(nb_desc)) {
1363 PMD_DRV_LOG(ERR,
1364 "Unsupported size of RX queue: %d is not a power of 2.\n",
1365 nb_desc);
1366 return -EINVAL;
1367 }
1368
1369 if (nb_desc > adapter->max_rx_ring_size) {
1370 PMD_DRV_LOG(ERR,
1371 "Unsupported size of RX queue (max size: %d)\n",
1372 adapter->max_rx_ring_size);
1373 return -EINVAL;
1374 }
1375
1376 /* ENA isn't supporting buffers smaller than 1400 bytes */
1377 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1378 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1379 PMD_DRV_LOG(ERR,
1380 "Unsupported size of RX buffer: %zu (min size: %d)\n",
1381 buffer_size, ENA_RX_BUF_MIN_SIZE);
1382 return -EINVAL;
1383 }
1384
1385 rxq->port_id = dev->data->port_id;
1386 rxq->next_to_clean = 0;
1387 rxq->next_to_use = 0;
1388 rxq->ring_size = nb_desc;
1389 rxq->size_mask = nb_desc - 1;
1390 rxq->numa_socket_id = socket_id;
1391 rxq->mb_pool = mp;
1392
1393 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1394 sizeof(struct ena_rx_buffer) * nb_desc,
1395 RTE_CACHE_LINE_SIZE);
1396 if (!rxq->rx_buffer_info) {
1397 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1398 return -ENOMEM;
1399 }
1400
1401 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1402 sizeof(struct rte_mbuf *) * nb_desc,
1403 RTE_CACHE_LINE_SIZE);
1404
1405 if (!rxq->rx_refill_buffer) {
1406 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1407 rte_free(rxq->rx_buffer_info);
1408 rxq->rx_buffer_info = NULL;
1409 return -ENOMEM;
1410 }
1411
1412 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1413 sizeof(uint16_t) * nb_desc,
1414 RTE_CACHE_LINE_SIZE);
1415 if (!rxq->empty_rx_reqs) {
1416 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1417 rte_free(rxq->rx_buffer_info);
1418 rxq->rx_buffer_info = NULL;
1419 rte_free(rxq->rx_refill_buffer);
1420 rxq->rx_refill_buffer = NULL;
1421 return -ENOMEM;
1422 }
1423
1424 for (i = 0; i < nb_desc; i++)
1425 rxq->empty_rx_reqs[i] = i;
1426
1427 /* Store pointer to this queue in upper layer */
1428 rxq->configured = 1;
1429 dev->data->rx_queues[queue_idx] = rxq;
1430
1431 return 0;
1432 }
1433
ena_add_single_rx_desc(struct ena_com_io_sq * io_sq,struct rte_mbuf * mbuf,uint16_t id)1434 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1435 struct rte_mbuf *mbuf, uint16_t id)
1436 {
1437 struct ena_com_buf ebuf;
1438 int rc;
1439
1440 /* prepare physical address for DMA transaction */
1441 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1442 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1443
1444 /* pass resource to device */
1445 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1446 if (unlikely(rc != 0))
1447 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1448
1449 return rc;
1450 }
1451
ena_populate_rx_queue(struct ena_ring * rxq,unsigned int count)1452 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1453 {
1454 unsigned int i;
1455 int rc;
1456 uint16_t next_to_use = rxq->next_to_use;
1457 uint16_t in_use, req_id;
1458 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1459
1460 if (unlikely(!count))
1461 return 0;
1462
1463 in_use = rxq->ring_size - 1 -
1464 ena_com_free_q_entries(rxq->ena_com_io_sq);
1465 ena_assert_msg(((in_use + count) < rxq->ring_size),
1466 "bad ring state\n");
1467
1468 /* get resources for incoming packets */
1469 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1470 if (unlikely(rc < 0)) {
1471 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1472 ++rxq->rx_stats.mbuf_alloc_fail;
1473 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1474 return 0;
1475 }
1476
1477 for (i = 0; i < count; i++) {
1478 struct rte_mbuf *mbuf = mbufs[i];
1479 struct ena_rx_buffer *rx_info;
1480
1481 if (likely((i + 4) < count))
1482 rte_prefetch0(mbufs[i + 4]);
1483
1484 req_id = rxq->empty_rx_reqs[next_to_use];
1485 rc = validate_rx_req_id(rxq, req_id);
1486 if (unlikely(rc))
1487 break;
1488
1489 rx_info = &rxq->rx_buffer_info[req_id];
1490
1491 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1492 if (unlikely(rc != 0))
1493 break;
1494
1495 rx_info->mbuf = mbuf;
1496 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1497 }
1498
1499 if (unlikely(i < count)) {
1500 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1501 "buffers (from %d)\n", rxq->id, i, count);
1502 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1503 count - i);
1504 ++rxq->rx_stats.refill_partial;
1505 }
1506
1507 /* When we submitted free recources to device... */
1508 if (likely(i > 0)) {
1509 /* ...let HW know that it can fill buffers with data. */
1510 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1511
1512 rxq->next_to_use = next_to_use;
1513 }
1514
1515 return i;
1516 }
1517
ena_device_init(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx,bool * wd_state)1518 static int ena_device_init(struct ena_com_dev *ena_dev,
1519 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1520 bool *wd_state)
1521 {
1522 uint32_t aenq_groups;
1523 int rc;
1524 bool readless_supported;
1525
1526 /* Initialize mmio registers */
1527 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1528 if (rc) {
1529 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1530 return rc;
1531 }
1532
1533 /* The PCIe configuration space revision id indicate if mmio reg
1534 * read is disabled.
1535 */
1536 readless_supported =
1537 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1538 & ENA_MMIO_DISABLE_REG_READ);
1539 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1540
1541 /* reset device */
1542 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1543 if (rc) {
1544 PMD_DRV_LOG(ERR, "cannot reset device\n");
1545 goto err_mmio_read_less;
1546 }
1547
1548 /* check FW version */
1549 rc = ena_com_validate_version(ena_dev);
1550 if (rc) {
1551 PMD_DRV_LOG(ERR, "device version is too low\n");
1552 goto err_mmio_read_less;
1553 }
1554
1555 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1556
1557 /* ENA device administration layer init */
1558 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1559 if (rc) {
1560 PMD_DRV_LOG(ERR,
1561 "cannot initialize ena admin queue with device\n");
1562 goto err_mmio_read_less;
1563 }
1564
1565 /* To enable the msix interrupts the driver needs to know the number
1566 * of queues. So the driver uses polling mode to retrieve this
1567 * information.
1568 */
1569 ena_com_set_admin_polling_mode(ena_dev, true);
1570
1571 ena_config_host_info(ena_dev);
1572
1573 /* Get Device Attributes and features */
1574 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1575 if (rc) {
1576 PMD_DRV_LOG(ERR,
1577 "cannot get attribute for ena device rc= %d\n", rc);
1578 goto err_admin_init;
1579 }
1580
1581 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1582 BIT(ENA_ADMIN_NOTIFICATION) |
1583 BIT(ENA_ADMIN_KEEP_ALIVE) |
1584 BIT(ENA_ADMIN_FATAL_ERROR) |
1585 BIT(ENA_ADMIN_WARNING);
1586
1587 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1588 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1589 if (rc) {
1590 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1591 goto err_admin_init;
1592 }
1593
1594 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1595
1596 return 0;
1597
1598 err_admin_init:
1599 ena_com_admin_destroy(ena_dev);
1600
1601 err_mmio_read_less:
1602 ena_com_mmio_reg_read_request_destroy(ena_dev);
1603
1604 return rc;
1605 }
1606
ena_interrupt_handler_rte(void * cb_arg)1607 static void ena_interrupt_handler_rte(void *cb_arg)
1608 {
1609 struct ena_adapter *adapter = cb_arg;
1610 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1611
1612 ena_com_admin_q_comp_intr_handler(ena_dev);
1613 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1614 ena_com_aenq_intr_handler(ena_dev, adapter);
1615 }
1616
check_for_missing_keep_alive(struct ena_adapter * adapter)1617 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1618 {
1619 if (!adapter->wd_state)
1620 return;
1621
1622 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1623 return;
1624
1625 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1626 adapter->keep_alive_timeout)) {
1627 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1628 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1629 adapter->trigger_reset = true;
1630 ++adapter->dev_stats.wd_expired;
1631 }
1632 }
1633
1634 /* Check if admin queue is enabled */
check_for_admin_com_state(struct ena_adapter * adapter)1635 static void check_for_admin_com_state(struct ena_adapter *adapter)
1636 {
1637 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1638 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1639 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1640 adapter->trigger_reset = true;
1641 }
1642 }
1643
ena_timer_wd_callback(__rte_unused struct rte_timer * timer,void * arg)1644 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1645 void *arg)
1646 {
1647 struct ena_adapter *adapter = arg;
1648 struct rte_eth_dev *dev = adapter->rte_dev;
1649
1650 check_for_missing_keep_alive(adapter);
1651 check_for_admin_com_state(adapter);
1652
1653 if (unlikely(adapter->trigger_reset)) {
1654 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1655 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1656 NULL);
1657 }
1658 }
1659
1660 static inline void
set_default_llq_configurations(struct ena_llq_configurations * llq_config,struct ena_admin_feature_llq_desc * llq,bool use_large_llq_hdr)1661 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1662 struct ena_admin_feature_llq_desc *llq,
1663 bool use_large_llq_hdr)
1664 {
1665 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1666 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1667 llq_config->llq_num_decs_before_header =
1668 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1669
1670 if (use_large_llq_hdr &&
1671 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1672 llq_config->llq_ring_entry_size =
1673 ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1674 llq_config->llq_ring_entry_size_value = 256;
1675 } else {
1676 llq_config->llq_ring_entry_size =
1677 ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1678 llq_config->llq_ring_entry_size_value = 128;
1679 }
1680 }
1681
1682 static int
ena_set_queues_placement_policy(struct ena_adapter * adapter,struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq,struct ena_llq_configurations * llq_default_configurations)1683 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1684 struct ena_com_dev *ena_dev,
1685 struct ena_admin_feature_llq_desc *llq,
1686 struct ena_llq_configurations *llq_default_configurations)
1687 {
1688 int rc;
1689 u32 llq_feature_mask;
1690
1691 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1692 if (!(ena_dev->supported_features & llq_feature_mask)) {
1693 PMD_DRV_LOG(INFO,
1694 "LLQ is not supported. Fallback to host mode policy.\n");
1695 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1696 return 0;
1697 }
1698
1699 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1700 if (unlikely(rc)) {
1701 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1702 "Fallback to host mode policy.");
1703 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1704 return 0;
1705 }
1706
1707 /* Nothing to config, exit */
1708 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1709 return 0;
1710
1711 if (!adapter->dev_mem_base) {
1712 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1713 "Fallback to host mode policy.\n.");
1714 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1715 return 0;
1716 }
1717
1718 ena_dev->mem_bar = adapter->dev_mem_base;
1719
1720 return 0;
1721 }
1722
ena_calc_max_io_queue_num(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx)1723 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1724 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1725 {
1726 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1727
1728 /* Regular queues capabilities */
1729 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1730 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1731 &get_feat_ctx->max_queue_ext.max_queue_ext;
1732 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1733 max_queue_ext->max_rx_cq_num);
1734 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1735 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1736 } else {
1737 struct ena_admin_queue_feature_desc *max_queues =
1738 &get_feat_ctx->max_queues;
1739 io_tx_sq_num = max_queues->max_sq_num;
1740 io_tx_cq_num = max_queues->max_cq_num;
1741 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1742 }
1743
1744 /* In case of LLQ use the llq number in the get feature cmd */
1745 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1746 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1747
1748 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1749 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1750 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1751
1752 if (unlikely(max_num_io_queues == 0)) {
1753 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1754 return -EFAULT;
1755 }
1756
1757 return max_num_io_queues;
1758 }
1759
eth_ena_dev_init(struct rte_eth_dev * eth_dev)1760 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1761 {
1762 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1763 struct rte_pci_device *pci_dev;
1764 struct rte_intr_handle *intr_handle;
1765 struct ena_adapter *adapter = eth_dev->data->dev_private;
1766 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1767 struct ena_com_dev_get_features_ctx get_feat_ctx;
1768 struct ena_llq_configurations llq_config;
1769 const char *queue_type_str;
1770 uint32_t max_num_io_queues;
1771 int rc;
1772 static int adapters_found;
1773 bool disable_meta_caching;
1774 bool wd_state = false;
1775
1776 eth_dev->dev_ops = &ena_dev_ops;
1777 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1778 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1779 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1780
1781 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1782 return 0;
1783
1784 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1785
1786 memset(adapter, 0, sizeof(struct ena_adapter));
1787 ena_dev = &adapter->ena_dev;
1788
1789 adapter->rte_eth_dev_data = eth_dev->data;
1790 adapter->rte_dev = eth_dev;
1791
1792 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1793 adapter->pdev = pci_dev;
1794
1795 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1796 pci_dev->addr.domain,
1797 pci_dev->addr.bus,
1798 pci_dev->addr.devid,
1799 pci_dev->addr.function);
1800
1801 intr_handle = &pci_dev->intr_handle;
1802
1803 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1804 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1805
1806 if (!adapter->regs) {
1807 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1808 ENA_REGS_BAR);
1809 return -ENXIO;
1810 }
1811
1812 ena_dev->reg_bar = adapter->regs;
1813 ena_dev->dmadev = adapter->pdev;
1814
1815 adapter->id_number = adapters_found;
1816
1817 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1818 adapter->id_number);
1819
1820 rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1821 if (rc != 0) {
1822 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1823 goto err;
1824 }
1825
1826 /* device specific initialization routine */
1827 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1828 if (rc) {
1829 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1830 goto err;
1831 }
1832 adapter->wd_state = wd_state;
1833
1834 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1835 adapter->use_large_llq_hdr);
1836 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1837 &get_feat_ctx.llq, &llq_config);
1838 if (unlikely(rc)) {
1839 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1840 return rc;
1841 }
1842
1843 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1844 queue_type_str = "Regular";
1845 else
1846 queue_type_str = "Low latency";
1847 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1848
1849 calc_queue_ctx.ena_dev = ena_dev;
1850 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1851
1852 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1853 rc = ena_calc_io_queue_size(&calc_queue_ctx,
1854 adapter->use_large_llq_hdr);
1855 if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1856 rc = -EFAULT;
1857 goto err_device_destroy;
1858 }
1859
1860 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1861 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1862 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1863 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1864 adapter->max_num_io_queues = max_num_io_queues;
1865
1866 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1867 disable_meta_caching =
1868 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1869 BIT(ENA_ADMIN_DISABLE_META_CACHING));
1870 } else {
1871 disable_meta_caching = false;
1872 }
1873
1874 /* prepare ring structures */
1875 ena_init_rings(adapter, disable_meta_caching);
1876
1877 ena_config_debug_area(adapter);
1878
1879 /* Set max MTU for this device */
1880 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1881
1882 /* set device support for offloads */
1883 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1884 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1885 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1886 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1887 adapter->offloads.rx_csum_supported =
1888 (get_feat_ctx.offload.rx_supported &
1889 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1890
1891 /* Copy MAC address and point DPDK to it */
1892 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1893 rte_ether_addr_copy((struct rte_ether_addr *)
1894 get_feat_ctx.dev_attr.mac_addr,
1895 (struct rte_ether_addr *)adapter->mac_addr);
1896
1897 adapter->drv_stats = rte_zmalloc("adapter stats",
1898 sizeof(*adapter->drv_stats),
1899 RTE_CACHE_LINE_SIZE);
1900 if (!adapter->drv_stats) {
1901 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1902 rc = -ENOMEM;
1903 goto err_delete_debug_area;
1904 }
1905
1906 rte_spinlock_init(&adapter->admin_lock);
1907
1908 rte_intr_callback_register(intr_handle,
1909 ena_interrupt_handler_rte,
1910 adapter);
1911 rte_intr_enable(intr_handle);
1912 ena_com_set_admin_polling_mode(ena_dev, false);
1913 ena_com_admin_aenq_enable(ena_dev);
1914
1915 if (adapters_found == 0)
1916 rte_timer_subsystem_init();
1917 rte_timer_init(&adapter->timer_wd);
1918
1919 adapters_found++;
1920 adapter->state = ENA_ADAPTER_STATE_INIT;
1921
1922 return 0;
1923
1924 err_delete_debug_area:
1925 ena_com_delete_debug_area(ena_dev);
1926
1927 err_device_destroy:
1928 ena_com_delete_host_info(ena_dev);
1929 ena_com_admin_destroy(ena_dev);
1930
1931 err:
1932 return rc;
1933 }
1934
ena_destroy_device(struct rte_eth_dev * eth_dev)1935 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1936 {
1937 struct ena_adapter *adapter = eth_dev->data->dev_private;
1938 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1939
1940 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1941 return;
1942
1943 ena_com_set_admin_running_state(ena_dev, false);
1944
1945 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1946 ena_close(eth_dev);
1947
1948 ena_com_delete_debug_area(ena_dev);
1949 ena_com_delete_host_info(ena_dev);
1950
1951 ena_com_abort_admin_commands(ena_dev);
1952 ena_com_wait_for_abort_completion(ena_dev);
1953 ena_com_admin_destroy(ena_dev);
1954 ena_com_mmio_reg_read_request_destroy(ena_dev);
1955
1956 adapter->state = ENA_ADAPTER_STATE_FREE;
1957 }
1958
eth_ena_dev_uninit(struct rte_eth_dev * eth_dev)1959 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1960 {
1961 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1962 return 0;
1963
1964 ena_destroy_device(eth_dev);
1965
1966 return 0;
1967 }
1968
ena_dev_configure(struct rte_eth_dev * dev)1969 static int ena_dev_configure(struct rte_eth_dev *dev)
1970 {
1971 struct ena_adapter *adapter = dev->data->dev_private;
1972
1973 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1974
1975 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1976 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1977 return 0;
1978 }
1979
ena_init_rings(struct ena_adapter * adapter,bool disable_meta_caching)1980 static void ena_init_rings(struct ena_adapter *adapter,
1981 bool disable_meta_caching)
1982 {
1983 size_t i;
1984
1985 for (i = 0; i < adapter->max_num_io_queues; i++) {
1986 struct ena_ring *ring = &adapter->tx_ring[i];
1987
1988 ring->configured = 0;
1989 ring->type = ENA_RING_TYPE_TX;
1990 ring->adapter = adapter;
1991 ring->id = i;
1992 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1993 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1994 ring->sgl_size = adapter->max_tx_sgl_size;
1995 ring->disable_meta_caching = disable_meta_caching;
1996 }
1997
1998 for (i = 0; i < adapter->max_num_io_queues; i++) {
1999 struct ena_ring *ring = &adapter->rx_ring[i];
2000
2001 ring->configured = 0;
2002 ring->type = ENA_RING_TYPE_RX;
2003 ring->adapter = adapter;
2004 ring->id = i;
2005 ring->sgl_size = adapter->max_rx_sgl_size;
2006 }
2007 }
2008
ena_infos_get(struct rte_eth_dev * dev,struct rte_eth_dev_info * dev_info)2009 static int ena_infos_get(struct rte_eth_dev *dev,
2010 struct rte_eth_dev_info *dev_info)
2011 {
2012 struct ena_adapter *adapter;
2013 struct ena_com_dev *ena_dev;
2014 uint64_t rx_feat = 0, tx_feat = 0;
2015
2016 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2017 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2018 adapter = dev->data->dev_private;
2019
2020 ena_dev = &adapter->ena_dev;
2021 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2022
2023 dev_info->speed_capa =
2024 ETH_LINK_SPEED_1G |
2025 ETH_LINK_SPEED_2_5G |
2026 ETH_LINK_SPEED_5G |
2027 ETH_LINK_SPEED_10G |
2028 ETH_LINK_SPEED_25G |
2029 ETH_LINK_SPEED_40G |
2030 ETH_LINK_SPEED_50G |
2031 ETH_LINK_SPEED_100G;
2032
2033 /* Set Tx & Rx features available for device */
2034 if (adapter->offloads.tso4_supported)
2035 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2036
2037 if (adapter->offloads.tx_csum_supported)
2038 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2039 DEV_TX_OFFLOAD_UDP_CKSUM |
2040 DEV_TX_OFFLOAD_TCP_CKSUM;
2041
2042 if (adapter->offloads.rx_csum_supported)
2043 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2044 DEV_RX_OFFLOAD_UDP_CKSUM |
2045 DEV_RX_OFFLOAD_TCP_CKSUM;
2046
2047 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2048
2049 /* Inform framework about available features */
2050 dev_info->rx_offload_capa = rx_feat;
2051 dev_info->rx_queue_offload_capa = rx_feat;
2052 dev_info->tx_offload_capa = tx_feat;
2053 dev_info->tx_queue_offload_capa = tx_feat;
2054
2055 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2056 ETH_RSS_UDP;
2057
2058 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2059 dev_info->max_rx_pktlen = adapter->max_mtu;
2060 dev_info->max_mac_addrs = 1;
2061
2062 dev_info->max_rx_queues = adapter->max_num_io_queues;
2063 dev_info->max_tx_queues = adapter->max_num_io_queues;
2064 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2065
2066 adapter->tx_supported_offloads = tx_feat;
2067 adapter->rx_supported_offloads = rx_feat;
2068
2069 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2070 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2071 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2072 adapter->max_rx_sgl_size);
2073 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2074 adapter->max_rx_sgl_size);
2075
2076 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2077 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2078 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2079 adapter->max_tx_sgl_size);
2080 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2081 adapter->max_tx_sgl_size);
2082
2083 return 0;
2084 }
2085
ena_init_rx_mbuf(struct rte_mbuf * mbuf,uint16_t len)2086 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2087 {
2088 mbuf->data_len = len;
2089 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2090 mbuf->refcnt = 1;
2091 mbuf->next = NULL;
2092 }
2093
ena_rx_mbuf(struct ena_ring * rx_ring,struct ena_com_rx_buf_info * ena_bufs,uint32_t descs,uint16_t * next_to_clean,uint8_t offset)2094 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2095 struct ena_com_rx_buf_info *ena_bufs,
2096 uint32_t descs,
2097 uint16_t *next_to_clean,
2098 uint8_t offset)
2099 {
2100 struct rte_mbuf *mbuf;
2101 struct rte_mbuf *mbuf_head;
2102 struct ena_rx_buffer *rx_info;
2103 int rc;
2104 uint16_t ntc, len, req_id, buf = 0;
2105
2106 if (unlikely(descs == 0))
2107 return NULL;
2108
2109 ntc = *next_to_clean;
2110
2111 len = ena_bufs[buf].len;
2112 req_id = ena_bufs[buf].req_id;
2113 if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2114 return NULL;
2115
2116 rx_info = &rx_ring->rx_buffer_info[req_id];
2117
2118 mbuf = rx_info->mbuf;
2119 RTE_ASSERT(mbuf != NULL);
2120
2121 ena_init_rx_mbuf(mbuf, len);
2122
2123 /* Fill the mbuf head with the data specific for 1st segment. */
2124 mbuf_head = mbuf;
2125 mbuf_head->nb_segs = descs;
2126 mbuf_head->port = rx_ring->port_id;
2127 mbuf_head->pkt_len = len;
2128 mbuf_head->data_off += offset;
2129
2130 rx_info->mbuf = NULL;
2131 rx_ring->empty_rx_reqs[ntc] = req_id;
2132 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2133
2134 while (--descs) {
2135 ++buf;
2136 len = ena_bufs[buf].len;
2137 req_id = ena_bufs[buf].req_id;
2138 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2139 rte_mbuf_raw_free(mbuf_head);
2140 return NULL;
2141 }
2142
2143 rx_info = &rx_ring->rx_buffer_info[req_id];
2144 RTE_ASSERT(rx_info->mbuf != NULL);
2145
2146 if (unlikely(len == 0)) {
2147 /*
2148 * Some devices can pass descriptor with the length 0.
2149 * To avoid confusion, the PMD is simply putting the
2150 * descriptor back, as it was never used. We'll avoid
2151 * mbuf allocation that way.
2152 */
2153 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2154 rx_info->mbuf, req_id);
2155 if (unlikely(rc != 0)) {
2156 /* Free the mbuf in case of an error. */
2157 rte_mbuf_raw_free(rx_info->mbuf);
2158 } else {
2159 /*
2160 * If there was no error, just exit the loop as
2161 * 0 length descriptor is always the last one.
2162 */
2163 break;
2164 }
2165 } else {
2166 /* Create an mbuf chain. */
2167 mbuf->next = rx_info->mbuf;
2168 mbuf = mbuf->next;
2169
2170 ena_init_rx_mbuf(mbuf, len);
2171 mbuf_head->pkt_len += len;
2172 }
2173
2174 /*
2175 * Mark the descriptor as depleted and perform necessary
2176 * cleanup.
2177 * This code will execute in two cases:
2178 * 1. Descriptor len was greater than 0 - normal situation.
2179 * 2. Descriptor len was 0 and we failed to add the descriptor
2180 * to the device. In that situation, we should try to add
2181 * the mbuf again in the populate routine and mark the
2182 * descriptor as used up by the device.
2183 */
2184 rx_info->mbuf = NULL;
2185 rx_ring->empty_rx_reqs[ntc] = req_id;
2186 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2187 }
2188
2189 *next_to_clean = ntc;
2190
2191 return mbuf_head;
2192 }
2193
eth_ena_recv_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)2194 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2195 uint16_t nb_pkts)
2196 {
2197 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2198 unsigned int free_queue_entries;
2199 unsigned int refill_threshold;
2200 uint16_t next_to_clean = rx_ring->next_to_clean;
2201 uint16_t descs_in_use;
2202 struct rte_mbuf *mbuf;
2203 uint16_t completed;
2204 struct ena_com_rx_ctx ena_rx_ctx;
2205 int i, rc = 0;
2206
2207 /* Check adapter state */
2208 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2209 PMD_DRV_LOG(ALERT,
2210 "Trying to receive pkts while device is NOT running\n");
2211 return 0;
2212 }
2213
2214 descs_in_use = rx_ring->ring_size -
2215 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2216 nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2217
2218 for (completed = 0; completed < nb_pkts; completed++) {
2219 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2220 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2221 ena_rx_ctx.descs = 0;
2222 ena_rx_ctx.pkt_offset = 0;
2223 /* receive packet context */
2224 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2225 rx_ring->ena_com_io_sq,
2226 &ena_rx_ctx);
2227 if (unlikely(rc)) {
2228 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2229 rx_ring->adapter->reset_reason =
2230 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2231 rx_ring->adapter->trigger_reset = true;
2232 ++rx_ring->rx_stats.bad_desc_num;
2233 return 0;
2234 }
2235
2236 mbuf = ena_rx_mbuf(rx_ring,
2237 ena_rx_ctx.ena_bufs,
2238 ena_rx_ctx.descs,
2239 &next_to_clean,
2240 ena_rx_ctx.pkt_offset);
2241 if (unlikely(mbuf == NULL)) {
2242 for (i = 0; i < ena_rx_ctx.descs; ++i) {
2243 rx_ring->empty_rx_reqs[next_to_clean] =
2244 rx_ring->ena_bufs[i].req_id;
2245 next_to_clean = ENA_IDX_NEXT_MASKED(
2246 next_to_clean, rx_ring->size_mask);
2247 }
2248 break;
2249 }
2250
2251 /* fill mbuf attributes if any */
2252 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2253
2254 if (unlikely(mbuf->ol_flags &
2255 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2256 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2257 ++rx_ring->rx_stats.bad_csum;
2258 }
2259
2260 mbuf->hash.rss = ena_rx_ctx.hash;
2261
2262 rx_pkts[completed] = mbuf;
2263 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2264 }
2265
2266 rx_ring->rx_stats.cnt += completed;
2267 rx_ring->next_to_clean = next_to_clean;
2268
2269 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2270 refill_threshold =
2271 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2272 (unsigned int)ENA_REFILL_THRESH_PACKET);
2273
2274 /* Burst refill to save doorbells, memory barriers, const interval */
2275 if (free_queue_entries > refill_threshold) {
2276 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2277 ena_populate_rx_queue(rx_ring, free_queue_entries);
2278 }
2279
2280 return completed;
2281 }
2282
2283 static uint16_t
eth_ena_prep_pkts(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)2284 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2285 uint16_t nb_pkts)
2286 {
2287 int32_t ret;
2288 uint32_t i;
2289 struct rte_mbuf *m;
2290 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2291 struct rte_ipv4_hdr *ip_hdr;
2292 uint64_t ol_flags;
2293 uint16_t frag_field;
2294
2295 for (i = 0; i != nb_pkts; i++) {
2296 m = tx_pkts[i];
2297 ol_flags = m->ol_flags;
2298
2299 if (!(ol_flags & PKT_TX_IPV4))
2300 continue;
2301
2302 /* If there was not L2 header length specified, assume it is
2303 * length of the ethernet header.
2304 */
2305 if (unlikely(m->l2_len == 0))
2306 m->l2_len = sizeof(struct rte_ether_hdr);
2307
2308 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2309 m->l2_len);
2310 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2311
2312 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2313 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2314
2315 /* If IPv4 header has DF flag enabled and TSO support is
2316 * disabled, partial chcecksum should not be calculated.
2317 */
2318 if (!tx_ring->adapter->offloads.tso4_supported)
2319 continue;
2320 }
2321
2322 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2323 (ol_flags & PKT_TX_L4_MASK) ==
2324 PKT_TX_SCTP_CKSUM) {
2325 rte_errno = ENOTSUP;
2326 return i;
2327 }
2328
2329 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2330 ret = rte_validate_tx_offload(m);
2331 if (ret != 0) {
2332 rte_errno = -ret;
2333 return i;
2334 }
2335 #endif
2336
2337 /* In case we are supposed to TSO and have DF not set (DF=0)
2338 * hardware must be provided with partial checksum, otherwise
2339 * it will take care of necessary calculations.
2340 */
2341
2342 ret = rte_net_intel_cksum_flags_prepare(m,
2343 ol_flags & ~PKT_TX_TCP_SEG);
2344 if (ret != 0) {
2345 rte_errno = -ret;
2346 return i;
2347 }
2348 }
2349
2350 return i;
2351 }
2352
ena_update_hints(struct ena_adapter * adapter,struct ena_admin_ena_hw_hints * hints)2353 static void ena_update_hints(struct ena_adapter *adapter,
2354 struct ena_admin_ena_hw_hints *hints)
2355 {
2356 if (hints->admin_completion_tx_timeout)
2357 adapter->ena_dev.admin_queue.completion_timeout =
2358 hints->admin_completion_tx_timeout * 1000;
2359
2360 if (hints->mmio_read_timeout)
2361 /* convert to usec */
2362 adapter->ena_dev.mmio_read.reg_read_to =
2363 hints->mmio_read_timeout * 1000;
2364
2365 if (hints->driver_watchdog_timeout) {
2366 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2367 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2368 else
2369 // Convert msecs to ticks
2370 adapter->keep_alive_timeout =
2371 (hints->driver_watchdog_timeout *
2372 rte_get_timer_hz()) / 1000;
2373 }
2374 }
2375
ena_check_and_linearize_mbuf(struct ena_ring * tx_ring,struct rte_mbuf * mbuf)2376 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2377 struct rte_mbuf *mbuf)
2378 {
2379 struct ena_com_dev *ena_dev;
2380 int num_segments, header_len, rc;
2381
2382 ena_dev = &tx_ring->adapter->ena_dev;
2383 num_segments = mbuf->nb_segs;
2384 header_len = mbuf->data_len;
2385
2386 if (likely(num_segments < tx_ring->sgl_size))
2387 return 0;
2388
2389 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2390 (num_segments == tx_ring->sgl_size) &&
2391 (header_len < tx_ring->tx_max_header_size))
2392 return 0;
2393
2394 ++tx_ring->tx_stats.linearize;
2395 rc = rte_pktmbuf_linearize(mbuf);
2396 if (unlikely(rc)) {
2397 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2398 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2399 ++tx_ring->tx_stats.linearize_failed;
2400 return rc;
2401 }
2402
2403 return rc;
2404 }
2405
ena_tx_map_mbuf(struct ena_ring * tx_ring,struct ena_tx_buffer * tx_info,struct rte_mbuf * mbuf,void ** push_header,uint16_t * header_len)2406 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2407 struct ena_tx_buffer *tx_info,
2408 struct rte_mbuf *mbuf,
2409 void **push_header,
2410 uint16_t *header_len)
2411 {
2412 struct ena_com_buf *ena_buf;
2413 uint16_t delta, seg_len, push_len;
2414
2415 delta = 0;
2416 seg_len = mbuf->data_len;
2417
2418 tx_info->mbuf = mbuf;
2419 ena_buf = tx_info->bufs;
2420
2421 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2422 /*
2423 * Tx header might be (and will be in most cases) smaller than
2424 * tx_max_header_size. But it's not an issue to send more data
2425 * to the device, than actually needed if the mbuf size is
2426 * greater than tx_max_header_size.
2427 */
2428 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2429 *header_len = push_len;
2430
2431 if (likely(push_len <= seg_len)) {
2432 /* If the push header is in the single segment, then
2433 * just point it to the 1st mbuf data.
2434 */
2435 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2436 } else {
2437 /* If the push header lays in the several segments, copy
2438 * it to the intermediate buffer.
2439 */
2440 rte_pktmbuf_read(mbuf, 0, push_len,
2441 tx_ring->push_buf_intermediate_buf);
2442 *push_header = tx_ring->push_buf_intermediate_buf;
2443 delta = push_len - seg_len;
2444 }
2445 } else {
2446 *push_header = NULL;
2447 *header_len = 0;
2448 push_len = 0;
2449 }
2450
2451 /* Process first segment taking into consideration pushed header */
2452 if (seg_len > push_len) {
2453 ena_buf->paddr = mbuf->buf_iova +
2454 mbuf->data_off +
2455 push_len;
2456 ena_buf->len = seg_len - push_len;
2457 ena_buf++;
2458 tx_info->num_of_bufs++;
2459 }
2460
2461 while ((mbuf = mbuf->next) != NULL) {
2462 seg_len = mbuf->data_len;
2463
2464 /* Skip mbufs if whole data is pushed as a header */
2465 if (unlikely(delta > seg_len)) {
2466 delta -= seg_len;
2467 continue;
2468 }
2469
2470 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2471 ena_buf->len = seg_len - delta;
2472 ena_buf++;
2473 tx_info->num_of_bufs++;
2474
2475 delta = 0;
2476 }
2477 }
2478
ena_xmit_mbuf(struct ena_ring * tx_ring,struct rte_mbuf * mbuf)2479 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2480 {
2481 struct ena_tx_buffer *tx_info;
2482 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2483 uint16_t next_to_use;
2484 uint16_t header_len;
2485 uint16_t req_id;
2486 void *push_header;
2487 int nb_hw_desc;
2488 int rc;
2489
2490 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2491 if (unlikely(rc))
2492 return rc;
2493
2494 next_to_use = tx_ring->next_to_use;
2495
2496 req_id = tx_ring->empty_tx_reqs[next_to_use];
2497 tx_info = &tx_ring->tx_buffer_info[req_id];
2498 tx_info->num_of_bufs = 0;
2499
2500 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2501
2502 ena_tx_ctx.ena_bufs = tx_info->bufs;
2503 ena_tx_ctx.push_header = push_header;
2504 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2505 ena_tx_ctx.req_id = req_id;
2506 ena_tx_ctx.header_len = header_len;
2507
2508 /* Set Tx offloads flags, if applicable */
2509 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2510 tx_ring->disable_meta_caching);
2511
2512 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2513 &ena_tx_ctx))) {
2514 PMD_DRV_LOG(DEBUG,
2515 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2516 tx_ring->id);
2517 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2518 }
2519
2520 /* prepare the packet's descriptors to dma engine */
2521 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2522 &nb_hw_desc);
2523 if (unlikely(rc)) {
2524 ++tx_ring->tx_stats.prepare_ctx_err;
2525 return rc;
2526 }
2527
2528 tx_info->tx_descs = nb_hw_desc;
2529
2530 tx_ring->tx_stats.cnt++;
2531 tx_ring->tx_stats.bytes += mbuf->pkt_len;
2532
2533 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2534 tx_ring->size_mask);
2535
2536 return 0;
2537 }
2538
ena_tx_cleanup(struct ena_ring * tx_ring)2539 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2540 {
2541 unsigned int cleanup_budget;
2542 unsigned int total_tx_descs = 0;
2543 uint16_t next_to_clean = tx_ring->next_to_clean;
2544
2545 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2546 (unsigned int)ENA_REFILL_THRESH_PACKET);
2547
2548 while (likely(total_tx_descs < cleanup_budget)) {
2549 struct rte_mbuf *mbuf;
2550 struct ena_tx_buffer *tx_info;
2551 uint16_t req_id;
2552
2553 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2554 break;
2555
2556 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2557 break;
2558
2559 /* Get Tx info & store how many descs were processed */
2560 tx_info = &tx_ring->tx_buffer_info[req_id];
2561
2562 mbuf = tx_info->mbuf;
2563 rte_pktmbuf_free(mbuf);
2564
2565 tx_info->mbuf = NULL;
2566 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2567
2568 total_tx_descs += tx_info->tx_descs;
2569
2570 /* Put back descriptor to the ring for reuse */
2571 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2572 tx_ring->size_mask);
2573 }
2574
2575 if (likely(total_tx_descs > 0)) {
2576 /* acknowledge completion of sent packets */
2577 tx_ring->next_to_clean = next_to_clean;
2578 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2579 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2580 }
2581 }
2582
eth_ena_xmit_pkts(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)2583 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2584 uint16_t nb_pkts)
2585 {
2586 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2587 uint16_t sent_idx = 0;
2588
2589 /* Check adapter state */
2590 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2591 PMD_DRV_LOG(ALERT,
2592 "Trying to xmit pkts while device is NOT running\n");
2593 return 0;
2594 }
2595
2596 nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2597 nb_pkts);
2598
2599 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2600 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2601 break;
2602
2603 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2604 tx_ring->size_mask)]);
2605 }
2606
2607 tx_ring->tx_stats.available_desc =
2608 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2609
2610 /* If there are ready packets to be xmitted... */
2611 if (sent_idx > 0) {
2612 /* ...let HW do its best :-) */
2613 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2614 tx_ring->tx_stats.doorbells++;
2615 }
2616
2617 ena_tx_cleanup(tx_ring);
2618
2619 tx_ring->tx_stats.available_desc =
2620 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2621 tx_ring->tx_stats.tx_poll++;
2622
2623 return sent_idx;
2624 }
2625
ena_copy_eni_stats(struct ena_adapter * adapter)2626 int ena_copy_eni_stats(struct ena_adapter *adapter)
2627 {
2628 struct ena_admin_eni_stats admin_eni_stats;
2629 int rc;
2630
2631 rte_spinlock_lock(&adapter->admin_lock);
2632 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2633 rte_spinlock_unlock(&adapter->admin_lock);
2634 if (rc != 0) {
2635 if (rc == ENA_COM_UNSUPPORTED) {
2636 PMD_DRV_LOG(DEBUG,
2637 "Retrieving ENI metrics is not supported.\n");
2638 } else {
2639 PMD_DRV_LOG(WARNING,
2640 "Failed to get ENI metrics: %d\n", rc);
2641 }
2642 return rc;
2643 }
2644
2645 rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2646 sizeof(struct ena_stats_eni));
2647
2648 return 0;
2649 }
2650
2651 /**
2652 * DPDK callback to retrieve names of extended device statistics
2653 *
2654 * @param dev
2655 * Pointer to Ethernet device structure.
2656 * @param[out] xstats_names
2657 * Buffer to insert names into.
2658 * @param n
2659 * Number of names.
2660 *
2661 * @return
2662 * Number of xstats names.
2663 */
ena_xstats_get_names(struct rte_eth_dev * dev,struct rte_eth_xstat_name * xstats_names,unsigned int n)2664 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2665 struct rte_eth_xstat_name *xstats_names,
2666 unsigned int n)
2667 {
2668 unsigned int xstats_count = ena_xstats_calc_num(dev);
2669 unsigned int stat, i, count = 0;
2670
2671 if (n < xstats_count || !xstats_names)
2672 return xstats_count;
2673
2674 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2675 strcpy(xstats_names[count].name,
2676 ena_stats_global_strings[stat].name);
2677
2678 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2679 strcpy(xstats_names[count].name,
2680 ena_stats_eni_strings[stat].name);
2681
2682 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2683 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2684 snprintf(xstats_names[count].name,
2685 sizeof(xstats_names[count].name),
2686 "rx_q%d_%s", i,
2687 ena_stats_rx_strings[stat].name);
2688
2689 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2690 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2691 snprintf(xstats_names[count].name,
2692 sizeof(xstats_names[count].name),
2693 "tx_q%d_%s", i,
2694 ena_stats_tx_strings[stat].name);
2695
2696 return xstats_count;
2697 }
2698
2699 /**
2700 * DPDK callback to get extended device statistics.
2701 *
2702 * @param dev
2703 * Pointer to Ethernet device structure.
2704 * @param[out] stats
2705 * Stats table output buffer.
2706 * @param n
2707 * The size of the stats table.
2708 *
2709 * @return
2710 * Number of xstats on success, negative on failure.
2711 */
ena_xstats_get(struct rte_eth_dev * dev,struct rte_eth_xstat * xstats,unsigned int n)2712 static int ena_xstats_get(struct rte_eth_dev *dev,
2713 struct rte_eth_xstat *xstats,
2714 unsigned int n)
2715 {
2716 struct ena_adapter *adapter = dev->data->dev_private;
2717 unsigned int xstats_count = ena_xstats_calc_num(dev);
2718 unsigned int stat, i, count = 0;
2719 int stat_offset;
2720 void *stats_begin;
2721
2722 if (n < xstats_count)
2723 return xstats_count;
2724
2725 if (!xstats)
2726 return 0;
2727
2728 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2729 stat_offset = ena_stats_global_strings[stat].stat_offset;
2730 stats_begin = &adapter->dev_stats;
2731
2732 xstats[count].id = count;
2733 xstats[count].value = *((uint64_t *)
2734 ((char *)stats_begin + stat_offset));
2735 }
2736
2737 /* Even if the function below fails, we should copy previous (or initial
2738 * values) to keep structure of rte_eth_xstat consistent.
2739 */
2740 ena_copy_eni_stats(adapter);
2741 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2742 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2743 stats_begin = &adapter->eni_stats;
2744
2745 xstats[count].id = count;
2746 xstats[count].value = *((uint64_t *)
2747 ((char *)stats_begin + stat_offset));
2748 }
2749
2750 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2751 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2752 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2753 stats_begin = &adapter->rx_ring[i].rx_stats;
2754
2755 xstats[count].id = count;
2756 xstats[count].value = *((uint64_t *)
2757 ((char *)stats_begin + stat_offset));
2758 }
2759 }
2760
2761 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2762 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2763 stat_offset = ena_stats_tx_strings[stat].stat_offset;
2764 stats_begin = &adapter->tx_ring[i].rx_stats;
2765
2766 xstats[count].id = count;
2767 xstats[count].value = *((uint64_t *)
2768 ((char *)stats_begin + stat_offset));
2769 }
2770 }
2771
2772 return count;
2773 }
2774
ena_xstats_get_by_id(struct rte_eth_dev * dev,const uint64_t * ids,uint64_t * values,unsigned int n)2775 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2776 const uint64_t *ids,
2777 uint64_t *values,
2778 unsigned int n)
2779 {
2780 struct ena_adapter *adapter = dev->data->dev_private;
2781 uint64_t id;
2782 uint64_t rx_entries, tx_entries;
2783 unsigned int i;
2784 int qid;
2785 int valid = 0;
2786 bool was_eni_copied = false;
2787
2788 for (i = 0; i < n; ++i) {
2789 id = ids[i];
2790 /* Check if id belongs to global statistics */
2791 if (id < ENA_STATS_ARRAY_GLOBAL) {
2792 values[i] = *((uint64_t *)&adapter->dev_stats + id);
2793 ++valid;
2794 continue;
2795 }
2796
2797 /* Check if id belongs to ENI statistics */
2798 id -= ENA_STATS_ARRAY_GLOBAL;
2799 if (id < ENA_STATS_ARRAY_ENI) {
2800 /* Avoid reading ENI stats multiple times in a single
2801 * function call, as it requires communication with the
2802 * admin queue.
2803 */
2804 if (!was_eni_copied) {
2805 was_eni_copied = true;
2806 ena_copy_eni_stats(adapter);
2807 }
2808 values[i] = *((uint64_t *)&adapter->eni_stats + id);
2809 ++valid;
2810 continue;
2811 }
2812
2813 /* Check if id belongs to rx queue statistics */
2814 id -= ENA_STATS_ARRAY_ENI;
2815 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2816 if (id < rx_entries) {
2817 qid = id % dev->data->nb_rx_queues;
2818 id /= dev->data->nb_rx_queues;
2819 values[i] = *((uint64_t *)
2820 &adapter->rx_ring[qid].rx_stats + id);
2821 ++valid;
2822 continue;
2823 }
2824 /* Check if id belongs to rx queue statistics */
2825 id -= rx_entries;
2826 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2827 if (id < tx_entries) {
2828 qid = id % dev->data->nb_tx_queues;
2829 id /= dev->data->nb_tx_queues;
2830 values[i] = *((uint64_t *)
2831 &adapter->tx_ring[qid].tx_stats + id);
2832 ++valid;
2833 continue;
2834 }
2835 }
2836
2837 return valid;
2838 }
2839
ena_process_bool_devarg(const char * key,const char * value,void * opaque)2840 static int ena_process_bool_devarg(const char *key,
2841 const char *value,
2842 void *opaque)
2843 {
2844 struct ena_adapter *adapter = opaque;
2845 bool bool_value;
2846
2847 /* Parse the value. */
2848 if (strcmp(value, "1") == 0) {
2849 bool_value = true;
2850 } else if (strcmp(value, "0") == 0) {
2851 bool_value = false;
2852 } else {
2853 PMD_INIT_LOG(ERR,
2854 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2855 value, key);
2856 return -EINVAL;
2857 }
2858
2859 /* Now, assign it to the proper adapter field. */
2860 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2861 adapter->use_large_llq_hdr = bool_value;
2862
2863 return 0;
2864 }
2865
ena_parse_devargs(struct ena_adapter * adapter,struct rte_devargs * devargs)2866 static int ena_parse_devargs(struct ena_adapter *adapter,
2867 struct rte_devargs *devargs)
2868 {
2869 static const char * const allowed_args[] = {
2870 ENA_DEVARG_LARGE_LLQ_HDR,
2871 };
2872 struct rte_kvargs *kvlist;
2873 int rc;
2874
2875 if (devargs == NULL)
2876 return 0;
2877
2878 kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2879 if (kvlist == NULL) {
2880 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2881 devargs->args);
2882 return -EINVAL;
2883 }
2884
2885 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2886 ena_process_bool_devarg, adapter);
2887
2888 rte_kvargs_free(kvlist);
2889
2890 return rc;
2891 }
2892
2893 /*********************************************************************
2894 * PMD configuration
2895 *********************************************************************/
eth_ena_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)2896 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2897 struct rte_pci_device *pci_dev)
2898 {
2899 return rte_eth_dev_pci_generic_probe(pci_dev,
2900 sizeof(struct ena_adapter), eth_ena_dev_init);
2901 }
2902
eth_ena_pci_remove(struct rte_pci_device * pci_dev)2903 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2904 {
2905 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2906 }
2907
2908 static struct rte_pci_driver rte_ena_pmd = {
2909 .id_table = pci_id_ena_map,
2910 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2911 RTE_PCI_DRV_WC_ACTIVATE,
2912 .probe = eth_ena_pci_probe,
2913 .remove = eth_ena_pci_remove,
2914 };
2915
2916 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2917 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2918 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2919 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2920 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE);
2921 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE);
2922 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2923 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE);
2924 #endif
2925 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2926 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE);
2927 #endif
2928 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2929 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE);
2930 #endif
2931 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2932 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE);
2933 #endif
2934
2935 /******************************************************************************
2936 ******************************** AENQ Handlers *******************************
2937 *****************************************************************************/
ena_update_on_link_change(void * adapter_data,struct ena_admin_aenq_entry * aenq_e)2938 static void ena_update_on_link_change(void *adapter_data,
2939 struct ena_admin_aenq_entry *aenq_e)
2940 {
2941 struct rte_eth_dev *eth_dev;
2942 struct ena_adapter *adapter;
2943 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2944 uint32_t status;
2945
2946 adapter = adapter_data;
2947 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2948 eth_dev = adapter->rte_dev;
2949
2950 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2951 adapter->link_status = status;
2952
2953 ena_link_update(eth_dev, 0);
2954 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2955 }
2956
ena_notification(void * data,struct ena_admin_aenq_entry * aenq_e)2957 static void ena_notification(void *data,
2958 struct ena_admin_aenq_entry *aenq_e)
2959 {
2960 struct ena_adapter *adapter = data;
2961 struct ena_admin_ena_hw_hints *hints;
2962
2963 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2964 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2965 aenq_e->aenq_common_desc.group,
2966 ENA_ADMIN_NOTIFICATION);
2967
2968 switch (aenq_e->aenq_common_desc.syndrom) {
2969 case ENA_ADMIN_UPDATE_HINTS:
2970 hints = (struct ena_admin_ena_hw_hints *)
2971 (&aenq_e->inline_data_w4);
2972 ena_update_hints(adapter, hints);
2973 break;
2974 default:
2975 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2976 aenq_e->aenq_common_desc.syndrom);
2977 }
2978 }
2979
ena_keep_alive(void * adapter_data,__rte_unused struct ena_admin_aenq_entry * aenq_e)2980 static void ena_keep_alive(void *adapter_data,
2981 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2982 {
2983 struct ena_adapter *adapter = adapter_data;
2984 struct ena_admin_aenq_keep_alive_desc *desc;
2985 uint64_t rx_drops;
2986 uint64_t tx_drops;
2987
2988 adapter->timestamp_wd = rte_get_timer_cycles();
2989
2990 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2991 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2992 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2993
2994 adapter->drv_stats->rx_drops = rx_drops;
2995 adapter->dev_stats.tx_drops = tx_drops;
2996 }
2997
2998 /**
2999 * This handler will called for unknown event group or unimplemented handlers
3000 **/
unimplemented_aenq_handler(__rte_unused void * data,__rte_unused struct ena_admin_aenq_entry * aenq_e)3001 static void unimplemented_aenq_handler(__rte_unused void *data,
3002 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3003 {
3004 PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3005 "unimplemented handler\n");
3006 }
3007
3008 static struct ena_aenq_handlers aenq_handlers = {
3009 .handlers = {
3010 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3011 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3012 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3013 },
3014 .unimplemented_handler = unimplemented_aenq_handler
3015 };
3016