1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _ICE_ACL_H_ 6 #define _ICE_ACL_H_ 7 8 #include "ice_common.h" 9 #include "ice_adminq_cmd.h" 10 11 struct ice_acl_tbl_params { 12 u16 width; /* Select/match bytes */ 13 u16 depth; /* Number of entries */ 14 15 #define ICE_ACL_TBL_MAX_DEP_TBLS 15 16 u16 dep_tbls[ICE_ACL_TBL_MAX_DEP_TBLS]; 17 18 u8 entry_act_pairs; /* Action pairs per entry */ 19 u8 concurr; /* Concurrent table lookup enable */ 20 }; 21 22 struct ice_acl_act_mem { 23 u8 act_mem; 24 #define ICE_ACL_ACT_PAIR_MEM_INVAL 0xff 25 u8 member_of_tcam; 26 }; 27 28 struct ice_acl_tbl { 29 /* TCAM configuration */ 30 u8 first_tcam; /* Index of the first TCAM block */ 31 u8 last_tcam; /* Index of the last TCAM block */ 32 /* Index of the first entry in the first TCAM */ 33 u16 first_entry; 34 /* Index of the last entry in the last TCAM */ 35 u16 last_entry; 36 37 /* List of active scenarios */ 38 struct LIST_HEAD_TYPE scens; 39 40 struct ice_acl_tbl_params info; 41 struct ice_acl_act_mem act_mems[ICE_AQC_MAX_ACTION_MEMORIES]; 42 43 /* Keep track of available 64-entry chunks in TCAMs */ 44 ice_declare_bitmap(avail, ICE_AQC_ACL_ALLOC_UNITS); 45 46 u16 id; 47 }; 48 49 #define ICE_MAX_ACL_TCAM_ENTRY (ICE_AQC_ACL_TCAM_DEPTH * ICE_AQC_ACL_SLICES) 50 enum ice_acl_entry_prio { 51 ICE_ACL_PRIO_LOW = 0, 52 ICE_ACL_PRIO_NORMAL, 53 ICE_ACL_PRIO_HIGH, 54 ICE_ACL_MAX_PRIO 55 }; 56 57 /* Scenario structure 58 * A scenario is a logical partition within an ACL table. It can span more 59 * than one TCAM in cascade mode to support select/mask key widths larger. 60 * than the width of a TCAM. It can also span more than one TCAM in stacked 61 * mode to support larger number of entries than what a TCAM can hold. It is 62 * used to select values from selection bases (field vectors holding extract 63 * protocol header fields) to form lookup keys, and to associate action memory 64 * banks to the TCAMs used. 65 */ 66 struct ice_acl_scen { 67 struct LIST_ENTRY_TYPE list_entry; 68 /* If nth bit of act_mem_bitmap is set, then nth action memory will 69 * participate in this scenario 70 */ 71 ice_declare_bitmap(act_mem_bitmap, ICE_AQC_MAX_ACTION_MEMORIES); 72 73 /* If nth bit of entry_bitmap is set, then nth entry will 74 * be available in this scenario 75 */ 76 ice_declare_bitmap(entry_bitmap, ICE_MAX_ACL_TCAM_ENTRY); 77 u16 first_idx[ICE_ACL_MAX_PRIO]; 78 u16 last_idx[ICE_ACL_MAX_PRIO]; 79 80 u16 id; 81 u16 start; /* Number of entry from the start of the parent table */ 82 #define ICE_ACL_SCEN_MIN_WIDTH 0x3 83 u16 width; /* Number of select/mask bytes */ 84 u16 num_entry; /* Number of scenario entry */ 85 u16 end; /* Last addressable entry from start of table */ 86 u8 eff_width; /* Available width in bytes to match */ 87 #define ICE_ACL_SCEN_PKT_DIR_IDX_IN_TCAM 0x2 88 #define ICE_ACL_SCEN_PID_IDX_IN_TCAM 0x3 89 #define ICE_ACL_SCEN_RNG_CHK_IDX_IN_TCAM 0x4 90 u8 pid_idx; /* Byte index used to match profile ID */ 91 u8 rng_chk_idx; /* Byte index used to match range checkers result */ 92 u8 pkt_dir_idx; /* Byte index used to match packet direction */ 93 }; 94 95 /* This structure represents input fields needed to allocate ACL table */ 96 struct ice_acl_alloc_tbl { 97 /* Table's width in number of bytes matched */ 98 u16 width; 99 /* Table's depth in number of entries. */ 100 u16 depth; 101 u8 num_dependent_alloc_ids; /* number of depdendent alloc IDs */ 102 u8 concurr; /* true for concurrent table type */ 103 104 /* Amount of action pairs per table entry. Minimal valid 105 * value for this field is 1 (e.g. single pair of actions) 106 */ 107 u8 act_pairs_per_entry; 108 union { 109 struct ice_aqc_acl_alloc_table_data data_buf; 110 struct ice_aqc_acl_generic resp_buf; 111 } buf; 112 }; 113 114 /* This structure is used to communicate input and output params for 115 * [de]allocate_acl_counters 116 */ 117 struct ice_acl_cntrs { 118 u8 amount; 119 u8 type; 120 u8 bank; 121 122 /* Next 2 variables are used for output in case of alloc_acl_counters 123 * and input in case of deallocate_acl_counters 124 */ 125 u16 first_cntr; 126 u16 last_cntr; 127 }; 128 129 enum ice_status 130 ice_acl_create_tbl(struct ice_hw *hw, struct ice_acl_tbl_params *params); 131 enum ice_status ice_acl_destroy_tbl(struct ice_hw *hw); 132 enum ice_status 133 ice_acl_create_scen(struct ice_hw *hw, u16 match_width, u16 num_entries, 134 u16 *scen_id); 135 enum ice_status 136 ice_aq_alloc_acl_tbl(struct ice_hw *hw, struct ice_acl_alloc_tbl *tbl, 137 struct ice_sq_cd *cd); 138 enum ice_status 139 ice_aq_dealloc_acl_tbl(struct ice_hw *hw, u16 alloc_id, 140 struct ice_aqc_acl_generic *buf, struct ice_sq_cd *cd); 141 enum ice_status 142 ice_aq_program_acl_entry(struct ice_hw *hw, u8 tcam_idx, u16 entry_idx, 143 struct ice_aqc_acl_data *buf, struct ice_sq_cd *cd); 144 enum ice_status 145 ice_aq_query_acl_entry(struct ice_hw *hw, u8 tcam_idx, u16 entry_idx, 146 struct ice_aqc_acl_data *buf, struct ice_sq_cd *cd); 147 enum ice_status 148 ice_aq_alloc_actpair(struct ice_hw *hw, u16 alloc_id, 149 struct ice_aqc_acl_generic *buf, struct ice_sq_cd *cd); 150 enum ice_status 151 ice_aq_dealloc_actpair(struct ice_hw *hw, u16 alloc_id, 152 struct ice_aqc_acl_generic *buf, struct ice_sq_cd *cd); 153 enum ice_status 154 ice_aq_program_actpair(struct ice_hw *hw, u8 act_mem_idx, u16 act_entry_idx, 155 struct ice_aqc_actpair *buf, struct ice_sq_cd *cd); 156 enum ice_status 157 ice_aq_query_actpair(struct ice_hw *hw, u8 act_mem_idx, u16 act_entry_idx, 158 struct ice_aqc_actpair *buf, struct ice_sq_cd *cd); 159 enum ice_status ice_aq_dealloc_acl_res(struct ice_hw *hw, struct ice_sq_cd *cd); 160 enum ice_status 161 ice_prgm_acl_prof_xtrct(struct ice_hw *hw, u8 prof_id, 162 struct ice_aqc_acl_prof_generic_frmt *buf, 163 struct ice_sq_cd *cd); 164 enum ice_status 165 ice_query_acl_prof(struct ice_hw *hw, u8 prof_id, 166 struct ice_aqc_acl_prof_generic_frmt *buf, 167 struct ice_sq_cd *cd); 168 enum ice_status 169 ice_aq_alloc_acl_cntrs(struct ice_hw *hw, struct ice_acl_cntrs *cntrs, 170 struct ice_sq_cd *cd); 171 enum ice_status 172 ice_aq_dealloc_acl_cntrs(struct ice_hw *hw, struct ice_acl_cntrs *cntrs, 173 struct ice_sq_cd *cd); 174 enum ice_status 175 ice_prog_acl_prof_ranges(struct ice_hw *hw, u8 prof_id, 176 struct ice_aqc_acl_profile_ranges *buf, 177 struct ice_sq_cd *cd); 178 enum ice_status 179 ice_query_acl_prof_ranges(struct ice_hw *hw, u8 prof_id, 180 struct ice_aqc_acl_profile_ranges *buf, 181 struct ice_sq_cd *cd); 182 enum ice_status 183 ice_aq_alloc_acl_scen(struct ice_hw *hw, u16 *scen_id, 184 struct ice_aqc_acl_scen *buf, struct ice_sq_cd *cd); 185 enum ice_status 186 ice_aq_dealloc_acl_scen(struct ice_hw *hw, u16 scen_id, struct ice_sq_cd *cd); 187 enum ice_status 188 ice_aq_update_acl_scen(struct ice_hw *hw, u16 scen_id, 189 struct ice_aqc_acl_scen *buf, struct ice_sq_cd *cd); 190 enum ice_status 191 ice_aq_query_acl_scen(struct ice_hw *hw, u16 scen_id, 192 struct ice_aqc_acl_scen *buf, struct ice_sq_cd *cd); 193 enum ice_status 194 ice_acl_add_entry(struct ice_hw *hw, struct ice_acl_scen *scen, 195 enum ice_acl_entry_prio prio, u8 *keys, u8 *inverts, 196 struct ice_acl_act_entry *acts, u8 acts_cnt, u16 *entry_idx); 197 enum ice_status 198 ice_acl_prog_act(struct ice_hw *hw, struct ice_acl_scen *scen, 199 struct ice_acl_act_entry *acts, u8 acts_cnt, u16 entry_idx); 200 enum ice_status 201 ice_acl_rem_entry(struct ice_hw *hw, struct ice_acl_scen *scen, u16 entry_idx); 202 #endif /* _ICE_ACL_H_ */ 203