1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
5 */
6
7 #include "efx.h"
8 #include "efx_impl.h"
9
10
11 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
12
13 __checkReturn efx_rc_t
ef10_mac_poll(__in efx_nic_t * enp,__out efx_link_mode_t * link_modep)14 ef10_mac_poll(
15 __in efx_nic_t *enp,
16 __out efx_link_mode_t *link_modep)
17 {
18 efx_port_t *epp = &(enp->en_port);
19 ef10_link_state_t els;
20 efx_rc_t rc;
21
22 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
23 goto fail1;
24
25 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
26 epp->ep_fcntl = els.epls.epls_fcntl;
27
28 *link_modep = els.epls.epls_link_mode;
29
30 return (0);
31
32 fail1:
33 EFSYS_PROBE1(fail1, efx_rc_t, rc);
34
35 *link_modep = EFX_LINK_UNKNOWN;
36
37 return (rc);
38 }
39
40 __checkReturn efx_rc_t
ef10_mac_up(__in efx_nic_t * enp,__out boolean_t * mac_upp)41 ef10_mac_up(
42 __in efx_nic_t *enp,
43 __out boolean_t *mac_upp)
44 {
45 ef10_link_state_t els;
46 efx_rc_t rc;
47
48 /*
49 * Because EF10 doesn't *require* polling, we can't rely on
50 * ef10_mac_poll() being executed to populate epp->ep_mac_up.
51 */
52 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
53 goto fail1;
54
55 *mac_upp = els.els_mac_up;
56
57 return (0);
58
59 fail1:
60 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61
62 return (rc);
63 }
64
65 /*
66 * EF10 adapters use MC_CMD_VADAPTOR_SET_MAC to set the
67 * MAC address; the address field in MC_CMD_SET_MAC has no
68 * effect.
69 * MC_CMD_VADAPTOR_SET_MAC requires mac-spoofing privilege and
70 * the port to have no filters or queues active.
71 */
72 static __checkReturn efx_rc_t
efx_mcdi_vadapter_set_mac(__in efx_nic_t * enp)73 efx_mcdi_vadapter_set_mac(
74 __in efx_nic_t *enp)
75 {
76 efx_port_t *epp = &(enp->en_port);
77 efx_mcdi_req_t req;
78 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_SET_MAC_IN_LEN,
79 MC_CMD_VADAPTOR_SET_MAC_OUT_LEN);
80 efx_rc_t rc;
81
82 req.emr_cmd = MC_CMD_VADAPTOR_SET_MAC;
83 req.emr_in_buf = payload;
84 req.emr_in_length = MC_CMD_VADAPTOR_SET_MAC_IN_LEN;
85 req.emr_out_buf = payload;
86 req.emr_out_length = MC_CMD_VADAPTOR_SET_MAC_OUT_LEN;
87
88 MCDI_IN_SET_DWORD(req, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
89 enp->en_vport_id);
90 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, VADAPTOR_SET_MAC_IN_MACADDR),
91 epp->ep_mac_addr);
92
93 efx_mcdi_execute(enp, &req);
94
95 if (req.emr_rc != 0) {
96 rc = req.emr_rc;
97 goto fail1;
98 }
99
100 return (0);
101
102 fail1:
103 EFSYS_PROBE1(fail1, efx_rc_t, rc);
104
105 return (rc);
106 }
107
108 __checkReturn efx_rc_t
ef10_mac_addr_set(__in efx_nic_t * enp)109 ef10_mac_addr_set(
110 __in efx_nic_t *enp)
111 {
112 efx_rc_t rc;
113
114 if ((rc = efx_mcdi_vadapter_set_mac(enp)) != 0) {
115 if (rc != ENOTSUP)
116 goto fail1;
117
118 /*
119 * Fallback for older Huntington firmware without Vadapter
120 * support.
121 */
122 if ((rc = ef10_mac_reconfigure(enp)) != 0)
123 goto fail2;
124 }
125
126 return (0);
127
128 fail2:
129 EFSYS_PROBE(fail2);
130
131 fail1:
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
133
134 return (rc);
135 }
136
137 static __checkReturn efx_rc_t
efx_mcdi_mtu_set(__in efx_nic_t * enp,__in uint32_t mtu)138 efx_mcdi_mtu_set(
139 __in efx_nic_t *enp,
140 __in uint32_t mtu)
141 {
142 efx_mcdi_req_t req;
143 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_MAC_EXT_IN_LEN,
144 MC_CMD_SET_MAC_OUT_LEN);
145 efx_rc_t rc;
146
147 req.emr_cmd = MC_CMD_SET_MAC;
148 req.emr_in_buf = payload;
149 req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
150 req.emr_out_buf = payload;
151 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
152
153 /* Only configure the MTU in this call to MC_CMD_SET_MAC */
154 MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_MTU, mtu);
155 MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_EXT_IN_CONTROL,
156 SET_MAC_EXT_IN_CFG_MTU, 1);
157
158 efx_mcdi_execute(enp, &req);
159
160 if (req.emr_rc != 0) {
161 rc = req.emr_rc;
162 goto fail1;
163 }
164
165 return (0);
166
167 fail1:
168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
169
170 return (rc);
171 }
172
173 static __checkReturn efx_rc_t
efx_mcdi_mtu_get(__in efx_nic_t * enp,__out size_t * mtu)174 efx_mcdi_mtu_get(
175 __in efx_nic_t *enp,
176 __out size_t *mtu)
177 {
178 efx_mcdi_req_t req;
179 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_MAC_EXT_IN_LEN,
180 MC_CMD_SET_MAC_V2_OUT_LEN);
181 efx_rc_t rc;
182
183 req.emr_cmd = MC_CMD_SET_MAC;
184 req.emr_in_buf = payload;
185 req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
186 req.emr_out_buf = payload;
187 req.emr_out_length = MC_CMD_SET_MAC_V2_OUT_LEN;
188
189 /*
190 * With MC_CMD_SET_MAC_EXT_IN_CONTROL set to 0, this just queries the
191 * MTU. This should always be supported on Medford, but it is not
192 * supported on older Huntington firmware.
193 */
194 MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_CONTROL, 0);
195
196 efx_mcdi_execute(enp, &req);
197
198 if (req.emr_rc != 0) {
199 rc = req.emr_rc;
200 goto fail1;
201 }
202 if (req.emr_out_length_used < MC_CMD_SET_MAC_V2_OUT_MTU_OFST + 4) {
203 rc = EMSGSIZE;
204 goto fail2;
205 }
206
207 *mtu = MCDI_OUT_DWORD(req, SET_MAC_V2_OUT_MTU);
208
209 return (0);
210
211 fail2:
212 EFSYS_PROBE(fail2);
213 fail1:
214 EFSYS_PROBE1(fail1, efx_rc_t, rc);
215
216 return (rc);
217 }
218
219 __checkReturn efx_rc_t
ef10_mac_pdu_set(__in efx_nic_t * enp)220 ef10_mac_pdu_set(
221 __in efx_nic_t *enp)
222 {
223 efx_port_t *epp = &(enp->en_port);
224 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
225 efx_rc_t rc;
226
227 if (encp->enc_enhanced_set_mac_supported) {
228 if ((rc = efx_mcdi_mtu_set(enp, epp->ep_mac_pdu)) != 0)
229 goto fail1;
230 } else {
231 /*
232 * Fallback for older Huntington firmware, which always
233 * configure all of the parameters to MC_CMD_SET_MAC. This isn't
234 * suitable for setting the MTU on unpriviliged functions.
235 */
236 if ((rc = ef10_mac_reconfigure(enp)) != 0)
237 goto fail2;
238 }
239
240 return (0);
241
242 fail2:
243 EFSYS_PROBE(fail2);
244 fail1:
245 EFSYS_PROBE1(fail1, efx_rc_t, rc);
246
247 return (rc);
248 }
249
250 __checkReturn efx_rc_t
ef10_mac_pdu_get(__in efx_nic_t * enp,__out size_t * pdu)251 ef10_mac_pdu_get(
252 __in efx_nic_t *enp,
253 __out size_t *pdu)
254 {
255 efx_rc_t rc;
256
257 if ((rc = efx_mcdi_mtu_get(enp, pdu)) != 0)
258 goto fail1;
259
260 return (0);
261
262 fail1:
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
264
265 return (rc);
266 }
267
268 __checkReturn efx_rc_t
ef10_mac_reconfigure(__in efx_nic_t * enp)269 ef10_mac_reconfigure(
270 __in efx_nic_t *enp)
271 {
272 efx_port_t *epp = &(enp->en_port);
273 efx_mcdi_req_t req;
274 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_MAC_IN_LEN,
275 MC_CMD_SET_MAC_OUT_LEN);
276 efx_rc_t rc;
277
278 req.emr_cmd = MC_CMD_SET_MAC;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
283
284 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
285 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
286 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
287 epp->ep_mac_addr);
288
289 /*
290 * Note: The Huntington MAC does not support REJECT_BRDCST.
291 * The REJECT_UNCST flag will also prevent multicast traffic
292 * from reaching the filters. As Huntington filters drop any
293 * traffic that does not match a filter it is ok to leave the
294 * MAC running in promiscuous mode. See bug41141.
295 *
296 * FIXME: Does REJECT_UNCST behave the same way on Medford?
297 */
298 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
299 SET_MAC_IN_REJECT_UNCST, 0,
300 SET_MAC_IN_REJECT_BRDCST, 0);
301
302 /*
303 * Flow control, whether it is auto-negotiated or not,
304 * is set via the PHY advertised capabilities. When set to
305 * automatic the MAC will use the PHY settings to determine
306 * the flow control settings.
307 */
308 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, MC_CMD_FCNTL_AUTO);
309
310 /* Do not include the Ethernet frame checksum in RX packets */
311 MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_IN_FLAGS,
312 SET_MAC_IN_FLAG_INCLUDE_FCS, 0);
313
314 efx_mcdi_execute_quiet(enp, &req);
315
316 if (req.emr_rc != 0) {
317 /*
318 * Unprivileged functions cannot control link state,
319 * but still need to configure filters.
320 */
321 if (req.emr_rc != EACCES) {
322 rc = req.emr_rc;
323 goto fail1;
324 }
325 }
326
327 /*
328 * Apply the filters for the MAC configuration.
329 * If the NIC isn't ready to accept filters this may
330 * return success without setting anything.
331 */
332 rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
333 epp->ep_all_unicst, epp->ep_mulcst,
334 epp->ep_all_mulcst, epp->ep_brdcst,
335 epp->ep_mulcst_addr_list,
336 epp->ep_mulcst_addr_count);
337
338 return (0);
339
340 fail1:
341 EFSYS_PROBE1(fail1, efx_rc_t, rc);
342
343 return (rc);
344 }
345
346 __checkReturn efx_rc_t
ef10_mac_multicast_list_set(__in efx_nic_t * enp)347 ef10_mac_multicast_list_set(
348 __in efx_nic_t *enp)
349 {
350 efx_port_t *epp = &(enp->en_port);
351 const efx_mac_ops_t *emop = epp->ep_emop;
352 efx_rc_t rc;
353
354 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
355
356 if ((rc = emop->emo_reconfigure(enp)) != 0)
357 goto fail1;
358
359 return (0);
360
361 fail1:
362 EFSYS_PROBE1(fail1, efx_rc_t, rc);
363
364 return (rc);
365 }
366
367 __checkReturn efx_rc_t
ef10_mac_filter_default_rxq_set(__in efx_nic_t * enp,__in efx_rxq_t * erp,__in boolean_t using_rss)368 ef10_mac_filter_default_rxq_set(
369 __in efx_nic_t *enp,
370 __in efx_rxq_t *erp,
371 __in boolean_t using_rss)
372 {
373 efx_port_t *epp = &(enp->en_port);
374 efx_rxq_t *old_rxq;
375 boolean_t old_using_rss;
376 efx_rc_t rc;
377
378 ef10_filter_get_default_rxq(enp, &old_rxq, &old_using_rss);
379
380 ef10_filter_default_rxq_set(enp, erp, using_rss);
381
382 rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
383 epp->ep_all_unicst, epp->ep_mulcst,
384 epp->ep_all_mulcst, epp->ep_brdcst,
385 epp->ep_mulcst_addr_list,
386 epp->ep_mulcst_addr_count);
387
388 if (rc != 0)
389 goto fail1;
390
391 return (0);
392
393 fail1:
394 EFSYS_PROBE1(fail1, efx_rc_t, rc);
395
396 ef10_filter_default_rxq_set(enp, old_rxq, old_using_rss);
397
398 return (rc);
399 }
400
401 void
ef10_mac_filter_default_rxq_clear(__in efx_nic_t * enp)402 ef10_mac_filter_default_rxq_clear(
403 __in efx_nic_t *enp)
404 {
405 efx_port_t *epp = &(enp->en_port);
406
407 ef10_filter_default_rxq_clear(enp);
408
409 (void) efx_filter_reconfigure(enp, epp->ep_mac_addr,
410 epp->ep_all_unicst, epp->ep_mulcst,
411 epp->ep_all_mulcst, epp->ep_brdcst,
412 epp->ep_mulcst_addr_list,
413 epp->ep_mulcst_addr_count);
414 }
415
416
417 #if EFSYS_OPT_LOOPBACK
418
419 __checkReturn efx_rc_t
ef10_mac_loopback_set(__in efx_nic_t * enp,__in efx_link_mode_t link_mode,__in efx_loopback_type_t loopback_type)420 ef10_mac_loopback_set(
421 __in efx_nic_t *enp,
422 __in efx_link_mode_t link_mode,
423 __in efx_loopback_type_t loopback_type)
424 {
425 efx_port_t *epp = &(enp->en_port);
426 const efx_phy_ops_t *epop = epp->ep_epop;
427 efx_loopback_type_t old_loopback_type;
428 efx_link_mode_t old_loopback_link_mode;
429 efx_rc_t rc;
430
431 /* The PHY object handles this on EF10 */
432 old_loopback_type = epp->ep_loopback_type;
433 old_loopback_link_mode = epp->ep_loopback_link_mode;
434 epp->ep_loopback_type = loopback_type;
435 epp->ep_loopback_link_mode = link_mode;
436
437 if ((rc = epop->epo_reconfigure(enp)) != 0)
438 goto fail1;
439
440 return (0);
441
442 fail1:
443 EFSYS_PROBE1(fail1, efx_rc_t, rc);
444
445 epp->ep_loopback_type = old_loopback_type;
446 epp->ep_loopback_link_mode = old_loopback_link_mode;
447
448 return (rc);
449 }
450
451 #endif /* EFSYS_OPT_LOOPBACK */
452
453 #if EFSYS_OPT_MAC_STATS
454
455 __checkReturn efx_rc_t
ef10_mac_stats_get_mask(__in efx_nic_t * enp,__inout_bcount (mask_size)uint32_t * maskp,__in size_t mask_size)456 ef10_mac_stats_get_mask(
457 __in efx_nic_t *enp,
458 __inout_bcount(mask_size) uint32_t *maskp,
459 __in size_t mask_size)
460 {
461 const struct efx_mac_stats_range ef10_common[] = {
462 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
463 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_RX_DROP_EVENTS },
464 { EFX_MAC_RX_JABBER_PKTS, EFX_MAC_RX_JABBER_PKTS },
465 { EFX_MAC_RX_NODESC_DROP_CNT, EFX_MAC_TX_PAUSE_PKTS },
466 };
467 const struct efx_mac_stats_range ef10_tx_size_bins[] = {
468 { EFX_MAC_TX_LE_64_PKTS, EFX_MAC_TX_GE_15XX_PKTS },
469 };
470 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
471 efx_port_t *epp = &(enp->en_port);
472 efx_rc_t rc;
473
474 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
475 ef10_common, EFX_ARRAY_SIZE(ef10_common))) != 0)
476 goto fail1;
477
478 if (epp->ep_phy_cap_mask & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
479 const struct efx_mac_stats_range ef10_40g_extra[] = {
480 { EFX_MAC_RX_ALIGN_ERRORS, EFX_MAC_RX_ALIGN_ERRORS },
481 };
482
483 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
484 ef10_40g_extra, EFX_ARRAY_SIZE(ef10_40g_extra))) != 0)
485 goto fail2;
486
487 if (encp->enc_mac_stats_40g_tx_size_bins) {
488 if ((rc = efx_mac_stats_mask_add_ranges(maskp,
489 mask_size, ef10_tx_size_bins,
490 EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
491 goto fail3;
492 }
493 } else {
494 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
495 ef10_tx_size_bins, EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
496 goto fail4;
497 }
498
499 if (encp->enc_pm_and_rxdp_counters) {
500 const struct efx_mac_stats_range ef10_pm_and_rxdp[] = {
501 { EFX_MAC_PM_TRUNC_BB_OVERFLOW, EFX_MAC_RXDP_HLB_WAIT },
502 };
503
504 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
505 ef10_pm_and_rxdp, EFX_ARRAY_SIZE(ef10_pm_and_rxdp))) != 0)
506 goto fail5;
507 }
508
509 if (encp->enc_datapath_cap_evb) {
510 const struct efx_mac_stats_range ef10_vadaptor[] = {
511 { EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
512 EFX_MAC_VADAPTER_TX_OVERFLOW },
513 };
514
515 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
516 ef10_vadaptor, EFX_ARRAY_SIZE(ef10_vadaptor))) != 0)
517 goto fail6;
518 }
519
520 if (encp->enc_fec_counters) {
521 const struct efx_mac_stats_range ef10_fec[] = {
522 { EFX_MAC_FEC_UNCORRECTED_ERRORS,
523 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3 },
524 };
525 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
526 ef10_fec, EFX_ARRAY_SIZE(ef10_fec))) != 0)
527 goto fail7;
528 }
529
530 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V4) {
531 const struct efx_mac_stats_range ef10_rxdp_sdt[] = {
532 { EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
533 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC },
534 };
535
536 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
537 ef10_rxdp_sdt, EFX_ARRAY_SIZE(ef10_rxdp_sdt))) != 0)
538 goto fail8;
539 }
540
541 if (encp->enc_hlb_counters) {
542 const struct efx_mac_stats_range ef10_hlb[] = {
543 { EFX_MAC_RXDP_HLB_IDLE, EFX_MAC_RXDP_HLB_TIMEOUT },
544 };
545 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
546 ef10_hlb, EFX_ARRAY_SIZE(ef10_hlb))) != 0)
547 goto fail9;
548 }
549
550 return (0);
551
552 fail9:
553 EFSYS_PROBE(fail9);
554 fail8:
555 EFSYS_PROBE(fail8);
556 fail7:
557 EFSYS_PROBE(fail7);
558 fail6:
559 EFSYS_PROBE(fail6);
560 fail5:
561 EFSYS_PROBE(fail5);
562 fail4:
563 EFSYS_PROBE(fail4);
564 fail3:
565 EFSYS_PROBE(fail3);
566 fail2:
567 EFSYS_PROBE(fail2);
568 fail1:
569 EFSYS_PROBE1(fail1, efx_rc_t, rc);
570
571 return (rc);
572 }
573
574 #define EF10_MAC_STAT_READ(_esmp, _field, _eqp) \
575 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
576
577
578 __checkReturn efx_rc_t
ef10_mac_stats_update(__in efx_nic_t * enp,__in efsys_mem_t * esmp,__inout_ecount (EFX_MAC_NSTATS)efsys_stat_t * stat,__inout_opt uint32_t * generationp)579 ef10_mac_stats_update(
580 __in efx_nic_t *enp,
581 __in efsys_mem_t *esmp,
582 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
583 __inout_opt uint32_t *generationp)
584 {
585 const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
586 efx_qword_t generation_start;
587 efx_qword_t generation_end;
588 efx_qword_t value;
589 efx_rc_t rc;
590
591 /*
592 * The MAC_STATS contain start and end generation counters used to
593 * detect when the DMA buffer has been updated during stats decode.
594 * All stats counters are 64bit unsigned values.
595 *
596 * Siena-compatible MAC stats contain MC_CMD_MAC_NSTATS 64bit counters.
597 * The generation end counter is at index MC_CMD_MAC_GENERATION_END
598 * (same as MC_CMD_MAC_NSTATS-1).
599 *
600 * Medford2 and later use a larger DMA buffer: MAC_STATS_NUM_STATS from
601 * MC_CMD_GET_CAPABILITIES_V4_OUT reports the number of 64bit counters.
602 *
603 * Firmware writes the generation end counter as the last counter in the
604 * DMA buffer. Do not use MC_CMD_MAC_GENERATION_END, as that is only
605 * correct for legacy Siena-compatible MAC stats.
606 */
607
608 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) {
609 /* MAC stats count too small for legacy MAC stats */
610 rc = ENOSPC;
611 goto fail1;
612 }
613 if (EFSYS_MEM_SIZE(esmp) <
614 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
615 /* DMA buffer too small */
616 rc = ENOSPC;
617 goto fail2;
618 }
619
620 /* Read END first so we don't race with the MC */
621 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
622 EF10_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
623 &generation_end);
624 EFSYS_MEM_READ_BARRIER();
625
626 /* TX */
627 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
628 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
629
630 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
631 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
632
633 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
634 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
635
636 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
637 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
638
639 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
640 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
641
642 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
643 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
644
645 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
646 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
647
648 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
649 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
650 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
651 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
652
653 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
654 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
655
656 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
657 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
658
659 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
660 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
661
662 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
663 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
664
665 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
666 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
667
668 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
669 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
670 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
671 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
672
673 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
674 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
675
676 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
677 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
678
679 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
680 &value);
681 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
682
683 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
684 &value);
685 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
686
687 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
688 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
689
690 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
691 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
692
693 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
694 &value);
695 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
696
697 /* RX */
698 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
699 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
700
701 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
702 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
703
704 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
705 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
706
707 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
708 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
709
710 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
711 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
712
713 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
714 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
715
716 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
717 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
718 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
719 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
720
721 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
722 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
723
724 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
725 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
726
727 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
728 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
729
730 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
731 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
732
733 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
734 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
735
736 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
737 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
738 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
739 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
740
741 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
742 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
743
744 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
745 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
746
747 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
748 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
749
750 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
751 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
752
753 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
754 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
755
756 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
757 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
758
759 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
760 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
761
762 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
763 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
764 &(value.eq_dword[0]));
765 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
766 &(value.eq_dword[1]));
767
768 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
769 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
770 &(value.eq_dword[0]));
771 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
772 &(value.eq_dword[1]));
773
774 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
775 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
776 &(value.eq_dword[0]));
777 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
778 &(value.eq_dword[1]));
779
780 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
781 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
782 &(value.eq_dword[0]));
783 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
784 &(value.eq_dword[1]));
785
786 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
787 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
788
789 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
790 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
791
792 /* Packet memory (EF10 only) */
793 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW, &value);
794 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_BB_OVERFLOW]), &value);
795
796 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW, &value);
797 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_BB_OVERFLOW]), &value);
798
799 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_VFIFO_FULL, &value);
800 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_VFIFO_FULL]), &value);
801
802 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_VFIFO_FULL, &value);
803 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_VFIFO_FULL]), &value);
804
805 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_QBB, &value);
806 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_QBB]), &value);
807
808 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_QBB, &value);
809 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_QBB]), &value);
810
811 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_MAPPING, &value);
812 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_MAPPING]), &value);
813
814 /* RX datapath */
815 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_Q_DISABLED_PKTS, &value);
816 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_Q_DISABLED_PKTS]), &value);
817
818 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_DI_DROPPED_PKTS, &value);
819 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_DI_DROPPED_PKTS]), &value);
820
821 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_STREAMING_PKTS, &value);
822 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_STREAMING_PKTS]), &value);
823
824 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS, &value);
825 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_FETCH]), &value);
826
827 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value);
828 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value);
829
830
831 /* VADAPTER RX */
832 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS,
833 &value);
834 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS]),
835 &value);
836
837 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES,
838 &value);
839 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_BYTES]),
840 &value);
841
842 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS,
843 &value);
844 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS]),
845 &value);
846
847 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES,
848 &value);
849 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES]),
850 &value);
851
852 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS,
853 &value);
854 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]),
855 &value);
856
857 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES,
858 &value);
859 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]),
860 &value);
861
862 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS,
863 &value);
864 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_PACKETS]),
865 &value);
866
867 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_BYTES, &value);
868 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_BYTES]), &value);
869
870 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_OVERFLOW, &value);
871 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_OVERFLOW]), &value);
872
873 /* VADAPTER TX */
874 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS,
875 &value);
876 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS]),
877 &value);
878
879 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES,
880 &value);
881 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_BYTES]),
882 &value);
883
884 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS,
885 &value);
886 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS]),
887 &value);
888
889 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES,
890 &value);
891 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES]),
892 &value);
893
894 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS,
895 &value);
896 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]),
897 &value);
898
899 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES,
900 &value);
901 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]),
902 &value);
903
904 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS, &value);
905 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_PACKETS]), &value);
906
907 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_BYTES, &value);
908 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_BYTES]), &value);
909
910 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value);
911 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value);
912
913
914 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V2)
915 goto done;
916
917 /* FEC */
918 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_UNCORRECTED_ERRORS, &value);
919 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_UNCORRECTED_ERRORS]), &value);
920
921 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_ERRORS, &value);
922 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_ERRORS]), &value);
923
924 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
925 &value);
926 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0]),
927 &value);
928
929 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
930 &value);
931 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1]),
932 &value);
933
934 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
935 &value);
936 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2]),
937 &value);
938
939 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
940 &value);
941 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3]),
942 &value);
943
944 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V3)
945 goto done;
946
947 /* CTPIO exceptions */
948 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK, &value);
949 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_VI_BUSY_FALLBACK]), &value);
950
951 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS, &value);
952 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_LONG_WRITE_SUCCESS]), &value);
953
954 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL, &value);
955 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_MISSING_DBELL_FAIL]), &value);
956
957 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_OVERFLOW_FAIL, &value);
958 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_OVERFLOW_FAIL]), &value);
959
960 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL, &value);
961 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_UNDERFLOW_FAIL]), &value);
962
963 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_TIMEOUT_FAIL, &value);
964 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_TIMEOUT_FAIL]), &value);
965
966 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL, &value);
967 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_NONCONTIG_WR_FAIL]), &value);
968
969 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL, &value);
970 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_FRM_CLOBBER_FAIL]), &value);
971
972 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_INVALID_WR_FAIL, &value);
973 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_INVALID_WR_FAIL]), &value);
974
975 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK, &value);
976 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK]),
977 &value);
978
979 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK, &value);
980 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK]),
981 &value);
982
983 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_RUNT_FALLBACK, &value);
984 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_RUNT_FALLBACK]), &value);
985
986 /* CTPIO per-port stats */
987 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_SUCCESS, &value);
988 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_SUCCESS]), &value);
989
990 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_FALLBACK, &value);
991 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_FALLBACK]), &value);
992
993 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_POISON, &value);
994 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_POISON]), &value);
995
996 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_ERASE, &value);
997 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_ERASE]), &value);
998
999 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V4)
1000 goto done;
1001
1002 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC,
1003 &value);
1004 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC]),
1005 &value);
1006
1007 /* Head-of-line blocking */
1008 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_IDLE, &value);
1009 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_IDLE]), &value);
1010
1011 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_TIMEOUT, &value);
1012 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_TIMEOUT]), &value);
1013
1014 done:
1015 /* Read START generation counter */
1016 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
1017 EFSYS_MEM_READ_BARRIER();
1018 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
1019 &generation_start);
1020
1021 /* Check that we didn't read the stats in the middle of a DMA */
1022 /* Not a good enough check ? */
1023 if (memcmp(&generation_start, &generation_end,
1024 sizeof (generation_start)))
1025 return (EAGAIN);
1026
1027 if (generationp)
1028 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
1029
1030 return (0);
1031
1032 fail2:
1033 EFSYS_PROBE(fail2);
1034 fail1:
1035 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1036
1037 return (rc);
1038 }
1039
1040 #endif /* EFSYS_OPT_MAC_STATS */
1041
1042 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1043