1 //===-- lldb_EmulateInstructionARM.h ----------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef lldb_EmulateInstructionARM_h_ 11 #define lldb_EmulateInstructionARM_h_ 12 13 #include "Plugins/Process/Utility/ARMDefines.h" 14 #include "lldb/Core/EmulateInstruction.h" 15 #include "lldb/Utility/ConstString.h" 16 #include "lldb/Utility/Status.h" 17 18 namespace lldb_private { 19 20 // ITSession - Keep track of the IT Block progression. 21 class ITSession { 22 public: ITSession()23 ITSession() : ITCounter(0), ITState(0) {} ~ITSession()24 ~ITSession() {} 25 26 // InitIT - Initializes ITCounter/ITState. 27 bool InitIT(uint32_t bits7_0); 28 29 // ITAdvance - Updates ITCounter/ITState as IT Block progresses. 30 void ITAdvance(); 31 32 // InITBlock - Returns true if we're inside an IT Block. 33 bool InITBlock(); 34 35 // LastInITBlock - Returns true if we're the last instruction inside an IT 36 // Block. 37 bool LastInITBlock(); 38 39 // GetCond - Gets condition bits for the current thumb instruction. 40 uint32_t GetCond(); 41 42 private: 43 uint32_t ITCounter; // Possible values: 0, 1, 2, 3, 4. 44 uint32_t ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. 45 }; 46 47 class EmulateInstructionARM : public EmulateInstruction { 48 public: 49 typedef enum { 50 eEncodingA1, 51 eEncodingA2, 52 eEncodingA3, 53 eEncodingA4, 54 eEncodingA5, 55 eEncodingT1, 56 eEncodingT2, 57 eEncodingT3, 58 eEncodingT4, 59 eEncodingT5 60 } ARMEncoding; 61 62 static void Initialize(); 63 64 static void Terminate(); 65 66 static lldb_private::ConstString GetPluginNameStatic(); 67 68 static const char *GetPluginDescriptionStatic(); 69 70 static lldb_private::EmulateInstruction * 71 CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type); 72 73 static bool SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type)74 SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type) { 75 switch (inst_type) { 76 case eInstructionTypeAny: 77 case eInstructionTypePrologueEpilogue: 78 case eInstructionTypePCModifying: 79 return true; 80 81 case eInstructionTypeAll: 82 return false; 83 } 84 return false; 85 } 86 GetPluginName()87 lldb_private::ConstString GetPluginName() override { 88 return GetPluginNameStatic(); 89 } 90 GetPluginVersion()91 uint32_t GetPluginVersion() override { return 1; } 92 93 bool SetTargetTriple(const ArchSpec &arch) override; 94 95 enum Mode { eModeInvalid = -1, eModeARM, eModeThumb }; 96 EmulateInstructionARM(const ArchSpec & arch)97 EmulateInstructionARM(const ArchSpec &arch) 98 : EmulateInstruction(arch), m_arm_isa(0), m_opcode_mode(eModeInvalid), 99 m_opcode_cpsr(0), m_it_session(), m_ignore_conditions(false) { 100 SetArchitecture(arch); 101 } 102 103 // EmulateInstructionARM (const ArchSpec &arch, 104 // bool ignore_conditions, 105 // void *baton, 106 // ReadMemory read_mem_callback, 107 // WriteMemory write_mem_callback, 108 // ReadRegister read_reg_callback, 109 // WriteRegister write_reg_callback) : 110 // EmulateInstruction (arch, 111 // ignore_conditions, 112 // baton, 113 // read_mem_callback, 114 // write_mem_callback, 115 // read_reg_callback, 116 // write_reg_callback), 117 // m_arm_isa (0), 118 // m_opcode_mode (eModeInvalid), 119 // m_opcode_cpsr (0), 120 // m_it_session () 121 // { 122 // } 123 SupportsEmulatingInstructionsOfType(InstructionType inst_type)124 bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override { 125 return SupportsEmulatingInstructionsOfTypeStatic(inst_type); 126 } 127 128 virtual bool SetArchitecture(const ArchSpec &arch); 129 130 bool ReadInstruction() override; 131 132 bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr, 133 Target *target) override; 134 135 bool EvaluateInstruction(uint32_t evaluate_options) override; 136 137 InstructionCondition GetInstructionCondition() override; 138 139 bool TestEmulation(Stream *out_stream, ArchSpec &arch, 140 OptionValueDictionary *test_data) override; 141 142 bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num, 143 RegisterInfo ®_info) override; 144 145 bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override; 146 147 uint32_t ArchVersion(); 148 149 bool ConditionPassed(const uint32_t opcode); 150 151 uint32_t CurrentCond(const uint32_t opcode); 152 153 // InITBlock - Returns true if we're in Thumb mode and inside an IT Block. 154 bool InITBlock(); 155 156 // LastInITBlock - Returns true if we're in Thumb mode and the last 157 // instruction inside an IT Block. 158 bool LastInITBlock(); 159 160 bool BadMode(uint32_t mode); 161 162 bool CurrentModeIsPrivileged(); 163 164 void CPSRWriteByInstr(uint32_t value, uint32_t bytemask, 165 bool affect_execstate); 166 167 bool BranchWritePC(const Context &context, uint32_t addr); 168 169 bool BXWritePC(Context &context, uint32_t addr); 170 171 bool LoadWritePC(Context &context, uint32_t addr); 172 173 bool ALUWritePC(Context &context, uint32_t addr); 174 175 Mode CurrentInstrSet(); 176 177 bool SelectInstrSet(Mode arm_or_thumb); 178 179 bool WriteBits32Unknown(int n); 180 181 bool WriteBits32UnknownToMemory(lldb::addr_t address); 182 183 bool UnalignedSupport(); 184 185 typedef struct { 186 uint32_t result; 187 uint8_t carry_out; 188 uint8_t overflow; 189 } AddWithCarryResult; 190 191 AddWithCarryResult AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in); 192 193 // Helper method to read the content of an ARM core register. 194 uint32_t ReadCoreReg(uint32_t regnum, bool *success); 195 196 // See A8.6.96 MOV (immediate) Operation. 197 // Default arguments are specified for carry and overflow parameters, which 198 // means 199 // not to update the respective flags even if setflags is true. 200 bool WriteCoreRegOptionalFlags(Context &context, const uint32_t result, 201 const uint32_t Rd, bool setflags, 202 const uint32_t carry = ~0u, 203 const uint32_t overflow = ~0u); 204 WriteCoreReg(Context & context,const uint32_t result,const uint32_t Rd)205 bool WriteCoreReg(Context &context, const uint32_t result, 206 const uint32_t Rd) { 207 // Don't set the flags. 208 return WriteCoreRegOptionalFlags(context, result, Rd, false); 209 } 210 211 // See A8.6.35 CMP (immediate) Operation. 212 // Default arguments are specified for carry and overflow parameters, which 213 // means 214 // not to update the respective flags. 215 bool WriteFlags(Context &context, const uint32_t result, 216 const uint32_t carry = ~0u, const uint32_t overflow = ~0u); 217 MemARead(EmulateInstruction::Context & context,lldb::addr_t address,uint32_t size,uint64_t fail_value,bool * success_ptr)218 inline uint64_t MemARead(EmulateInstruction::Context &context, 219 lldb::addr_t address, uint32_t size, 220 uint64_t fail_value, bool *success_ptr) { 221 // This is a stub function corresponding to "MemA[]" in the ARM manual 222 // pseudocode, for 223 // aligned reads from memory. Since we are not trying to write a full 224 // hardware simulator, and since 225 // we are running in User mode (rather than Kernel mode) and therefore won't 226 // have access to many of the 227 // system registers we would need in order to fully implement this function, 228 // we will just call 229 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 230 // do more faithful emulation of 231 // the hardware, we can update this function appropriately. 232 233 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 234 } 235 MemAWrite(EmulateInstruction::Context & context,lldb::addr_t address,uint64_t data_val,uint32_t size)236 inline bool MemAWrite(EmulateInstruction::Context &context, 237 lldb::addr_t address, uint64_t data_val, uint32_t size) 238 239 { 240 // This is a stub function corresponding to "MemA[]" in the ARM manual 241 // pseudocode, for 242 // aligned writes to memory. Since we are not trying to write a full 243 // hardware simulator, and since 244 // we are running in User mode (rather than Kernel mode) and therefore won't 245 // have access to many of the 246 // system registers we would need in order to fully implement this function, 247 // we will just call 248 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 249 // do more faithful emulation of 250 // the hardware, we can update this function appropriately. 251 252 return WriteMemoryUnsigned(context, address, data_val, size); 253 } 254 MemURead(EmulateInstruction::Context & context,lldb::addr_t address,uint32_t size,uint64_t fail_value,bool * success_ptr)255 inline uint64_t MemURead(EmulateInstruction::Context &context, 256 lldb::addr_t address, uint32_t size, 257 uint64_t fail_value, bool *success_ptr) { 258 // This is a stub function corresponding to "MemU[]" in the ARM manual 259 // pseudocode, for 260 // unaligned reads from memory. Since we are not trying to write a full 261 // hardware simulator, and since 262 // we are running in User mode (rather than Kernel mode) and therefore won't 263 // have access to many of the 264 // system registers we would need in order to fully implement this function, 265 // we will just call 266 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 267 // do more faithful emulation of 268 // the hardware, we can update this function appropriately. 269 270 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 271 } 272 MemUWrite(EmulateInstruction::Context & context,lldb::addr_t address,uint64_t data_val,uint32_t size)273 inline bool MemUWrite(EmulateInstruction::Context &context, 274 lldb::addr_t address, uint64_t data_val, uint32_t size) 275 276 { 277 // This is a stub function corresponding to "MemU[]" in the ARM manual 278 // pseudocode, for 279 // unaligned writes to memory. Since we are not trying to write a full 280 // hardware simulator, and since 281 // we are running in User mode (rather than Kernel mode) and therefore won't 282 // have access to many of the 283 // system registers we would need in order to fully implement this function, 284 // we will just call 285 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 286 // do more faithful emulation of 287 // the hardware, we can update this function appropriately. 288 289 return WriteMemoryUnsigned(context, address, data_val, size); 290 } 291 292 protected: 293 // Typedef for the callback function used during the emulation. 294 // Pass along (ARMEncoding)encoding as the callback data. 295 typedef enum { eSize16, eSize32 } ARMInstrSize; 296 297 typedef struct { 298 uint32_t mask; 299 uint32_t value; 300 uint32_t variants; 301 EmulateInstructionARM::ARMEncoding encoding; 302 uint32_t vfp_variants; 303 ARMInstrSize size; 304 bool (EmulateInstructionARM::*callback)( 305 const uint32_t opcode, 306 const EmulateInstructionARM::ARMEncoding encoding); 307 const char *name; 308 } ARMOpcode; 309 310 uint32_t GetFramePointerRegisterNumber() const; 311 312 uint32_t GetFramePointerDWARFRegisterNumber() const; 313 314 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode, 315 uint32_t isa_mask); 316 317 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode, 318 uint32_t isa_mask); 319 320 // A8.6.123 PUSH 321 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding); 322 323 // A8.6.122 POP 324 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding); 325 326 // A8.6.8 ADD (SP plus immediate) 327 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding); 328 329 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp 330 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding); 331 332 // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7 333 bool EmulateMOVLowHigh(const uint32_t opcode, const ARMEncoding encoding); 334 335 // A8.6.59 LDR (literal) 336 bool EmulateLDRRtPCRelative(const uint32_t opcode, 337 const ARMEncoding encoding); 338 339 // A8.6.8 ADD (SP plus immediate) 340 bool EmulateADDSPImm(const uint32_t opcode, const ARMEncoding encoding); 341 342 // A8.6.9 ADD (SP plus register) 343 bool EmulateADDSPRm(const uint32_t opcode, const ARMEncoding encoding); 344 345 // A8.6.23 BL, BLX (immediate) 346 bool EmulateBLXImmediate(const uint32_t opcode, const ARMEncoding encoding); 347 348 // A8.6.24 BLX (register) 349 bool EmulateBLXRm(const uint32_t opcode, const ARMEncoding encoding); 350 351 // A8.6.25 BX 352 bool EmulateBXRm(const uint32_t opcode, const ARMEncoding encoding); 353 354 // A8.6.26 BXJ 355 bool EmulateBXJRm(const uint32_t opcode, const ARMEncoding encoding); 356 357 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip 358 bool EmulateSUBR7IPImm(const uint32_t opcode, const ARMEncoding encoding); 359 360 // A8.6.215 SUB (SP minus immediate) -- Rd == ip 361 bool EmulateSUBIPSPImm(const uint32_t opcode, const ARMEncoding encoding); 362 363 // A8.6.215 SUB (SP minus immediate) 364 bool EmulateSUBSPImm(const uint32_t opcode, const ARMEncoding encoding); 365 366 // A8.6.216 SUB (SP minus register) 367 bool EmulateSUBSPReg(const uint32_t opcode, const ARMEncoding encoding); 368 369 // A8.6.194 STR (immediate, ARM) -- Rn == sp 370 bool EmulateSTRRtSP(const uint32_t opcode, const ARMEncoding encoding); 371 372 // A8.6.355 VPUSH 373 bool EmulateVPUSH(const uint32_t opcode, const ARMEncoding encoding); 374 375 // A8.6.354 VPOP 376 bool EmulateVPOP(const uint32_t opcode, const ARMEncoding encoding); 377 378 // A8.6.218 SVC (previously SWI) 379 bool EmulateSVC(const uint32_t opcode, const ARMEncoding encoding); 380 381 // A8.6.50 IT 382 bool EmulateIT(const uint32_t opcode, const ARMEncoding encoding); 383 384 // NOP 385 bool EmulateNop(const uint32_t opcode, const ARMEncoding encoding); 386 387 // A8.6.16 B 388 bool EmulateB(const uint32_t opcode, const ARMEncoding encoding); 389 390 // A8.6.27 CBNZ, CBZ 391 bool EmulateCB(const uint32_t opcode, const ARMEncoding encoding); 392 393 // A8.6.226 TBB, TBH 394 bool EmulateTB(const uint32_t opcode, const ARMEncoding encoding); 395 396 // A8.6.4 ADD (immediate, Thumb) 397 bool EmulateADDImmThumb(const uint32_t opcode, const ARMEncoding encoding); 398 399 // A8.6.5 ADD (immediate, ARM) 400 bool EmulateADDImmARM(const uint32_t opcode, const ARMEncoding encoding); 401 402 // A8.6.6 ADD (register) 403 bool EmulateADDReg(const uint32_t opcode, const ARMEncoding encoding); 404 405 // A8.6.7 ADD (register-shifted register) 406 bool EmulateADDRegShift(const uint32_t opcode, const ARMEncoding encoding); 407 408 // A8.6.97 MOV (register) 409 bool EmulateMOVRdRm(const uint32_t opcode, const ARMEncoding encoding); 410 411 // A8.6.96 MOV (immediate) 412 bool EmulateMOVRdImm(const uint32_t opcode, const ARMEncoding encoding); 413 414 // A8.6.35 CMP (immediate) 415 bool EmulateCMPImm(const uint32_t opcode, const ARMEncoding encoding); 416 417 // A8.6.36 CMP (register) 418 bool EmulateCMPReg(const uint32_t opcode, const ARMEncoding encoding); 419 420 // A8.6.14 ASR (immediate) 421 bool EmulateASRImm(const uint32_t opcode, const ARMEncoding encoding); 422 423 // A8.6.15 ASR (register) 424 bool EmulateASRReg(const uint32_t opcode, const ARMEncoding encoding); 425 426 // A8.6.88 LSL (immediate) 427 bool EmulateLSLImm(const uint32_t opcode, const ARMEncoding encoding); 428 429 // A8.6.89 LSL (register) 430 bool EmulateLSLReg(const uint32_t opcode, const ARMEncoding encoding); 431 432 // A8.6.90 LSR (immediate) 433 bool EmulateLSRImm(const uint32_t opcode, const ARMEncoding encoding); 434 435 // A8.6.91 LSR (register) 436 bool EmulateLSRReg(const uint32_t opcode, const ARMEncoding encoding); 437 438 // A8.6.139 ROR (immediate) 439 bool EmulateRORImm(const uint32_t opcode, const ARMEncoding encoding); 440 441 // A8.6.140 ROR (register) 442 bool EmulateRORReg(const uint32_t opcode, const ARMEncoding encoding); 443 444 // A8.6.141 RRX 445 bool EmulateRRX(const uint32_t opcode, const ARMEncoding encoding); 446 447 // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX 448 bool EmulateShiftImm(const uint32_t opcode, const ARMEncoding encoding, 449 ARM_ShifterType shift_type); 450 451 // Helper method for ASR, LSL, LSR, and ROR (register) 452 bool EmulateShiftReg(const uint32_t opcode, const ARMEncoding encoding, 453 ARM_ShifterType shift_type); 454 455 // LOAD FUNCTIONS 456 457 // A8.6.53 LDM/LDMIA/LDMFD 458 bool EmulateLDM(const uint32_t opcode, const ARMEncoding encoding); 459 460 // A8.6.54 LDMDA/LDMFA 461 bool EmulateLDMDA(const uint32_t opcode, const ARMEncoding encoding); 462 463 // A8.6.55 LDMDB/LDMEA 464 bool EmulateLDMDB(const uint32_t opcode, const ARMEncoding encoding); 465 466 // A8.6.56 LDMIB/LDMED 467 bool EmulateLDMIB(const uint32_t opcode, const ARMEncoding encoding); 468 469 // A8.6.57 LDR (immediate, Thumb) -- Encoding T1 470 bool EmulateLDRRtRnImm(const uint32_t opcode, const ARMEncoding encoding); 471 472 // A8.6.58 LDR (immediate, ARM) - Encoding A1 473 bool EmulateLDRImmediateARM(const uint32_t opcode, 474 const ARMEncoding encoding); 475 476 // A8.6.59 LDR (literal) 477 bool EmulateLDRLiteral(const uint32_t, const ARMEncoding encoding); 478 479 // A8.6.60 LDR (register) - Encoding T1, T2, A1 480 bool EmulateLDRRegister(const uint32_t opcode, const ARMEncoding encoding); 481 482 // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 483 bool EmulateLDRBImmediate(const uint32_t opcode, const ARMEncoding encoding); 484 485 // A8.6.62 LDRB (immediate, ARM) 486 bool EmulateLDRBImmediateARM(const uint32_t opcode, 487 const ARMEncoding encoding); 488 489 // A8.6.63 LDRB (literal) - Encoding T1, A1 490 bool EmulateLDRBLiteral(const uint32_t opcode, const ARMEncoding encoding); 491 492 // A8.6.64 LDRB (register) - Encoding T1, T2, A1 493 bool EmulateLDRBRegister(const uint32_t opcode, const ARMEncoding encoding); 494 495 // A8.6.65 LDRBT 496 bool EmulateLDRBT(const uint32_t opcode, const ARMEncoding encoding); 497 498 // A8.6.66 LDRD (immediate) 499 bool EmulateLDRDImmediate(const uint32_t opcode, const ARMEncoding encoding); 500 501 // A8.6.67 502 bool EmulateLDRDLiteral(const uint32_t opcode, const ARMEncoding encoding); 503 504 // A8.6.68 LDRD (register) 505 bool EmulateLDRDRegister(const uint32_t opcode, const ARMEncoding encoding); 506 507 // A8.6.69 LDREX 508 bool EmulateLDREX(const uint32_t opcode, const ARMEncoding encoding); 509 510 // A8.6.70 LDREXB 511 bool EmulateLDREXB(const uint32_t opcode, const ARMEncoding encoding); 512 513 // A8.6.71 LDREXD 514 bool EmulateLDREXD(const uint32_t opcode, const ARMEncoding encoding); 515 516 // A8.6.72 LDREXH 517 bool EmulateLDREXH(const uint32_t opcode, const ARMEncoding encoding); 518 519 // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 520 bool EmulateLDRHImmediate(const uint32_t opcode, const ARMEncoding encoding); 521 522 // A8.6.74 LDRS (immediate, ARM) 523 bool EmulateLDRHImmediateARM(const uint32_t opcode, 524 const ARMEncoding encoding); 525 526 // A8.6.75 LDRH (literal) - Encoding T1, A1 527 bool EmulateLDRHLiteral(const uint32_t opcode, const ARMEncoding encoding); 528 529 // A8.6.76 LDRH (register) - Encoding T1, T2, A1 530 bool EmulateLDRHRegister(const uint32_t opcode, const ARMEncoding encoding); 531 532 // A8.6.77 LDRHT 533 bool EmulateLDRHT(const uint32_t opcode, const ARMEncoding encoding); 534 535 // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 536 bool EmulateLDRSBImmediate(const uint32_t opcode, const ARMEncoding encoding); 537 538 // A8.6.79 LDRSB (literal) - Encoding T1, A1 539 bool EmulateLDRSBLiteral(const uint32_t opcode, const ARMEncoding encoding); 540 541 // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 542 bool EmulateLDRSBRegister(const uint32_t opcode, const ARMEncoding encoding); 543 544 // A8.6.81 LDRSBT 545 bool EmulateLDRSBT(const uint32_t opcode, const ARMEncoding encoding); 546 547 // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 548 bool EmulateLDRSHImmediate(const uint32_t opcode, const ARMEncoding encoding); 549 550 // A8.6.83 LDRSH (literal) - Encoding T1, A1 551 bool EmulateLDRSHLiteral(const uint32_t opcode, const ARMEncoding encoding); 552 553 // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 554 bool EmulateLDRSHRegister(const uint32_t opcode, const ARMEncoding encoding); 555 556 // A8.6.85 LDRSHT 557 bool EmulateLDRSHT(const uint32_t opcode, const ARMEncoding encoding); 558 559 // A8.6.86 560 bool EmulateLDRT(const uint32_t opcode, const ARMEncoding encoding); 561 562 // STORE FUNCTIONS 563 564 // A8.6.189 STM/STMIA/STMEA 565 bool EmulateSTM(const uint32_t opcode, const ARMEncoding encoding); 566 567 // A8.6.190 STMDA/STMED 568 bool EmulateSTMDA(const uint32_t opcode, const ARMEncoding encoding); 569 570 // A8.6.191 STMDB/STMFD 571 bool EmulateSTMDB(const uint32_t opcode, const ARMEncoding encoding); 572 573 // A8.6.192 STMIB/STMFA 574 bool EmulateSTMIB(const uint32_t opcode, const ARMEncoding encoding); 575 576 // A8.6.193 STR (immediate, Thumb) 577 bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); 578 579 // A8.6.194 STR (immediate, ARM) 580 bool EmulateSTRImmARM(const uint32_t opcode, const ARMEncoding encoding); 581 582 // A8.6.195 STR (register) 583 bool EmulateSTRRegister(const uint32_t opcode, const ARMEncoding encoding); 584 585 // A8.6.196 STRB (immediate, Thumb) 586 bool EmulateSTRBThumb(const uint32_t opcode, const ARMEncoding encoding); 587 588 // A8.6.197 STRB (immediate, ARM) 589 bool EmulateSTRBImmARM(const uint32_t opcode, const ARMEncoding encoding); 590 591 // A8.6.198 STRB (register) 592 bool EmulateSTRBReg(const uint32_t opcode, const ARMEncoding encoding); 593 594 // A8.6.199 STRBT 595 bool EmulateSTRBT(const uint32_t opcode, const ARMEncoding encoding); 596 597 // A8.6.200 STRD (immediate) 598 bool EmulateSTRDImm(const uint32_t opcode, const ARMEncoding encoding); 599 600 // A8.6.201 STRD (register) 601 bool EmulateSTRDReg(const uint32_t opcode, const ARMEncoding encoding); 602 603 // A8.6.202 STREX 604 bool EmulateSTREX(const uint32_t opcode, const ARMEncoding encoding); 605 606 // A8.6.203 STREXB 607 bool EmulateSTREXB(const uint32_t opcode, const ARMEncoding encoding); 608 609 // A8.6.204 STREXD 610 bool EmulateSTREXD(const uint32_t opcode, const ARMEncoding encoding); 611 612 // A8.6.205 STREXH 613 bool EmulateSTREXH(const uint32_t opcode, const ARMEncoding encoding); 614 615 // A8.6.206 STRH (immediate, Thumb) 616 bool EmulateSTRHImmThumb(const uint32_t opcode, const ARMEncoding encoding); 617 618 // A8.6.207 STRH (immediate, ARM) 619 bool EmulateSTRHImmARM(const uint32_t opcode, const ARMEncoding encoding); 620 621 // A8.6.208 STRH (register) 622 bool EmulateSTRHRegister(const uint32_t opcode, const ARMEncoding encoding); 623 624 // A8.6.209 STRHT 625 bool EmulateSTRHT(const uint32_t opcode, const ARMEncoding encoding); 626 627 // A8.6.210 STRT 628 bool EmulateSTRT(const uint32_t opcode, const ARMEncoding encoding); 629 630 // A8.6.1 ADC (immediate) 631 bool EmulateADCImm(const uint32_t opcode, const ARMEncoding encoding); 632 633 // A8.6.2 ADC (Register) 634 bool EmulateADCReg(const uint32_t opcode, const ARMEncoding encoding); 635 636 // A8.6.10 ADR 637 bool EmulateADR(const uint32_t opcode, const ARMEncoding encoding); 638 639 // A8.6.11 AND (immediate) 640 bool EmulateANDImm(const uint32_t opcode, const ARMEncoding encoding); 641 642 // A8.6.12 AND (register) 643 bool EmulateANDReg(const uint32_t opcode, const ARMEncoding encoding); 644 645 // A8.6.19 BIC (immediate) 646 bool EmulateBICImm(const uint32_t opcode, const ARMEncoding encoding); 647 648 // A8.6.20 BIC (register) 649 bool EmulateBICReg(const uint32_t opcode, const ARMEncoding encoding); 650 651 // A8.6.26 BXJ 652 bool EmulateBXJ(const uint32_t opcode, const ARMEncoding encoding); 653 654 // A8.6.32 CMN (immediate) 655 bool EmulateCMNImm(const uint32_t opcode, const ARMEncoding encoding); 656 657 // A8.6.33 CMN (register) 658 bool EmulateCMNReg(const uint32_t opcode, const ARMEncoding encoding); 659 660 // A8.6.44 EOR (immediate) 661 bool EmulateEORImm(const uint32_t opcode, const ARMEncoding encoding); 662 663 // A8.6.45 EOR (register) 664 bool EmulateEORReg(const uint32_t opcode, const ARMEncoding encoding); 665 666 // A8.6.105 MUL 667 bool EmulateMUL(const uint32_t opcode, const ARMEncoding encoding); 668 669 // A8.6.106 MVN (immediate) 670 bool EmulateMVNImm(const uint32_t opcode, const ARMEncoding encoding); 671 672 // A8.6.107 MVN (register) 673 bool EmulateMVNReg(const uint32_t opcode, const ARMEncoding encoding); 674 675 // A8.6.113 ORR (immediate) 676 bool EmulateORRImm(const uint32_t opcode, const ARMEncoding encoding); 677 678 // A8.6.114 ORR (register) 679 bool EmulateORRReg(const uint32_t opcode, const ARMEncoding encoding); 680 681 // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1 682 bool EmulatePLDImmediate(const uint32_t opcode, const ARMEncoding encoding); 683 684 // A8.6.119 PLI (immediate,literal) - Encoding T3, A1 685 bool EmulatePLIImmediate(const uint32_t opcode, const ARMEncoding encoding); 686 687 // A8.6.120 PLI (register) - Encoding T1, A1 688 bool EmulatePLIRegister(const uint32_t opcode, const ARMEncoding encoding); 689 690 // A8.6.141 RSB (immediate) 691 bool EmulateRSBImm(const uint32_t opcode, const ARMEncoding encoding); 692 693 // A8.6.142 RSB (register) 694 bool EmulateRSBReg(const uint32_t opcode, const ARMEncoding encoding); 695 696 // A8.6.144 RSC (immediate) 697 bool EmulateRSCImm(const uint32_t opcode, const ARMEncoding encoding); 698 699 // A8.6.145 RSC (register) 700 bool EmulateRSCReg(const uint32_t opcode, const ARMEncoding encoding); 701 702 // A8.6.150 SBC (immediate) 703 bool EmulateSBCImm(const uint32_t opcode, const ARMEncoding encoding); 704 705 // A8.6.151 SBC (register) 706 bool EmulateSBCReg(const uint32_t opcode, const ARMEncoding encoding); 707 708 // A8.6.211 SUB (immediate, Thumb) 709 bool EmulateSUBImmThumb(const uint32_t opcode, const ARMEncoding encoding); 710 711 // A8.6.212 SUB (immediate, ARM) 712 bool EmulateSUBImmARM(const uint32_t opcode, const ARMEncoding encoding); 713 714 // A8.6.213 SUB (register) 715 bool EmulateSUBReg(const uint32_t opcode, const ARMEncoding encoding); 716 717 // A8.6.214 SUB (register-shifted register) 718 bool EmulateSUBRegShift(const uint32_t opcode, const ARMEncoding encoding); 719 720 // A8.6.222 SXTB - Encoding T1 721 bool EmulateSXTB(const uint32_t opcode, const ARMEncoding encoding); 722 723 // A8.6.224 SXTH - EncodingT1 724 bool EmulateSXTH(const uint32_t opcode, const ARMEncoding encoding); 725 726 // A8.6.227 TEQ (immediate) - Encoding A1 727 bool EmulateTEQImm(const uint32_t opcode, const ARMEncoding encoding); 728 729 // A8.6.228 TEQ (register) - Encoding A1 730 bool EmulateTEQReg(const uint32_t opcode, const ARMEncoding encoding); 731 732 // A8.6.230 TST (immediate) - Encoding A1 733 bool EmulateTSTImm(const uint32_t opcode, const ARMEncoding encoding); 734 735 // A8.6.231 TST (register) - Encoding T1, A1 736 bool EmulateTSTReg(const uint32_t opcode, const ARMEncoding encoding); 737 738 // A8.6.262 UXTB - Encoding T1 739 bool EmulateUXTB(const uint32_t opcode, const ARMEncoding encoding); 740 741 // A8.6.264 UXTH - Encoding T1 742 bool EmulateUXTH(const uint32_t opcode, const ARMEncoding encoding); 743 744 // B6.1.8 RFE 745 bool EmulateRFE(const uint32_t opcode, const ARMEncoding encoding); 746 747 // A8.6.319 VLDM 748 bool EmulateVLDM(const uint32_t opcode, const ARMEncoding encoding); 749 750 // A8.6.399 VSTM 751 bool EmulateVSTM(const uint32_t opcode, const ARMEncoding encoding); 752 753 // A8.6.307 VLD1 (multiple single elements) 754 bool EmulateVLD1Multiple(const uint32_t opcode, const ARMEncoding encoding); 755 756 // A8.6.308 VLD1 (single element to one lane) 757 bool EmulateVLD1Single(const uint32_t opcode, const ARMEncoding encoding); 758 759 // A8.6.309 VLD1 (single element to all lanes) 760 bool EmulateVLD1SingleAll(const uint32_t opcode, const ARMEncoding encoding); 761 762 // A8.6.391 VST1 (multiple single elements) 763 bool EmulateVST1Multiple(const uint32_t opcode, const ARMEncoding encoding); 764 765 // A8.6.392 VST1 (single element from one lane) 766 bool EmulateVST1Single(const uint32_t opcode, const ARMEncoding encoding); 767 768 // A8.6.317 VLDR 769 bool EmulateVLDR(const uint32_t opcode, const ARMEncoding encoding); 770 771 // A8.6.400 VSTR 772 bool EmulateVSTR(const uint32_t opcode, const ARMEncoding encoding); 773 774 // B6.2.13 SUBS PC, LR and related instructions 775 bool EmulateSUBSPcLrEtc(const uint32_t opcode, const ARMEncoding encoding); 776 777 uint32_t m_arm_isa; 778 Mode m_opcode_mode; 779 uint32_t m_opcode_cpsr; 780 uint32_t m_new_inst_cpsr; // This can get updated by the opcode. 781 ITSession m_it_session; 782 bool m_ignore_conditions; 783 }; 784 785 } // namespace lldb_private 786 787 #endif // lldb_EmulateInstructionARM_h_ 788