1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #ifndef _ICE_PTP_CONSTS_H_ 6 #define _ICE_PTP_CONSTS_H_ 7 8 /* Constant definitions related to the hardware clock used for PTP 1588 9 * features and functionality. 10 */ 11 /* Constants defined for the PTP 1588 clock hardware. */ 12 13 /* 14 * struct ice_time_ref_info_e822 15 * 16 * E822 hardware can use different sources as the reference for the PTP 17 * hardware clock. Each clock has different characteristics such as a slightly 18 * different frequency, etc. 19 * 20 * This lookup table defines several constants that depend on the current time 21 * reference. See the struct ice_time_ref_info_e822 for information about the 22 * meaning of each constant. 23 */ 24 const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = { 25 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */ 26 { 27 /* pll_freq */ 28 823437500, /* 823.4375 MHz PLL */ 29 /* nominal_incval */ 30 0x136e44fabULL, 31 /* pps_delay */ 32 11, 33 }, 34 35 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */ 36 { 37 /* pll_freq */ 38 783360000, /* 783.36 MHz */ 39 /* nominal_incval */ 40 0x146cc2177ULL, 41 /* pps_delay */ 42 12, 43 }, 44 45 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */ 46 { 47 /* pll_freq */ 48 796875000, /* 796.875 MHz */ 49 /* nominal_incval */ 50 0x141414141ULL, 51 /* pps_delay */ 52 12, 53 }, 54 55 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */ 56 { 57 /* pll_freq */ 58 816000000, /* 816 MHz */ 59 /* nominal_incval */ 60 0x139b9b9baULL, 61 /* pps_delay */ 62 12, 63 }, 64 65 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */ 66 { 67 /* pll_freq */ 68 830078125, /* 830.78125 MHz */ 69 /* nominal_incval */ 70 0x134679aceULL, 71 /* pps_delay */ 72 11, 73 }, 74 75 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */ 76 { 77 /* pll_freq */ 78 783360000, /* 783.36 MHz */ 79 /* nominal_incval */ 80 0x146cc2177ULL, 81 /* pps_delay */ 82 12, 83 }, 84 }; 85 86 const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = { 87 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */ 88 { 89 /* refclk_pre_div */ 90 1, 91 /* feedback_div */ 92 197, 93 /* frac_n_div */ 94 2621440, 95 /* post_pll_div */ 96 6, 97 }, 98 99 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */ 100 { 101 /* refclk_pre_div */ 102 5, 103 /* feedback_div */ 104 223, 105 /* frac_n_div */ 106 524288, 107 /* post_pll_div */ 108 7, 109 }, 110 111 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */ 112 { 113 /* refclk_pre_div */ 114 5, 115 /* feedback_div */ 116 223, 117 /* frac_n_div */ 118 524288, 119 /* post_pll_div */ 120 7, 121 }, 122 123 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */ 124 { 125 /* refclk_pre_div */ 126 5, 127 /* feedback_div */ 128 159, 129 /* frac_n_div */ 130 1572864, 131 /* post_pll_div */ 132 6, 133 }, 134 135 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */ 136 { 137 /* refclk_pre_div */ 138 5, 139 /* feedback_div */ 140 159, 141 /* frac_n_div */ 142 1572864, 143 /* post_pll_div */ 144 6, 145 }, 146 147 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */ 148 { 149 /* refclk_pre_div */ 150 10, 151 /* feedback_div */ 152 223, 153 /* frac_n_div */ 154 524288, 155 /* post_pll_div */ 156 7, 157 }, 158 }; 159 160 /* struct ice_vernier_info_e822 161 * 162 * E822 hardware calibrates the delay of the timestamp indication from the 163 * actual packet transmission or reception during the initialization of the 164 * PHY. To do this, the hardware mechanism uses some conversions between the 165 * various clocks within the PHY block. This table defines constants used to 166 * calculate the correct conversion ratios in the PHY registers. 167 * 168 * Many of the values relate to the PAR/PCS clock conversion registers. For 169 * these registers, a value of 0 means that the associated register is not 170 * used by this link speed, and that the register should be cleared by writing 171 * 0. Other values specify the clock frequency in Hz. 172 */ 173 const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = { 174 /* ICE_PTP_LNK_SPD_1G */ 175 { 176 /* tx_par_clk */ 177 31250000, /* 31.25 MHz */ 178 /* rx_par_clk */ 179 31250000, /* 31.25 MHz */ 180 /* tx_pcs_clk */ 181 125000000, /* 125 MHz */ 182 /* rx_pcs_clk */ 183 125000000, /* 125 MHz */ 184 /* tx_desk_rsgb_par */ 185 0, /* unused */ 186 /* rx_desk_rsgb_par */ 187 0, /* unused */ 188 /* tx_desk_rsgb_pcs */ 189 0, /* unused */ 190 /* rx_desk_rsgb_pcs */ 191 0, /* unused */ 192 /* tx_fixed_delay */ 193 25140, 194 /* pmd_adj_divisor */ 195 10000000, 196 /* rx_fixed_delay */ 197 17372, 198 }, 199 /* ICE_PTP_LNK_SPD_10G */ 200 { 201 /* tx_par_clk */ 202 257812500, /* 257.8125 MHz */ 203 /* rx_par_clk */ 204 257812500, /* 257.8125 MHz */ 205 /* tx_pcs_clk */ 206 156250000, /* 156.25 MHz */ 207 /* rx_pcs_clk */ 208 156250000, /* 156.25 MHz */ 209 /* tx_desk_rsgb_par */ 210 0, /* unused */ 211 /* rx_desk_rsgb_par */ 212 0, /* unused */ 213 /* tx_desk_rsgb_pcs */ 214 0, /* unused */ 215 /* rx_desk_rsgb_pcs */ 216 0, /* unused */ 217 /* tx_fixed_delay */ 218 6938, 219 /* pmd_adj_divisor */ 220 82500000, 221 /* rx_fixed_delay */ 222 6212, 223 }, 224 /* ICE_PTP_LNK_SPD_25G */ 225 { 226 /* tx_par_clk */ 227 644531250, /* 644.53125 MHZ */ 228 /* rx_par_clk */ 229 644531250, /* 644.53125 MHz */ 230 /* tx_pcs_clk */ 231 390625000, /* 390.625 MHz */ 232 /* rx_pcs_clk */ 233 390625000, /* 390.625 MHz */ 234 /* tx_desk_rsgb_par */ 235 0, /* unused */ 236 /* rx_desk_rsgb_par */ 237 0, /* unused */ 238 /* tx_desk_rsgb_pcs */ 239 0, /* unused */ 240 /* rx_desk_rsgb_pcs */ 241 0, /* unused */ 242 /* tx_fixed_delay */ 243 2778, 244 /* pmd_adj_divisor */ 245 206250000, 246 /* rx_fixed_delay */ 247 2491, 248 }, 249 /* ICE_PTP_LNK_SPD_25G_RS */ 250 { 251 /* tx_par_clk */ 252 0, /* unused */ 253 /* rx_par_clk */ 254 0, /* unused */ 255 /* tx_pcs_clk */ 256 0, /* unused */ 257 /* rx_pcs_clk */ 258 0, /* unused */ 259 /* tx_desk_rsgb_par */ 260 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 261 /* rx_desk_rsgb_par */ 262 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 263 /* tx_desk_rsgb_pcs */ 264 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 265 /* rx_desk_rsgb_pcs */ 266 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 267 /* tx_fixed_delay */ 268 3928, 269 /* pmd_adj_divisor */ 270 206250000, 271 /* rx_fixed_delay */ 272 29535, 273 }, 274 /* ICE_PTP_LNK_SPD_40G */ 275 { 276 /* tx_par_clk */ 277 257812500, 278 /* rx_par_clk */ 279 257812500, 280 /* tx_pcs_clk */ 281 156250000, /* 156.25 MHz */ 282 /* rx_pcs_clk */ 283 156250000, /* 156.25 MHz */ 284 /* tx_desk_rsgb_par */ 285 0, /* unused */ 286 /* rx_desk_rsgb_par */ 287 156250000, /* 156.25 MHz deskew clock */ 288 /* tx_desk_rsgb_pcs */ 289 0, /* unused */ 290 /* rx_desk_rsgb_pcs */ 291 156250000, /* 156.25 MHz deskew clock */ 292 /* tx_fixed_delay */ 293 5666, 294 /* pmd_adj_divisor */ 295 82500000, 296 /* rx_fixed_delay */ 297 4244, 298 }, 299 /* ICE_PTP_LNK_SPD_50G */ 300 { 301 /* tx_par_clk */ 302 644531250, /* 644.53125 MHZ */ 303 /* rx_par_clk */ 304 644531250, /* 644.53125 MHZ */ 305 /* tx_pcs_clk */ 306 390625000, /* 390.625 MHz */ 307 /* rx_pcs_clk */ 308 390625000, /* 390.625 MHz */ 309 /* tx_desk_rsgb_par */ 310 0, /* unused */ 311 /* rx_desk_rsgb_par */ 312 195312500, /* 193.3125 MHz deskew clock */ 313 /* tx_desk_rsgb_pcs */ 314 0, /* unused */ 315 /* rx_desk_rsgb_pcs */ 316 195312500, /* 193.3125 MHz deskew clock */ 317 /* tx_fixed_delay */ 318 2778, 319 /* pmd_adj_divisor */ 320 206250000, 321 /* rx_fixed_delay */ 322 2868, 323 }, 324 /* ICE_PTP_LNK_SPD_50G_RS */ 325 { 326 /* tx_par_clk */ 327 0, /* unused */ 328 /* rx_par_clk */ 329 644531250, /* 644.53125 MHz */ 330 /* tx_pcs_clk */ 331 0, /* unused */ 332 /* rx_pcs_clk */ 333 644531250, /* 644.53125 MHz */ 334 /* tx_desk_rsgb_par */ 335 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 336 /* rx_desk_rsgb_par */ 337 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 338 /* tx_desk_rsgb_pcs */ 339 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 340 /* rx_desk_rsgb_pcs */ 341 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 342 /* tx_fixed_delay */ 343 2095, 344 /* pmd_adj_divisor */ 345 206250000, 346 /* rx_fixed_delay */ 347 14524, 348 }, 349 /* ICE_PTP_LNK_SPD_100G_RS */ 350 { 351 /* tx_par_clk */ 352 0, /* unused */ 353 /* rx_par_clk */ 354 644531250, /* 644.53125 MHz */ 355 /* tx_pcs_clk */ 356 0, /* unused */ 357 /* rx_pcs_clk */ 358 644531250, /* 644.53125 MHz */ 359 /* tx_desk_rsgb_par */ 360 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 361 /* rx_desk_rsgb_par */ 362 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 363 /* tx_desk_rsgb_pcs */ 364 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 365 /* rx_desk_rsgb_pcs */ 366 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 367 /* tx_fixed_delay */ 368 1620, 369 /* pmd_adj_divisor */ 370 206250000, 371 /* rx_fixed_delay */ 372 7775, 373 }, 374 }; 375 376 #endif /* _ICE_PTP_CONSTS_H_ */ 377