1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 #include "e1000_api.h"
6
7 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
8 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
9 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw);
10
11 /**
12 * e1000_init_mac_ops_generic - Initialize MAC function pointers
13 * @hw: pointer to the HW structure
14 *
15 * Setups up the function pointers to no-op functions
16 **/
e1000_init_mac_ops_generic(struct e1000_hw * hw)17 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
18 {
19 struct e1000_mac_info *mac = &hw->mac;
20 DEBUGFUNC("e1000_init_mac_ops_generic");
21
22 /* General Setup */
23 mac->ops.init_params = e1000_null_ops_generic;
24 mac->ops.init_hw = e1000_null_ops_generic;
25 mac->ops.reset_hw = e1000_null_ops_generic;
26 mac->ops.setup_physical_interface = e1000_null_ops_generic;
27 mac->ops.get_bus_info = e1000_null_ops_generic;
28 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
29 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
30 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
31 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
32 /* LED */
33 mac->ops.cleanup_led = e1000_null_ops_generic;
34 mac->ops.setup_led = e1000_null_ops_generic;
35 mac->ops.blink_led = e1000_null_ops_generic;
36 mac->ops.led_on = e1000_null_ops_generic;
37 mac->ops.led_off = e1000_null_ops_generic;
38 /* LINK */
39 mac->ops.setup_link = e1000_null_ops_generic;
40 mac->ops.get_link_up_info = e1000_null_link_info;
41 mac->ops.check_for_link = e1000_null_ops_generic;
42 /* Management */
43 mac->ops.check_mng_mode = e1000_null_mng_mode;
44 /* VLAN, MC, etc. */
45 mac->ops.update_mc_addr_list = e1000_null_update_mc;
46 mac->ops.clear_vfta = e1000_null_mac_generic;
47 mac->ops.write_vfta = e1000_null_write_vfta;
48 mac->ops.rar_set = e1000_rar_set_generic;
49 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
50 }
51
52 /**
53 * e1000_null_ops_generic - No-op function, returns 0
54 * @hw: pointer to the HW structure
55 **/
e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG * hw)56 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
57 {
58 DEBUGFUNC("e1000_null_ops_generic");
59 UNREFERENCED_1PARAMETER(hw);
60 return E1000_SUCCESS;
61 }
62
63 /**
64 * e1000_null_mac_generic - No-op function, return void
65 * @hw: pointer to the HW structure
66 **/
e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG * hw)67 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
68 {
69 DEBUGFUNC("e1000_null_mac_generic");
70 UNREFERENCED_1PARAMETER(hw);
71 return;
72 }
73
74 /**
75 * e1000_null_link_info - No-op function, return 0
76 * @hw: pointer to the HW structure
77 * @s: dummy variable
78 * @d: dummy variable
79 **/
e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG * hw,u16 E1000_UNUSEDARG * s,u16 E1000_UNUSEDARG * d)80 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
81 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
82 {
83 DEBUGFUNC("e1000_null_link_info");
84 UNREFERENCED_3PARAMETER(hw, s, d);
85 return E1000_SUCCESS;
86 }
87
88 /**
89 * e1000_null_mng_mode - No-op function, return false
90 * @hw: pointer to the HW structure
91 **/
e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG * hw)92 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
93 {
94 DEBUGFUNC("e1000_null_mng_mode");
95 UNREFERENCED_1PARAMETER(hw);
96 return false;
97 }
98
99 /**
100 * e1000_null_update_mc - No-op function, return void
101 * @hw: pointer to the HW structure
102 * @h: dummy variable
103 * @a: dummy variable
104 **/
e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG * h,u32 E1000_UNUSEDARG a)105 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
106 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
107 {
108 DEBUGFUNC("e1000_null_update_mc");
109 UNREFERENCED_3PARAMETER(hw, h, a);
110 return;
111 }
112
113 /**
114 * e1000_null_write_vfta - No-op function, return void
115 * @hw: pointer to the HW structure
116 * @a: dummy variable
117 * @b: dummy variable
118 **/
e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG a,u32 E1000_UNUSEDARG b)119 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
120 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
121 {
122 DEBUGFUNC("e1000_null_write_vfta");
123 UNREFERENCED_3PARAMETER(hw, a, b);
124 return;
125 }
126
127 /**
128 * e1000_null_rar_set - No-op function, return 0
129 * @hw: pointer to the HW structure
130 * @h: dummy variable
131 * @a: dummy variable
132 **/
e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG * h,u32 E1000_UNUSEDARG a)133 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
134 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
135 {
136 DEBUGFUNC("e1000_null_rar_set");
137 UNREFERENCED_3PARAMETER(hw, h, a);
138 return E1000_SUCCESS;
139 }
140
141 /**
142 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
143 * @hw: pointer to the HW structure
144 *
145 * Determines and stores the system bus information for a particular
146 * network interface. The following bus information is determined and stored:
147 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
148 **/
e1000_get_bus_info_pci_generic(struct e1000_hw * hw)149 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
150 {
151 struct e1000_mac_info *mac = &hw->mac;
152 struct e1000_bus_info *bus = &hw->bus;
153 u32 status = E1000_READ_REG(hw, E1000_STATUS);
154 s32 ret_val = E1000_SUCCESS;
155
156 DEBUGFUNC("e1000_get_bus_info_pci_generic");
157
158 /* PCI or PCI-X? */
159 bus->type = (status & E1000_STATUS_PCIX_MODE)
160 ? e1000_bus_type_pcix
161 : e1000_bus_type_pci;
162
163 /* Bus speed */
164 if (bus->type == e1000_bus_type_pci) {
165 bus->speed = (status & E1000_STATUS_PCI66)
166 ? e1000_bus_speed_66
167 : e1000_bus_speed_33;
168 } else {
169 switch (status & E1000_STATUS_PCIX_SPEED) {
170 case E1000_STATUS_PCIX_SPEED_66:
171 bus->speed = e1000_bus_speed_66;
172 break;
173 case E1000_STATUS_PCIX_SPEED_100:
174 bus->speed = e1000_bus_speed_100;
175 break;
176 case E1000_STATUS_PCIX_SPEED_133:
177 bus->speed = e1000_bus_speed_133;
178 break;
179 default:
180 bus->speed = e1000_bus_speed_reserved;
181 break;
182 }
183 }
184
185 /* Bus width */
186 bus->width = (status & E1000_STATUS_BUS64)
187 ? e1000_bus_width_64
188 : e1000_bus_width_32;
189
190 /* Which PCI(-X) function? */
191 mac->ops.set_lan_id(hw);
192
193 return ret_val;
194 }
195
196 /**
197 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
198 * @hw: pointer to the HW structure
199 *
200 * Determines and stores the system bus information for a particular
201 * network interface. The following bus information is determined and stored:
202 * bus speed, bus width, type (PCIe), and PCIe function.
203 **/
e1000_get_bus_info_pcie_generic(struct e1000_hw * hw)204 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
205 {
206 struct e1000_mac_info *mac = &hw->mac;
207 struct e1000_bus_info *bus = &hw->bus;
208 s32 ret_val;
209 u16 pcie_link_status;
210
211 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
212
213 bus->type = e1000_bus_type_pci_express;
214
215 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
216 &pcie_link_status);
217 if (ret_val) {
218 bus->width = e1000_bus_width_unknown;
219 bus->speed = e1000_bus_speed_unknown;
220 } else {
221 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
222 case PCIE_LINK_SPEED_2500:
223 bus->speed = e1000_bus_speed_2500;
224 break;
225 case PCIE_LINK_SPEED_5000:
226 bus->speed = e1000_bus_speed_5000;
227 break;
228 default:
229 bus->speed = e1000_bus_speed_unknown;
230 break;
231 }
232
233 bus->width = (enum e1000_bus_width)((pcie_link_status &
234 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
235 }
236
237 mac->ops.set_lan_id(hw);
238
239 return E1000_SUCCESS;
240 }
241
242 /**
243 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
244 *
245 * @hw: pointer to the HW structure
246 *
247 * Determines the LAN function id by reading memory-mapped registers
248 * and swaps the port value if requested.
249 **/
e1000_set_lan_id_multi_port_pcie(struct e1000_hw * hw)250 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
251 {
252 struct e1000_bus_info *bus = &hw->bus;
253 u32 reg;
254
255 /* The status register reports the correct function number
256 * for the device regardless of function swap state.
257 */
258 reg = E1000_READ_REG(hw, E1000_STATUS);
259 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
260 }
261
262 /**
263 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
264 * @hw: pointer to the HW structure
265 *
266 * Determines the LAN function id by reading PCI config space.
267 **/
e1000_set_lan_id_multi_port_pci(struct e1000_hw * hw)268 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
269 {
270 struct e1000_bus_info *bus = &hw->bus;
271 u16 pci_header_type;
272 u32 status;
273
274 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
275 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
276 status = E1000_READ_REG(hw, E1000_STATUS);
277 bus->func = (status & E1000_STATUS_FUNC_MASK)
278 >> E1000_STATUS_FUNC_SHIFT;
279 } else {
280 bus->func = 0;
281 }
282 }
283
284 /**
285 * e1000_set_lan_id_single_port - Set LAN id for a single port device
286 * @hw: pointer to the HW structure
287 *
288 * Sets the LAN function id to zero for a single port device.
289 **/
e1000_set_lan_id_single_port(struct e1000_hw * hw)290 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
291 {
292 struct e1000_bus_info *bus = &hw->bus;
293
294 bus->func = 0;
295 }
296
297 /**
298 * e1000_clear_vfta_generic - Clear VLAN filter table
299 * @hw: pointer to the HW structure
300 *
301 * Clears the register array which contains the VLAN filter table by
302 * setting all the values to 0.
303 **/
e1000_clear_vfta_generic(struct e1000_hw * hw)304 void e1000_clear_vfta_generic(struct e1000_hw *hw)
305 {
306 u32 offset;
307
308 DEBUGFUNC("e1000_clear_vfta_generic");
309
310 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
311 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
312 E1000_WRITE_FLUSH(hw);
313 }
314 }
315
316 /**
317 * e1000_write_vfta_generic - Write value to VLAN filter table
318 * @hw: pointer to the HW structure
319 * @offset: register offset in VLAN filter table
320 * @value: register value written to VLAN filter table
321 *
322 * Writes value at the given offset in the register array which stores
323 * the VLAN filter table.
324 **/
e1000_write_vfta_generic(struct e1000_hw * hw,u32 offset,u32 value)325 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
326 {
327 DEBUGFUNC("e1000_write_vfta_generic");
328
329 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
330 E1000_WRITE_FLUSH(hw);
331 }
332
333 /**
334 * e1000_init_rx_addrs_generic - Initialize receive address's
335 * @hw: pointer to the HW structure
336 * @rar_count: receive address registers
337 *
338 * Setup the receive address registers by setting the base receive address
339 * register to the devices MAC address and clearing all the other receive
340 * address registers to 0.
341 **/
e1000_init_rx_addrs_generic(struct e1000_hw * hw,u16 rar_count)342 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
343 {
344 u32 i;
345 u8 mac_addr[ETH_ADDR_LEN] = {0};
346
347 DEBUGFUNC("e1000_init_rx_addrs_generic");
348
349 /* Setup the receive address */
350 DEBUGOUT("Programming MAC Address into RAR[0]\n");
351
352 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
353
354 /* Zero out the other (rar_entry_count - 1) receive addresses */
355 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
356 for (i = 1; i < rar_count; i++)
357 hw->mac.ops.rar_set(hw, mac_addr, i);
358 }
359
360 /**
361 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
362 * @hw: pointer to the HW structure
363 *
364 * Checks the nvm for an alternate MAC address. An alternate MAC address
365 * can be setup by pre-boot software and must be treated like a permanent
366 * address and must override the actual permanent MAC address. If an
367 * alternate MAC address is found it is programmed into RAR0, replacing
368 * the permanent address that was installed into RAR0 by the Si on reset.
369 * This function will return SUCCESS unless it encounters an error while
370 * reading the EEPROM.
371 **/
e1000_check_alt_mac_addr_generic(struct e1000_hw * hw)372 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
373 {
374 u32 i;
375 s32 ret_val;
376 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
377 u8 alt_mac_addr[ETH_ADDR_LEN];
378
379 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
380
381 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
382 if (ret_val)
383 return ret_val;
384
385 /* not supported on older hardware or 82573 */
386 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
387 return E1000_SUCCESS;
388
389 /* Alternate MAC address is handled by the option ROM for 82580
390 * and newer. SW support not required.
391 */
392 if (hw->mac.type >= e1000_82580)
393 return E1000_SUCCESS;
394
395 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
396 &nvm_alt_mac_addr_offset);
397 if (ret_val) {
398 DEBUGOUT("NVM Read Error\n");
399 return ret_val;
400 }
401
402 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
403 (nvm_alt_mac_addr_offset == 0x0000))
404 /* There is no Alternate MAC Address */
405 return E1000_SUCCESS;
406
407 if (hw->bus.func == E1000_FUNC_1)
408 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
409 if (hw->bus.func == E1000_FUNC_2)
410 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
411
412 if (hw->bus.func == E1000_FUNC_3)
413 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
414 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
415 offset = nvm_alt_mac_addr_offset + (i >> 1);
416 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
417 if (ret_val) {
418 DEBUGOUT("NVM Read Error\n");
419 return ret_val;
420 }
421
422 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
423 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
424 }
425
426 /* if multicast bit is set, the alternate address will not be used */
427 if (alt_mac_addr[0] & 0x01) {
428 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
429 return E1000_SUCCESS;
430 }
431
432 /* We have a valid alternate MAC address, and we want to treat it the
433 * same as the normal permanent MAC address stored by the HW into the
434 * RAR. Do this by mapping this address into RAR0.
435 */
436 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
437
438 return E1000_SUCCESS;
439 }
440
441 /**
442 * e1000_rar_set_generic - Set receive address register
443 * @hw: pointer to the HW structure
444 * @addr: pointer to the receive address
445 * @index: receive address array register
446 *
447 * Sets the receive address array register at index to the address passed
448 * in by addr.
449 **/
e1000_rar_set_generic(struct e1000_hw * hw,u8 * addr,u32 index)450 int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
451 {
452 u32 rar_low, rar_high;
453
454 DEBUGFUNC("e1000_rar_set_generic");
455
456 /* HW expects these in little endian so we reverse the byte order
457 * from network order (big endian) to little endian
458 */
459 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
460 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
461
462 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
463
464 /* If MAC address zero, no need to set the AV bit */
465 if (rar_low || rar_high)
466 rar_high |= E1000_RAH_AV;
467
468 /* Some bridges will combine consecutive 32-bit writes into
469 * a single burst write, which will malfunction on some parts.
470 * The flushes avoid this.
471 */
472 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
473 E1000_WRITE_FLUSH(hw);
474 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
475 E1000_WRITE_FLUSH(hw);
476
477 return E1000_SUCCESS;
478 }
479
480 /**
481 * e1000_hash_mc_addr_generic - Generate a multicast hash value
482 * @hw: pointer to the HW structure
483 * @mc_addr: pointer to a multicast address
484 *
485 * Generates a multicast address hash value which is used to determine
486 * the multicast filter table array address and new table value.
487 **/
e1000_hash_mc_addr_generic(struct e1000_hw * hw,u8 * mc_addr)488 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
489 {
490 u32 hash_value, hash_mask;
491 u8 bit_shift = 0;
492
493 DEBUGFUNC("e1000_hash_mc_addr_generic");
494
495 /* Register count multiplied by bits per register */
496 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
497
498 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
499 * where 0xFF would still fall within the hash mask.
500 */
501 while (hash_mask >> bit_shift != 0xFF)
502 bit_shift++;
503
504 /* The portion of the address that is used for the hash table
505 * is determined by the mc_filter_type setting.
506 * The algorithm is such that there is a total of 8 bits of shifting.
507 * The bit_shift for a mc_filter_type of 0 represents the number of
508 * left-shifts where the MSB of mc_addr[5] would still fall within
509 * the hash_mask. Case 0 does this exactly. Since there are a total
510 * of 8 bits of shifting, then mc_addr[4] will shift right the
511 * remaining number of bits. Thus 8 - bit_shift. The rest of the
512 * cases are a variation of this algorithm...essentially raising the
513 * number of bits to shift mc_addr[5] left, while still keeping the
514 * 8-bit shifting total.
515 *
516 * For example, given the following Destination MAC Address and an
517 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
518 * we can see that the bit_shift for case 0 is 4. These are the hash
519 * values resulting from each mc_filter_type...
520 * [0] [1] [2] [3] [4] [5]
521 * 01 AA 00 12 34 56
522 * LSB MSB
523 *
524 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
525 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
526 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
527 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
528 */
529 switch (hw->mac.mc_filter_type) {
530 default:
531 case 0:
532 break;
533 case 1:
534 bit_shift += 1;
535 break;
536 case 2:
537 bit_shift += 2;
538 break;
539 case 3:
540 bit_shift += 4;
541 break;
542 }
543
544 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
545 (((u16) mc_addr[5]) << bit_shift)));
546
547 return hash_value;
548 }
549
550 /**
551 * e1000_update_mc_addr_list_generic - Update Multicast addresses
552 * @hw: pointer to the HW structure
553 * @mc_addr_list: array of multicast addresses to program
554 * @mc_addr_count: number of multicast addresses to program
555 *
556 * Updates entire Multicast Table Array.
557 * The caller must have a packed mc_addr_list of multicast addresses.
558 **/
e1000_update_mc_addr_list_generic(struct e1000_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)559 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
560 u8 *mc_addr_list, u32 mc_addr_count)
561 {
562 u32 hash_value, hash_bit, hash_reg;
563 int i;
564
565 DEBUGFUNC("e1000_update_mc_addr_list_generic");
566
567 /* clear mta_shadow */
568 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
569
570 /* update mta_shadow from mc_addr_list */
571 for (i = 0; (u32) i < mc_addr_count; i++) {
572 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
573
574 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
575 hash_bit = hash_value & 0x1F;
576
577 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
578 mc_addr_list += (ETH_ADDR_LEN);
579 }
580
581 /* replace the entire MTA table */
582 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
583 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
584 E1000_WRITE_FLUSH(hw);
585 }
586
587 /**
588 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
589 * @hw: pointer to the HW structure
590 *
591 * In certain situations, a system BIOS may report that the PCIx maximum
592 * memory read byte count (MMRBC) value is higher than than the actual
593 * value. We check the PCIx command register with the current PCIx status
594 * register.
595 **/
e1000_pcix_mmrbc_workaround_generic(struct e1000_hw * hw)596 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
597 {
598 u16 cmd_mmrbc;
599 u16 pcix_cmd;
600 u16 pcix_stat_hi_word;
601 u16 stat_mmrbc;
602
603 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
604
605 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
606 if (hw->bus.type != e1000_bus_type_pcix)
607 return;
608
609 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
610 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
611 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
612 PCIX_COMMAND_MMRBC_SHIFT;
613 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
614 PCIX_STATUS_HI_MMRBC_SHIFT;
615 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
616 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
617 if (cmd_mmrbc > stat_mmrbc) {
618 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
619 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
620 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
621 }
622 }
623
624 /**
625 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
626 * @hw: pointer to the HW structure
627 *
628 * Clears the base hardware counters by reading the counter registers.
629 **/
e1000_clear_hw_cntrs_base_generic(struct e1000_hw * hw)630 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
631 {
632 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
633
634 E1000_READ_REG(hw, E1000_CRCERRS);
635 E1000_READ_REG(hw, E1000_SYMERRS);
636 E1000_READ_REG(hw, E1000_MPC);
637 E1000_READ_REG(hw, E1000_SCC);
638 E1000_READ_REG(hw, E1000_ECOL);
639 E1000_READ_REG(hw, E1000_MCC);
640 E1000_READ_REG(hw, E1000_LATECOL);
641 E1000_READ_REG(hw, E1000_COLC);
642 E1000_READ_REG(hw, E1000_DC);
643 E1000_READ_REG(hw, E1000_SEC);
644 E1000_READ_REG(hw, E1000_RLEC);
645 E1000_READ_REG(hw, E1000_XONRXC);
646 E1000_READ_REG(hw, E1000_XONTXC);
647 E1000_READ_REG(hw, E1000_XOFFRXC);
648 E1000_READ_REG(hw, E1000_XOFFTXC);
649 E1000_READ_REG(hw, E1000_FCRUC);
650 E1000_READ_REG(hw, E1000_GPRC);
651 E1000_READ_REG(hw, E1000_BPRC);
652 E1000_READ_REG(hw, E1000_MPRC);
653 E1000_READ_REG(hw, E1000_GPTC);
654 E1000_READ_REG(hw, E1000_GORCL);
655 E1000_READ_REG(hw, E1000_GORCH);
656 E1000_READ_REG(hw, E1000_GOTCL);
657 E1000_READ_REG(hw, E1000_GOTCH);
658 E1000_READ_REG(hw, E1000_RNBC);
659 E1000_READ_REG(hw, E1000_RUC);
660 E1000_READ_REG(hw, E1000_RFC);
661 E1000_READ_REG(hw, E1000_ROC);
662 E1000_READ_REG(hw, E1000_RJC);
663 E1000_READ_REG(hw, E1000_TORL);
664 E1000_READ_REG(hw, E1000_TORH);
665 E1000_READ_REG(hw, E1000_TOTL);
666 E1000_READ_REG(hw, E1000_TOTH);
667 E1000_READ_REG(hw, E1000_TPR);
668 E1000_READ_REG(hw, E1000_TPT);
669 E1000_READ_REG(hw, E1000_MPTC);
670 E1000_READ_REG(hw, E1000_BPTC);
671 }
672
673 /**
674 * e1000_check_for_copper_link_generic - Check for link (Copper)
675 * @hw: pointer to the HW structure
676 *
677 * Checks to see of the link status of the hardware has changed. If a
678 * change in link status has been detected, then we read the PHY registers
679 * to get the current speed/duplex if link exists.
680 **/
e1000_check_for_copper_link_generic(struct e1000_hw * hw)681 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
682 {
683 struct e1000_mac_info *mac = &hw->mac;
684 s32 ret_val;
685 bool link;
686
687 DEBUGFUNC("e1000_check_for_copper_link");
688
689 /* We only want to go out to the PHY registers to see if Auto-Neg
690 * has completed and/or if our link status has changed. The
691 * get_link_status flag is set upon receiving a Link Status
692 * Change or Rx Sequence Error interrupt.
693 */
694 if (!mac->get_link_status)
695 return E1000_SUCCESS;
696
697 /* First we want to see if the MII Status Register reports
698 * link. If so, then we want to get the current speed/duplex
699 * of the PHY.
700 */
701 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
702 if (ret_val)
703 return ret_val;
704
705 if (!link)
706 return E1000_SUCCESS; /* No link detected */
707
708 mac->get_link_status = false;
709
710 /* Check if there was DownShift, must be checked
711 * immediately after link-up
712 */
713 e1000_check_downshift_generic(hw);
714
715 /* If we are forcing speed/duplex, then we simply return since
716 * we have already determined whether we have link or not.
717 */
718 if (!mac->autoneg)
719 return -E1000_ERR_CONFIG;
720
721 /* Auto-Neg is enabled. Auto Speed Detection takes care
722 * of MAC speed/duplex configuration. So we only need to
723 * configure Collision Distance in the MAC.
724 */
725 mac->ops.config_collision_dist(hw);
726
727 /* Configure Flow Control now that Auto-Neg has completed.
728 * First, we need to restore the desired flow control
729 * settings because we may have had to re-autoneg with a
730 * different link partner.
731 */
732 ret_val = e1000_config_fc_after_link_up_generic(hw);
733 if (ret_val)
734 DEBUGOUT("Error configuring flow control\n");
735
736 return ret_val;
737 }
738
739 /**
740 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
741 * @hw: pointer to the HW structure
742 *
743 * Checks for link up on the hardware. If link is not up and we have
744 * a signal, then we need to force link up.
745 **/
e1000_check_for_fiber_link_generic(struct e1000_hw * hw)746 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
747 {
748 struct e1000_mac_info *mac = &hw->mac;
749 u32 rxcw;
750 u32 ctrl;
751 u32 status;
752 s32 ret_val;
753
754 DEBUGFUNC("e1000_check_for_fiber_link_generic");
755
756 ctrl = E1000_READ_REG(hw, E1000_CTRL);
757 status = E1000_READ_REG(hw, E1000_STATUS);
758 rxcw = E1000_READ_REG(hw, E1000_RXCW);
759
760 /* If we don't have link (auto-negotiation failed or link partner
761 * cannot auto-negotiate), the cable is plugged in (we have signal),
762 * and our link partner is not trying to auto-negotiate with us (we
763 * are receiving idles or data), we need to force link up. We also
764 * need to give auto-negotiation time to complete, in case the cable
765 * was just plugged in. The autoneg_failed flag does this.
766 */
767 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
768 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
769 !(rxcw & E1000_RXCW_C)) {
770 if (!mac->autoneg_failed) {
771 mac->autoneg_failed = true;
772 return E1000_SUCCESS;
773 }
774 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
775
776 /* Disable auto-negotiation in the TXCW register */
777 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
778
779 /* Force link-up and also force full-duplex. */
780 ctrl = E1000_READ_REG(hw, E1000_CTRL);
781 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
782 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
783
784 /* Configure Flow Control after forcing link up. */
785 ret_val = e1000_config_fc_after_link_up_generic(hw);
786 if (ret_val) {
787 DEBUGOUT("Error configuring flow control\n");
788 return ret_val;
789 }
790 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
791 /* If we are forcing link and we are receiving /C/ ordered
792 * sets, re-enable auto-negotiation in the TXCW register
793 * and disable forced link in the Device Control register
794 * in an attempt to auto-negotiate with our link partner.
795 */
796 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
797 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
798 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
799
800 mac->serdes_has_link = true;
801 }
802
803 return E1000_SUCCESS;
804 }
805
806 /**
807 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
808 * @hw: pointer to the HW structure
809 *
810 * Checks for link up on the hardware. If link is not up and we have
811 * a signal, then we need to force link up.
812 **/
e1000_check_for_serdes_link_generic(struct e1000_hw * hw)813 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
814 {
815 struct e1000_mac_info *mac = &hw->mac;
816 u32 rxcw;
817 u32 ctrl;
818 u32 status;
819 s32 ret_val;
820
821 DEBUGFUNC("e1000_check_for_serdes_link_generic");
822
823 ctrl = E1000_READ_REG(hw, E1000_CTRL);
824 status = E1000_READ_REG(hw, E1000_STATUS);
825 rxcw = E1000_READ_REG(hw, E1000_RXCW);
826
827 /* If we don't have link (auto-negotiation failed or link partner
828 * cannot auto-negotiate), and our link partner is not trying to
829 * auto-negotiate with us (we are receiving idles or data),
830 * we need to force link up. We also need to give auto-negotiation
831 * time to complete.
832 */
833 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
834 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
835 if (!mac->autoneg_failed) {
836 mac->autoneg_failed = true;
837 return E1000_SUCCESS;
838 }
839 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
840
841 /* Disable auto-negotiation in the TXCW register */
842 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
843
844 /* Force link-up and also force full-duplex. */
845 ctrl = E1000_READ_REG(hw, E1000_CTRL);
846 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
847 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
848
849 /* Configure Flow Control after forcing link up. */
850 ret_val = e1000_config_fc_after_link_up_generic(hw);
851 if (ret_val) {
852 DEBUGOUT("Error configuring flow control\n");
853 return ret_val;
854 }
855 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
856 /* If we are forcing link and we are receiving /C/ ordered
857 * sets, re-enable auto-negotiation in the TXCW register
858 * and disable forced link in the Device Control register
859 * in an attempt to auto-negotiate with our link partner.
860 */
861 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
862 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
863 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
864
865 mac->serdes_has_link = true;
866 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
867 /* If we force link for non-auto-negotiation switch, check
868 * link status based on MAC synchronization for internal
869 * serdes media type.
870 */
871 /* SYNCH bit and IV bit are sticky. */
872 usec_delay(10);
873 rxcw = E1000_READ_REG(hw, E1000_RXCW);
874 if (rxcw & E1000_RXCW_SYNCH) {
875 if (!(rxcw & E1000_RXCW_IV)) {
876 mac->serdes_has_link = true;
877 DEBUGOUT("SERDES: Link up - forced.\n");
878 }
879 } else {
880 mac->serdes_has_link = false;
881 DEBUGOUT("SERDES: Link down - force failed.\n");
882 }
883 }
884
885 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
886 status = E1000_READ_REG(hw, E1000_STATUS);
887 if (status & E1000_STATUS_LU) {
888 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
889 usec_delay(10);
890 rxcw = E1000_READ_REG(hw, E1000_RXCW);
891 if (rxcw & E1000_RXCW_SYNCH) {
892 if (!(rxcw & E1000_RXCW_IV)) {
893 mac->serdes_has_link = true;
894 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
895 } else {
896 mac->serdes_has_link = false;
897 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
898 }
899 } else {
900 mac->serdes_has_link = false;
901 DEBUGOUT("SERDES: Link down - no sync.\n");
902 }
903 } else {
904 mac->serdes_has_link = false;
905 DEBUGOUT("SERDES: Link down - autoneg failed\n");
906 }
907 }
908
909 return E1000_SUCCESS;
910 }
911
912 /**
913 * e1000_set_default_fc_generic - Set flow control default values
914 * @hw: pointer to the HW structure
915 *
916 * Read the EEPROM for the default values for flow control and store the
917 * values.
918 **/
e1000_set_default_fc_generic(struct e1000_hw * hw)919 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
920 {
921 s32 ret_val;
922 u16 nvm_data;
923 u16 nvm_offset = 0;
924
925 DEBUGFUNC("e1000_set_default_fc_generic");
926
927 /* Read and store word 0x0F of the EEPROM. This word contains bits
928 * that determine the hardware's default PAUSE (flow control) mode,
929 * a bit that determines whether the HW defaults to enabling or
930 * disabling auto-negotiation, and the direction of the
931 * SW defined pins. If there is no SW over-ride of the flow
932 * control setting, then the variable hw->fc will
933 * be initialized based on a value in the EEPROM.
934 */
935 if (hw->mac.type == e1000_i350) {
936 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
937 ret_val = hw->nvm.ops.read(hw,
938 NVM_INIT_CONTROL2_REG +
939 nvm_offset,
940 1, &nvm_data);
941 } else {
942 ret_val = hw->nvm.ops.read(hw,
943 NVM_INIT_CONTROL2_REG,
944 1, &nvm_data);
945 }
946
947
948 if (ret_val) {
949 DEBUGOUT("NVM Read Error\n");
950 return ret_val;
951 }
952
953 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
954 hw->fc.requested_mode = e1000_fc_none;
955 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
956 NVM_WORD0F_ASM_DIR)
957 hw->fc.requested_mode = e1000_fc_tx_pause;
958 else
959 hw->fc.requested_mode = e1000_fc_full;
960
961 return E1000_SUCCESS;
962 }
963
964 /**
965 * e1000_setup_link_generic - Setup flow control and link settings
966 * @hw: pointer to the HW structure
967 *
968 * Determines which flow control settings to use, then configures flow
969 * control. Calls the appropriate media-specific link configuration
970 * function. Assuming the adapter has a valid link partner, a valid link
971 * should be established. Assumes the hardware has previously been reset
972 * and the transmitter and receiver are not enabled.
973 **/
e1000_setup_link_generic(struct e1000_hw * hw)974 s32 e1000_setup_link_generic(struct e1000_hw *hw)
975 {
976 s32 ret_val;
977
978 DEBUGFUNC("e1000_setup_link_generic");
979
980 /* In the case of the phy reset being blocked, we already have a link.
981 * We do not need to set it up again.
982 */
983 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
984 return E1000_SUCCESS;
985
986 /* If requested flow control is set to default, set flow control
987 * based on the EEPROM flow control settings.
988 */
989 if (hw->fc.requested_mode == e1000_fc_default) {
990 ret_val = e1000_set_default_fc_generic(hw);
991 if (ret_val)
992 return ret_val;
993 }
994
995 /* Save off the requested flow control mode for use later. Depending
996 * on the link partner's capabilities, we may or may not use this mode.
997 */
998 hw->fc.current_mode = hw->fc.requested_mode;
999
1000 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1001 hw->fc.current_mode);
1002
1003 /* Call the necessary media_type subroutine to configure the link. */
1004 ret_val = hw->mac.ops.setup_physical_interface(hw);
1005 if (ret_val)
1006 return ret_val;
1007
1008 /* Initialize the flow control address, type, and PAUSE timer
1009 * registers to their default values. This is done even if flow
1010 * control is disabled, because it does not hurt anything to
1011 * initialize these registers.
1012 */
1013 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1014 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1015 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1016 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1017
1018 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1019
1020 return e1000_set_fc_watermarks_generic(hw);
1021 }
1022
1023 /**
1024 * e1000_commit_fc_settings_generic - Configure flow control
1025 * @hw: pointer to the HW structure
1026 *
1027 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1028 * base on the flow control settings in e1000_mac_info.
1029 **/
e1000_commit_fc_settings_generic(struct e1000_hw * hw)1030 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1031 {
1032 struct e1000_mac_info *mac = &hw->mac;
1033 u32 txcw;
1034
1035 DEBUGFUNC("e1000_commit_fc_settings_generic");
1036
1037 /* Check for a software override of the flow control settings, and
1038 * setup the device accordingly. If auto-negotiation is enabled, then
1039 * software will have to set the "PAUSE" bits to the correct value in
1040 * the Transmit Config Word Register (TXCW) and re-start auto-
1041 * negotiation. However, if auto-negotiation is disabled, then
1042 * software will have to manually configure the two flow control enable
1043 * bits in the CTRL register.
1044 *
1045 * The possible values of the "fc" parameter are:
1046 * 0: Flow control is completely disabled
1047 * 1: Rx flow control is enabled (we can receive pause frames,
1048 * but not send pause frames).
1049 * 2: Tx flow control is enabled (we can send pause frames but we
1050 * do not support receiving pause frames).
1051 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1052 */
1053 switch (hw->fc.current_mode) {
1054 case e1000_fc_none:
1055 /* Flow control completely disabled by a software over-ride. */
1056 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1057 break;
1058 case e1000_fc_rx_pause:
1059 /* Rx Flow control is enabled and Tx Flow control is disabled
1060 * by a software over-ride. Since there really isn't a way to
1061 * advertise that we are capable of Rx Pause ONLY, we will
1062 * advertise that we support both symmetric and asymmetric Rx
1063 * PAUSE. Later, we will disable the adapter's ability to send
1064 * PAUSE frames.
1065 */
1066 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1067 break;
1068 case e1000_fc_tx_pause:
1069 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1070 * by a software over-ride.
1071 */
1072 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1073 break;
1074 case e1000_fc_full:
1075 /* Flow control (both Rx and Tx) is enabled by a software
1076 * over-ride.
1077 */
1078 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1079 break;
1080 default:
1081 DEBUGOUT("Flow control param set incorrectly\n");
1082 return -E1000_ERR_CONFIG;
1083 break;
1084 }
1085
1086 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1087 mac->txcw = txcw;
1088
1089 return E1000_SUCCESS;
1090 }
1091
1092 /**
1093 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1094 * @hw: pointer to the HW structure
1095 *
1096 * Polls for link up by reading the status register, if link fails to come
1097 * up with auto-negotiation, then the link is forced if a signal is detected.
1098 **/
e1000_poll_fiber_serdes_link_generic(struct e1000_hw * hw)1099 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1100 {
1101 struct e1000_mac_info *mac = &hw->mac;
1102 u32 i, status;
1103 s32 ret_val;
1104
1105 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1106
1107 /* If we have a signal (the cable is plugged in, or assumed true for
1108 * serdes media) then poll for a "Link-Up" indication in the Device
1109 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1110 * seconds (Auto-negotiation should complete in less than 500
1111 * milliseconds even if the other end is doing it in SW).
1112 */
1113 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1114 msec_delay(10);
1115 status = E1000_READ_REG(hw, E1000_STATUS);
1116 if (status & E1000_STATUS_LU)
1117 break;
1118 }
1119 if (i == FIBER_LINK_UP_LIMIT) {
1120 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1121 mac->autoneg_failed = true;
1122 /* AutoNeg failed to achieve a link, so we'll call
1123 * mac->check_for_link. This routine will force the
1124 * link up if we detect a signal. This will allow us to
1125 * communicate with non-autonegotiating link partners.
1126 */
1127 ret_val = mac->ops.check_for_link(hw);
1128 if (ret_val) {
1129 DEBUGOUT("Error while checking for link\n");
1130 return ret_val;
1131 }
1132 mac->autoneg_failed = false;
1133 } else {
1134 mac->autoneg_failed = false;
1135 DEBUGOUT("Valid Link Found\n");
1136 }
1137
1138 return E1000_SUCCESS;
1139 }
1140
1141 /**
1142 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1143 * @hw: pointer to the HW structure
1144 *
1145 * Configures collision distance and flow control for fiber and serdes
1146 * links. Upon successful setup, poll for link.
1147 **/
e1000_setup_fiber_serdes_link_generic(struct e1000_hw * hw)1148 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1149 {
1150 u32 ctrl;
1151 s32 ret_val;
1152
1153 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1154
1155 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1156
1157 /* Take the link out of reset */
1158 ctrl &= ~E1000_CTRL_LRST;
1159
1160 hw->mac.ops.config_collision_dist(hw);
1161
1162 ret_val = e1000_commit_fc_settings_generic(hw);
1163 if (ret_val)
1164 return ret_val;
1165
1166 /* Since auto-negotiation is enabled, take the link out of reset (the
1167 * link will be in reset, because we previously reset the chip). This
1168 * will restart auto-negotiation. If auto-negotiation is successful
1169 * then the link-up status bit will be set and the flow control enable
1170 * bits (RFCE and TFCE) will be set according to their negotiated value.
1171 */
1172 DEBUGOUT("Auto-negotiation enabled\n");
1173
1174 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1175 E1000_WRITE_FLUSH(hw);
1176 msec_delay(1);
1177
1178 /* For these adapters, the SW definable pin 1 is set when the optics
1179 * detect a signal. If we have a signal, then poll for a "Link-Up"
1180 * indication.
1181 */
1182 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1183 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1184 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1185 } else {
1186 DEBUGOUT("No signal detected\n");
1187 }
1188
1189 return ret_val;
1190 }
1191
1192 /**
1193 * e1000_config_collision_dist_generic - Configure collision distance
1194 * @hw: pointer to the HW structure
1195 *
1196 * Configures the collision distance to the default value and is used
1197 * during link setup.
1198 **/
e1000_config_collision_dist_generic(struct e1000_hw * hw)1199 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1200 {
1201 u32 tctl;
1202
1203 DEBUGFUNC("e1000_config_collision_dist_generic");
1204
1205 tctl = E1000_READ_REG(hw, E1000_TCTL);
1206
1207 tctl &= ~E1000_TCTL_COLD;
1208 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1209
1210 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1211 E1000_WRITE_FLUSH(hw);
1212 }
1213
1214 /**
1215 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1216 * @hw: pointer to the HW structure
1217 *
1218 * Sets the flow control high/low threshold (watermark) registers. If
1219 * flow control XON frame transmission is enabled, then set XON frame
1220 * transmission as well.
1221 **/
e1000_set_fc_watermarks_generic(struct e1000_hw * hw)1222 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1223 {
1224 u32 fcrtl = 0, fcrth = 0;
1225
1226 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1227
1228 /* Set the flow control receive threshold registers. Normally,
1229 * these registers will be set to a default threshold that may be
1230 * adjusted later by the driver's runtime code. However, if the
1231 * ability to transmit pause frames is not enabled, then these
1232 * registers will be set to 0.
1233 */
1234 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1235 /* We need to set up the Receive Threshold high and low water
1236 * marks as well as (optionally) enabling the transmission of
1237 * XON frames.
1238 */
1239 fcrtl = hw->fc.low_water;
1240 if (hw->fc.send_xon)
1241 fcrtl |= E1000_FCRTL_XONE;
1242
1243 fcrth = hw->fc.high_water;
1244 }
1245 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1246 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1247
1248 return E1000_SUCCESS;
1249 }
1250
1251 /**
1252 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1253 * @hw: pointer to the HW structure
1254 *
1255 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1256 * device control register to reflect the adapter settings. TFCE and RFCE
1257 * need to be explicitly set by software when a copper PHY is used because
1258 * autonegotiation is managed by the PHY rather than the MAC. Software must
1259 * also configure these bits when link is forced on a fiber connection.
1260 **/
e1000_force_mac_fc_generic(struct e1000_hw * hw)1261 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1262 {
1263 u32 ctrl;
1264
1265 DEBUGFUNC("e1000_force_mac_fc_generic");
1266
1267 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1268
1269 /* Because we didn't get link via the internal auto-negotiation
1270 * mechanism (we either forced link or we got link via PHY
1271 * auto-neg), we have to manually enable/disable transmit an
1272 * receive flow control.
1273 *
1274 * The "Case" statement below enables/disable flow control
1275 * according to the "hw->fc.current_mode" parameter.
1276 *
1277 * The possible values of the "fc" parameter are:
1278 * 0: Flow control is completely disabled
1279 * 1: Rx flow control is enabled (we can receive pause
1280 * frames but not send pause frames).
1281 * 2: Tx flow control is enabled (we can send pause frames
1282 * frames but we do not receive pause frames).
1283 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1284 * other: No other values should be possible at this point.
1285 */
1286 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1287
1288 switch (hw->fc.current_mode) {
1289 case e1000_fc_none:
1290 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1291 break;
1292 case e1000_fc_rx_pause:
1293 ctrl &= (~E1000_CTRL_TFCE);
1294 ctrl |= E1000_CTRL_RFCE;
1295 break;
1296 case e1000_fc_tx_pause:
1297 ctrl &= (~E1000_CTRL_RFCE);
1298 ctrl |= E1000_CTRL_TFCE;
1299 break;
1300 case e1000_fc_full:
1301 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1302 break;
1303 default:
1304 DEBUGOUT("Flow control param set incorrectly\n");
1305 return -E1000_ERR_CONFIG;
1306 }
1307
1308 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1309
1310 return E1000_SUCCESS;
1311 }
1312
1313 /**
1314 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1315 * @hw: pointer to the HW structure
1316 *
1317 * Checks the status of auto-negotiation after link up to ensure that the
1318 * speed and duplex were not forced. If the link needed to be forced, then
1319 * flow control needs to be forced also. If auto-negotiation is enabled
1320 * and did not fail, then we configure flow control based on our link
1321 * partner.
1322 **/
e1000_config_fc_after_link_up_generic(struct e1000_hw * hw)1323 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1324 {
1325 struct e1000_mac_info *mac = &hw->mac;
1326 s32 ret_val = E1000_SUCCESS;
1327 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1328 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1329 u16 speed, duplex;
1330
1331 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1332
1333 /* Check for the case where we have fiber media and auto-neg failed
1334 * so we had to force link. In this case, we need to force the
1335 * configuration of the MAC to match the "fc" parameter.
1336 */
1337 if (mac->autoneg_failed) {
1338 if (hw->phy.media_type == e1000_media_type_fiber ||
1339 hw->phy.media_type == e1000_media_type_internal_serdes)
1340 ret_val = e1000_force_mac_fc_generic(hw);
1341 } else {
1342 if (hw->phy.media_type == e1000_media_type_copper)
1343 ret_val = e1000_force_mac_fc_generic(hw);
1344 }
1345
1346 if (ret_val) {
1347 DEBUGOUT("Error forcing flow control settings\n");
1348 return ret_val;
1349 }
1350
1351 /* Check for the case where we have copper media and auto-neg is
1352 * enabled. In this case, we need to check and see if Auto-Neg
1353 * has completed, and if so, how the PHY and link partner has
1354 * flow control configured.
1355 */
1356 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1357 /* Read the MII Status Register and check to see if AutoNeg
1358 * has completed. We read this twice because this reg has
1359 * some "sticky" (latched) bits.
1360 */
1361 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1362 if (ret_val)
1363 return ret_val;
1364 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1365 if (ret_val)
1366 return ret_val;
1367
1368 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1369 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1370 return ret_val;
1371 }
1372
1373 /* The AutoNeg process has completed, so we now need to
1374 * read both the Auto Negotiation Advertisement
1375 * Register (Address 4) and the Auto_Negotiation Base
1376 * Page Ability Register (Address 5) to determine how
1377 * flow control was negotiated.
1378 */
1379 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1380 &mii_nway_adv_reg);
1381 if (ret_val)
1382 return ret_val;
1383 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1384 &mii_nway_lp_ability_reg);
1385 if (ret_val)
1386 return ret_val;
1387
1388 /* Two bits in the Auto Negotiation Advertisement Register
1389 * (Address 4) and two bits in the Auto Negotiation Base
1390 * Page Ability Register (Address 5) determine flow control
1391 * for both the PHY and the link partner. The following
1392 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1393 * 1999, describes these PAUSE resolution bits and how flow
1394 * control is determined based upon these settings.
1395 * NOTE: DC = Don't Care
1396 *
1397 * LOCAL DEVICE | LINK PARTNER
1398 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1399 *-------|---------|-------|---------|--------------------
1400 * 0 | 0 | DC | DC | e1000_fc_none
1401 * 0 | 1 | 0 | DC | e1000_fc_none
1402 * 0 | 1 | 1 | 0 | e1000_fc_none
1403 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1404 * 1 | 0 | 0 | DC | e1000_fc_none
1405 * 1 | DC | 1 | DC | e1000_fc_full
1406 * 1 | 1 | 0 | 0 | e1000_fc_none
1407 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1408 *
1409 * Are both PAUSE bits set to 1? If so, this implies
1410 * Symmetric Flow Control is enabled at both ends. The
1411 * ASM_DIR bits are irrelevant per the spec.
1412 *
1413 * For Symmetric Flow Control:
1414 *
1415 * LOCAL DEVICE | LINK PARTNER
1416 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1417 *-------|---------|-------|---------|--------------------
1418 * 1 | DC | 1 | DC | E1000_fc_full
1419 *
1420 */
1421 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1422 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1423 /* Now we need to check if the user selected Rx ONLY
1424 * of pause frames. In this case, we had to advertise
1425 * FULL flow control because we could not advertise Rx
1426 * ONLY. Hence, we must now check to see if we need to
1427 * turn OFF the TRANSMISSION of PAUSE frames.
1428 */
1429 if (hw->fc.requested_mode == e1000_fc_full) {
1430 hw->fc.current_mode = e1000_fc_full;
1431 DEBUGOUT("Flow Control = FULL.\n");
1432 } else {
1433 hw->fc.current_mode = e1000_fc_rx_pause;
1434 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1435 }
1436 }
1437 /* For receiving PAUSE frames ONLY.
1438 *
1439 * LOCAL DEVICE | LINK PARTNER
1440 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1441 *-------|---------|-------|---------|--------------------
1442 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1443 */
1444 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1445 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1446 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1447 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1448 hw->fc.current_mode = e1000_fc_tx_pause;
1449 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1450 }
1451 /* For transmitting PAUSE frames ONLY.
1452 *
1453 * LOCAL DEVICE | LINK PARTNER
1454 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1455 *-------|---------|-------|---------|--------------------
1456 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1457 */
1458 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1459 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1460 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1461 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1462 hw->fc.current_mode = e1000_fc_rx_pause;
1463 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1464 } else {
1465 /* Per the IEEE spec, at this point flow control
1466 * should be disabled.
1467 */
1468 hw->fc.current_mode = e1000_fc_none;
1469 DEBUGOUT("Flow Control = NONE.\n");
1470 }
1471
1472 /* Now we need to do one last check... If we auto-
1473 * negotiated to HALF DUPLEX, flow control should not be
1474 * enabled per IEEE 802.3 spec.
1475 */
1476 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1477 if (ret_val) {
1478 DEBUGOUT("Error getting link speed and duplex\n");
1479 return ret_val;
1480 }
1481
1482 if (duplex == HALF_DUPLEX)
1483 hw->fc.current_mode = e1000_fc_none;
1484
1485 /* Now we call a subroutine to actually force the MAC
1486 * controller to use the correct flow control settings.
1487 */
1488 ret_val = e1000_force_mac_fc_generic(hw);
1489 if (ret_val) {
1490 DEBUGOUT("Error forcing flow control settings\n");
1491 return ret_val;
1492 }
1493 }
1494
1495 /* Check for the case where we have SerDes media and auto-neg is
1496 * enabled. In this case, we need to check and see if Auto-Neg
1497 * has completed, and if so, how the PHY and link partner has
1498 * flow control configured.
1499 */
1500 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1501 mac->autoneg) {
1502 /* Read the PCS_LSTS and check to see if AutoNeg
1503 * has completed.
1504 */
1505 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1506
1507 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1508 DEBUGOUT("PCS Auto Neg has not completed.\n");
1509 return ret_val;
1510 }
1511
1512 /* The AutoNeg process has completed, so we now need to
1513 * read both the Auto Negotiation Advertisement
1514 * Register (PCS_ANADV) and the Auto_Negotiation Base
1515 * Page Ability Register (PCS_LPAB) to determine how
1516 * flow control was negotiated.
1517 */
1518 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1519 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1520
1521 /* Two bits in the Auto Negotiation Advertisement Register
1522 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1523 * Page Ability Register (PCS_LPAB) determine flow control
1524 * for both the PHY and the link partner. The following
1525 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1526 * 1999, describes these PAUSE resolution bits and how flow
1527 * control is determined based upon these settings.
1528 * NOTE: DC = Don't Care
1529 *
1530 * LOCAL DEVICE | LINK PARTNER
1531 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1532 *-------|---------|-------|---------|--------------------
1533 * 0 | 0 | DC | DC | e1000_fc_none
1534 * 0 | 1 | 0 | DC | e1000_fc_none
1535 * 0 | 1 | 1 | 0 | e1000_fc_none
1536 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1537 * 1 | 0 | 0 | DC | e1000_fc_none
1538 * 1 | DC | 1 | DC | e1000_fc_full
1539 * 1 | 1 | 0 | 0 | e1000_fc_none
1540 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1541 *
1542 * Are both PAUSE bits set to 1? If so, this implies
1543 * Symmetric Flow Control is enabled at both ends. The
1544 * ASM_DIR bits are irrelevant per the spec.
1545 *
1546 * For Symmetric Flow Control:
1547 *
1548 * LOCAL DEVICE | LINK PARTNER
1549 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1550 *-------|---------|-------|---------|--------------------
1551 * 1 | DC | 1 | DC | e1000_fc_full
1552 *
1553 */
1554 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1555 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1556 /* Now we need to check if the user selected Rx ONLY
1557 * of pause frames. In this case, we had to advertise
1558 * FULL flow control because we could not advertise Rx
1559 * ONLY. Hence, we must now check to see if we need to
1560 * turn OFF the TRANSMISSION of PAUSE frames.
1561 */
1562 if (hw->fc.requested_mode == e1000_fc_full) {
1563 hw->fc.current_mode = e1000_fc_full;
1564 DEBUGOUT("Flow Control = FULL.\n");
1565 } else {
1566 hw->fc.current_mode = e1000_fc_rx_pause;
1567 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1568 }
1569 }
1570 /* For receiving PAUSE frames ONLY.
1571 *
1572 * LOCAL DEVICE | LINK PARTNER
1573 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1574 *-------|---------|-------|---------|--------------------
1575 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1576 */
1577 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1578 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1579 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1580 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1581 hw->fc.current_mode = e1000_fc_tx_pause;
1582 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1583 }
1584 /* For transmitting PAUSE frames ONLY.
1585 *
1586 * LOCAL DEVICE | LINK PARTNER
1587 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1588 *-------|---------|-------|---------|--------------------
1589 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1590 */
1591 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1592 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1593 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1594 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1595 hw->fc.current_mode = e1000_fc_rx_pause;
1596 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1597 } else {
1598 /* Per the IEEE spec, at this point flow control
1599 * should be disabled.
1600 */
1601 hw->fc.current_mode = e1000_fc_none;
1602 DEBUGOUT("Flow Control = NONE.\n");
1603 }
1604
1605 /* Now we call a subroutine to actually force the MAC
1606 * controller to use the correct flow control settings.
1607 */
1608 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1609 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1610 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1611
1612 ret_val = e1000_force_mac_fc_generic(hw);
1613 if (ret_val) {
1614 DEBUGOUT("Error forcing flow control settings\n");
1615 return ret_val;
1616 }
1617 }
1618
1619 return E1000_SUCCESS;
1620 }
1621
1622 /**
1623 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1624 * @hw: pointer to the HW structure
1625 * @speed: stores the current speed
1626 * @duplex: stores the current duplex
1627 *
1628 * Read the status register for the current speed/duplex and store the current
1629 * speed and duplex for copper connections.
1630 **/
e1000_get_speed_and_duplex_copper_generic(struct e1000_hw * hw,u16 * speed,u16 * duplex)1631 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1632 u16 *duplex)
1633 {
1634 u32 status;
1635
1636 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1637
1638 status = E1000_READ_REG(hw, E1000_STATUS);
1639 if (status & E1000_STATUS_SPEED_1000) {
1640 *speed = SPEED_1000;
1641 DEBUGOUT("1000 Mbs, ");
1642 } else if (status & E1000_STATUS_SPEED_100) {
1643 *speed = SPEED_100;
1644 DEBUGOUT("100 Mbs, ");
1645 } else {
1646 *speed = SPEED_10;
1647 DEBUGOUT("10 Mbs, ");
1648 }
1649
1650 if (status & E1000_STATUS_FD) {
1651 *duplex = FULL_DUPLEX;
1652 DEBUGOUT("Full Duplex\n");
1653 } else {
1654 *duplex = HALF_DUPLEX;
1655 DEBUGOUT("Half Duplex\n");
1656 }
1657
1658 return E1000_SUCCESS;
1659 }
1660
1661 /**
1662 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1663 * @hw: pointer to the HW structure
1664 * @speed: stores the current speed
1665 * @duplex: stores the current duplex
1666 *
1667 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1668 * for fiber/serdes links.
1669 **/
e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG * hw,u16 * speed,u16 * duplex)1670 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1671 u16 *speed, u16 *duplex)
1672 {
1673 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1674 UNREFERENCED_1PARAMETER(hw);
1675
1676 *speed = SPEED_1000;
1677 *duplex = FULL_DUPLEX;
1678
1679 return E1000_SUCCESS;
1680 }
1681
1682 /**
1683 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1684 * @hw: pointer to the HW structure
1685 *
1686 * Acquire the HW semaphore to access the PHY or NVM
1687 **/
e1000_get_hw_semaphore_generic(struct e1000_hw * hw)1688 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1689 {
1690 u32 swsm;
1691 s32 timeout = hw->nvm.word_size + 1;
1692 s32 i = 0;
1693
1694 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1695
1696 /* Get the SW semaphore */
1697 while (i < timeout) {
1698 swsm = E1000_READ_REG(hw, E1000_SWSM);
1699 if (!(swsm & E1000_SWSM_SMBI))
1700 break;
1701
1702 usec_delay(50);
1703 i++;
1704 }
1705
1706 if (i == timeout) {
1707 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1708 return -E1000_ERR_NVM;
1709 }
1710
1711 /* Get the FW semaphore. */
1712 for (i = 0; i < timeout; i++) {
1713 swsm = E1000_READ_REG(hw, E1000_SWSM);
1714 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1715
1716 /* Semaphore acquired if bit latched */
1717 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1718 break;
1719
1720 usec_delay(50);
1721 }
1722
1723 if (i == timeout) {
1724 /* Release semaphores */
1725 e1000_put_hw_semaphore_generic(hw);
1726 DEBUGOUT("Driver can't access the NVM\n");
1727 return -E1000_ERR_NVM;
1728 }
1729
1730 return E1000_SUCCESS;
1731 }
1732
1733 /**
1734 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1735 * @hw: pointer to the HW structure
1736 *
1737 * Release hardware semaphore used to access the PHY or NVM
1738 **/
e1000_put_hw_semaphore_generic(struct e1000_hw * hw)1739 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1740 {
1741 u32 swsm;
1742
1743 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1744
1745 swsm = E1000_READ_REG(hw, E1000_SWSM);
1746
1747 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1748
1749 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1750 }
1751
1752 /**
1753 * e1000_get_auto_rd_done_generic - Check for auto read completion
1754 * @hw: pointer to the HW structure
1755 *
1756 * Check EEPROM for Auto Read done bit.
1757 **/
e1000_get_auto_rd_done_generic(struct e1000_hw * hw)1758 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1759 {
1760 s32 i = 0;
1761
1762 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1763
1764 while (i < AUTO_READ_DONE_TIMEOUT) {
1765 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1766 break;
1767 msec_delay(1);
1768 i++;
1769 }
1770
1771 if (i == AUTO_READ_DONE_TIMEOUT) {
1772 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1773 return -E1000_ERR_RESET;
1774 }
1775
1776 return E1000_SUCCESS;
1777 }
1778
1779 /**
1780 * e1000_valid_led_default_generic - Verify a valid default LED config
1781 * @hw: pointer to the HW structure
1782 * @data: pointer to the NVM (EEPROM)
1783 *
1784 * Read the EEPROM for the current default LED configuration. If the
1785 * LED configuration is not valid, set to a valid LED configuration.
1786 **/
e1000_valid_led_default_generic(struct e1000_hw * hw,u16 * data)1787 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1788 {
1789 s32 ret_val;
1790
1791 DEBUGFUNC("e1000_valid_led_default_generic");
1792
1793 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1794 if (ret_val) {
1795 DEBUGOUT("NVM Read Error\n");
1796 return ret_val;
1797 }
1798
1799 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1800 *data = ID_LED_DEFAULT;
1801
1802 return E1000_SUCCESS;
1803 }
1804
1805 /**
1806 * e1000_id_led_init_generic -
1807 * @hw: pointer to the HW structure
1808 *
1809 **/
e1000_id_led_init_generic(struct e1000_hw * hw)1810 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1811 {
1812 struct e1000_mac_info *mac = &hw->mac;
1813 s32 ret_val;
1814 const u32 ledctl_mask = 0x000000FF;
1815 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1816 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1817 u16 data, i, temp;
1818 const u16 led_mask = 0x0F;
1819
1820 DEBUGFUNC("e1000_id_led_init_generic");
1821
1822 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1823 if (ret_val)
1824 return ret_val;
1825
1826 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1827 mac->ledctl_mode1 = mac->ledctl_default;
1828 mac->ledctl_mode2 = mac->ledctl_default;
1829
1830 for (i = 0; i < 4; i++) {
1831 temp = (data >> (i << 2)) & led_mask;
1832 switch (temp) {
1833 case ID_LED_ON1_DEF2:
1834 case ID_LED_ON1_ON2:
1835 case ID_LED_ON1_OFF2:
1836 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1837 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1838 break;
1839 case ID_LED_OFF1_DEF2:
1840 case ID_LED_OFF1_ON2:
1841 case ID_LED_OFF1_OFF2:
1842 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1843 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1844 break;
1845 default:
1846 /* Do nothing */
1847 break;
1848 }
1849 switch (temp) {
1850 case ID_LED_DEF1_ON2:
1851 case ID_LED_ON1_ON2:
1852 case ID_LED_OFF1_ON2:
1853 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1854 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1855 break;
1856 case ID_LED_DEF1_OFF2:
1857 case ID_LED_ON1_OFF2:
1858 case ID_LED_OFF1_OFF2:
1859 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1860 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1861 break;
1862 default:
1863 /* Do nothing */
1864 break;
1865 }
1866 }
1867
1868 return E1000_SUCCESS;
1869 }
1870
1871 /**
1872 * e1000_setup_led_generic - Configures SW controllable LED
1873 * @hw: pointer to the HW structure
1874 *
1875 * This prepares the SW controllable LED for use and saves the current state
1876 * of the LED so it can be later restored.
1877 **/
e1000_setup_led_generic(struct e1000_hw * hw)1878 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1879 {
1880 u32 ledctl;
1881
1882 DEBUGFUNC("e1000_setup_led_generic");
1883
1884 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1885 return -E1000_ERR_CONFIG;
1886
1887 if (hw->phy.media_type == e1000_media_type_fiber) {
1888 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1889 hw->mac.ledctl_default = ledctl;
1890 /* Turn off LED0 */
1891 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1892 E1000_LEDCTL_LED0_MODE_MASK);
1893 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1894 E1000_LEDCTL_LED0_MODE_SHIFT);
1895 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1896 } else if (hw->phy.media_type == e1000_media_type_copper) {
1897 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1898 }
1899
1900 return E1000_SUCCESS;
1901 }
1902
1903 /**
1904 * e1000_cleanup_led_generic - Set LED config to default operation
1905 * @hw: pointer to the HW structure
1906 *
1907 * Remove the current LED configuration and set the LED configuration
1908 * to the default value, saved from the EEPROM.
1909 **/
e1000_cleanup_led_generic(struct e1000_hw * hw)1910 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1911 {
1912 DEBUGFUNC("e1000_cleanup_led_generic");
1913
1914 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1915 return E1000_SUCCESS;
1916 }
1917
1918 /**
1919 * e1000_blink_led_generic - Blink LED
1920 * @hw: pointer to the HW structure
1921 *
1922 * Blink the LEDs which are set to be on.
1923 **/
e1000_blink_led_generic(struct e1000_hw * hw)1924 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1925 {
1926 u32 ledctl_blink = 0;
1927 u32 i;
1928
1929 DEBUGFUNC("e1000_blink_led_generic");
1930
1931 if (hw->phy.media_type == e1000_media_type_fiber) {
1932 /* always blink LED0 for PCI-E fiber */
1933 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1934 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1935 } else {
1936 /* Set the blink bit for each LED that's "on" (0x0E)
1937 * (or "off" if inverted) in ledctl_mode2. The blink
1938 * logic in hardware only works when mode is set to "on"
1939 * so it must be changed accordingly when the mode is
1940 * "off" and inverted.
1941 */
1942 ledctl_blink = hw->mac.ledctl_mode2;
1943 for (i = 0; i < 32; i += 8) {
1944 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1945 E1000_LEDCTL_LED0_MODE_MASK;
1946 u32 led_default = hw->mac.ledctl_default >> i;
1947
1948 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1949 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1950 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1951 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1952 ledctl_blink &=
1953 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1954 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1955 E1000_LEDCTL_MODE_LED_ON) << i;
1956 }
1957 }
1958 }
1959
1960 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1961
1962 return E1000_SUCCESS;
1963 }
1964
1965 /**
1966 * e1000_led_on_generic - Turn LED on
1967 * @hw: pointer to the HW structure
1968 *
1969 * Turn LED on.
1970 **/
e1000_led_on_generic(struct e1000_hw * hw)1971 s32 e1000_led_on_generic(struct e1000_hw *hw)
1972 {
1973 u32 ctrl;
1974
1975 DEBUGFUNC("e1000_led_on_generic");
1976
1977 switch (hw->phy.media_type) {
1978 case e1000_media_type_fiber:
1979 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1980 ctrl &= ~E1000_CTRL_SWDPIN0;
1981 ctrl |= E1000_CTRL_SWDPIO0;
1982 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1983 break;
1984 case e1000_media_type_copper:
1985 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1986 break;
1987 default:
1988 break;
1989 }
1990
1991 return E1000_SUCCESS;
1992 }
1993
1994 /**
1995 * e1000_led_off_generic - Turn LED off
1996 * @hw: pointer to the HW structure
1997 *
1998 * Turn LED off.
1999 **/
e1000_led_off_generic(struct e1000_hw * hw)2000 s32 e1000_led_off_generic(struct e1000_hw *hw)
2001 {
2002 u32 ctrl;
2003
2004 DEBUGFUNC("e1000_led_off_generic");
2005
2006 switch (hw->phy.media_type) {
2007 case e1000_media_type_fiber:
2008 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2009 ctrl |= E1000_CTRL_SWDPIN0;
2010 ctrl |= E1000_CTRL_SWDPIO0;
2011 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2012 break;
2013 case e1000_media_type_copper:
2014 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2015 break;
2016 default:
2017 break;
2018 }
2019
2020 return E1000_SUCCESS;
2021 }
2022
2023 /**
2024 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2025 * @hw: pointer to the HW structure
2026 * @no_snoop: bitmap of snoop events
2027 *
2028 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2029 **/
e1000_set_pcie_no_snoop_generic(struct e1000_hw * hw,u32 no_snoop)2030 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2031 {
2032 u32 gcr;
2033
2034 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2035
2036 if (hw->bus.type != e1000_bus_type_pci_express)
2037 return;
2038
2039 if (no_snoop) {
2040 gcr = E1000_READ_REG(hw, E1000_GCR);
2041 gcr &= ~(PCIE_NO_SNOOP_ALL);
2042 gcr |= no_snoop;
2043 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2044 }
2045 }
2046
2047 /**
2048 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2049 * @hw: pointer to the HW structure
2050 *
2051 * Returns E1000_SUCCESS if successful, else returns -10
2052 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2053 * the master requests to be disabled.
2054 *
2055 * Disables PCI-Express master access and verifies there are no pending
2056 * requests.
2057 **/
e1000_disable_pcie_master_generic(struct e1000_hw * hw)2058 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2059 {
2060 u32 ctrl;
2061 s32 timeout = MASTER_DISABLE_TIMEOUT;
2062
2063 DEBUGFUNC("e1000_disable_pcie_master_generic");
2064
2065 if (hw->bus.type != e1000_bus_type_pci_express)
2066 return E1000_SUCCESS;
2067
2068 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2069 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2070 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2071
2072 while (timeout) {
2073 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2074 E1000_STATUS_GIO_MASTER_ENABLE) ||
2075 E1000_REMOVED(hw->hw_addr))
2076 break;
2077 usec_delay(100);
2078 timeout--;
2079 }
2080
2081 if (!timeout) {
2082 DEBUGOUT("Master requests are pending.\n");
2083 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2084 }
2085
2086 return E1000_SUCCESS;
2087 }
2088
2089 /**
2090 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2091 * @hw: pointer to the HW structure
2092 *
2093 * Reset the Adaptive Interframe Spacing throttle to default values.
2094 **/
e1000_reset_adaptive_generic(struct e1000_hw * hw)2095 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2096 {
2097 struct e1000_mac_info *mac = &hw->mac;
2098
2099 DEBUGFUNC("e1000_reset_adaptive_generic");
2100
2101 if (!mac->adaptive_ifs) {
2102 DEBUGOUT("Not in Adaptive IFS mode!\n");
2103 return;
2104 }
2105
2106 mac->current_ifs_val = 0;
2107 mac->ifs_min_val = IFS_MIN;
2108 mac->ifs_max_val = IFS_MAX;
2109 mac->ifs_step_size = IFS_STEP;
2110 mac->ifs_ratio = IFS_RATIO;
2111
2112 mac->in_ifs_mode = false;
2113 E1000_WRITE_REG(hw, E1000_AIT, 0);
2114 }
2115
2116 /**
2117 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2118 * @hw: pointer to the HW structure
2119 *
2120 * Update the Adaptive Interframe Spacing Throttle value based on the
2121 * time between transmitted packets and time between collisions.
2122 **/
e1000_update_adaptive_generic(struct e1000_hw * hw)2123 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2124 {
2125 struct e1000_mac_info *mac = &hw->mac;
2126
2127 DEBUGFUNC("e1000_update_adaptive_generic");
2128
2129 if (!mac->adaptive_ifs) {
2130 DEBUGOUT("Not in Adaptive IFS mode!\n");
2131 return;
2132 }
2133
2134 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2135 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2136 mac->in_ifs_mode = true;
2137 if (mac->current_ifs_val < mac->ifs_max_val) {
2138 if (!mac->current_ifs_val)
2139 mac->current_ifs_val = mac->ifs_min_val;
2140 else
2141 mac->current_ifs_val +=
2142 mac->ifs_step_size;
2143 E1000_WRITE_REG(hw, E1000_AIT,
2144 mac->current_ifs_val);
2145 }
2146 }
2147 } else {
2148 if (mac->in_ifs_mode &&
2149 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2150 mac->current_ifs_val = 0;
2151 mac->in_ifs_mode = false;
2152 E1000_WRITE_REG(hw, E1000_AIT, 0);
2153 }
2154 }
2155 }
2156
2157 /**
2158 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2159 * @hw: pointer to the HW structure
2160 *
2161 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2162 * set, which is forced to MDI mode only.
2163 **/
e1000_validate_mdi_setting_generic(struct e1000_hw * hw)2164 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2165 {
2166 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2167
2168 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2169 DEBUGOUT("Invalid MDI setting detected\n");
2170 hw->phy.mdix = 1;
2171 return -E1000_ERR_CONFIG;
2172 }
2173
2174 return E1000_SUCCESS;
2175 }
2176
2177 /**
2178 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2179 * @hw: pointer to the HW structure
2180 *
2181 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2182 * operation.
2183 **/
e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG * hw)2184 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2185 {
2186 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2187 UNREFERENCED_1PARAMETER(hw);
2188
2189 return E1000_SUCCESS;
2190 }
2191
2192 /**
2193 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2194 * @hw: pointer to the HW structure
2195 * @reg: 32bit register offset such as E1000_SCTL
2196 * @offset: register offset to write to
2197 * @data: data to write at register offset
2198 *
2199 * Writes an address/data control type register. There are several of these
2200 * and they all have the format address << 8 | data and bit 31 is polled for
2201 * completion.
2202 **/
e1000_write_8bit_ctrl_reg_generic(struct e1000_hw * hw,u32 reg,u32 offset,u8 data)2203 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2204 u32 offset, u8 data)
2205 {
2206 u32 i, regvalue = 0;
2207
2208 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2209
2210 /* Set up the address and data */
2211 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2212 E1000_WRITE_REG(hw, reg, regvalue);
2213
2214 /* Poll the ready bit to see if the MDI read completed */
2215 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2216 usec_delay(5);
2217 regvalue = E1000_READ_REG(hw, reg);
2218 if (regvalue & E1000_GEN_CTL_READY)
2219 break;
2220 }
2221 if (!(regvalue & E1000_GEN_CTL_READY)) {
2222 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2223 return -E1000_ERR_PHY;
2224 }
2225
2226 return E1000_SUCCESS;
2227 }
2228