1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2015, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34 /*$FreeBSD$*/
35
36 /* 82562G 10/100 Network Connection
37 * 82562G-2 10/100 Network Connection
38 * 82562GT 10/100 Network Connection
39 * 82562GT-2 10/100 Network Connection
40 * 82562V 10/100 Network Connection
41 * 82562V-2 10/100 Network Connection
42 * 82566DC-2 Gigabit Network Connection
43 * 82566DC Gigabit Network Connection
44 * 82566DM-2 Gigabit Network Connection
45 * 82566DM Gigabit Network Connection
46 * 82566MC Gigabit Network Connection
47 * 82566MM Gigabit Network Connection
48 * 82567LM Gigabit Network Connection
49 * 82567LF Gigabit Network Connection
50 * 82567V Gigabit Network Connection
51 * 82567LM-2 Gigabit Network Connection
52 * 82567LF-2 Gigabit Network Connection
53 * 82567V-2 Gigabit Network Connection
54 * 82567LF-3 Gigabit Network Connection
55 * 82567LM-3 Gigabit Network Connection
56 * 82567LM-4 Gigabit Network Connection
57 * 82577LM Gigabit Network Connection
58 * 82577LC Gigabit Network Connection
59 * 82578DM Gigabit Network Connection
60 * 82578DC Gigabit Network Connection
61 * 82579LM Gigabit Network Connection
62 * 82579V Gigabit Network Connection
63 * Ethernet Connection I217-LM
64 * Ethernet Connection I217-V
65 * Ethernet Connection I218-V
66 * Ethernet Connection I218-LM
67 * Ethernet Connection (2) I218-LM
68 * Ethernet Connection (2) I218-V
69 * Ethernet Connection (3) I218-LM
70 * Ethernet Connection (3) I218-V
71 */
72
73 #include "e1000_api.h"
74
75 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
76 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
77 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
78 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
80 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
81 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
82 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
83 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
84 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
85 u8 *mc_addr_list,
86 u32 mc_addr_count);
87 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
90 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 bool active);
92 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 bool active);
94 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
95 u16 words, u16 *data);
96 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97 u16 *data);
98 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
99 u16 words, u16 *data);
100 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
102 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
103 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
104 u16 *data);
105 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
106 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
111 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
112 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
113 u16 *speed, u16 *duplex);
114 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
118 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
121 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
122 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
123 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
124 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
126 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
127 u32 offset, u8 *data);
128 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 u8 size, u16 *data);
130 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131 u32 *data);
132 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 *data);
134 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135 u32 offset, u32 data);
136 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137 u32 offset, u32 dword);
138 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
139 u32 offset, u16 *data);
140 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
141 u32 offset, u8 byte);
142 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
143 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
145 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
146 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
147 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
148 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
149
150 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
151 /* Offset 04h HSFSTS */
152 union ich8_hws_flash_status {
153 struct ich8_hsfsts {
154 u16 flcdone:1; /* bit 0 Flash Cycle Done */
155 u16 flcerr:1; /* bit 1 Flash Cycle Error */
156 u16 dael:1; /* bit 2 Direct Access error Log */
157 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
158 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
159 u16 reserved1:2; /* bit 13:6 Reserved */
160 u16 reserved2:6; /* bit 13:6 Reserved */
161 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
162 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
163 } hsf_status;
164 u16 regval;
165 };
166
167 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
168 /* Offset 06h FLCTL */
169 union ich8_hws_flash_ctrl {
170 struct ich8_hsflctl {
171 u16 flcgo:1; /* 0 Flash Cycle Go */
172 u16 flcycle:2; /* 2:1 Flash Cycle */
173 u16 reserved:5; /* 7:3 Reserved */
174 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
175 u16 flockdn:6; /* 15:10 Reserved */
176 } hsf_ctrl;
177 u16 regval;
178 };
179
180 /* ICH Flash Region Access Permissions */
181 union ich8_hws_flash_regacc {
182 struct ich8_flracc {
183 u32 grra:8; /* 0:7 GbE region Read Access */
184 u32 grwa:8; /* 8:15 GbE region Write Access */
185 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
186 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
187 } hsf_flregacc;
188 u16 regval;
189 };
190
191 /**
192 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
193 * @hw: pointer to the HW structure
194 *
195 * Test access to the PHY registers by reading the PHY ID registers. If
196 * the PHY ID is already known (e.g. resume path) compare it with known ID,
197 * otherwise assume the read PHY ID is correct if it is valid.
198 *
199 * Assumes the sw/fw/hw semaphore is already acquired.
200 **/
e1000_phy_is_accessible_pchlan(struct e1000_hw * hw)201 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
202 {
203 u16 phy_reg = 0;
204 u32 phy_id = 0;
205 s32 ret_val = 0;
206 u16 retry_count;
207 u32 mac_reg = 0;
208
209 for (retry_count = 0; retry_count < 2; retry_count++) {
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
211 if (ret_val || (phy_reg == 0xFFFF))
212 continue;
213 phy_id = (u32)(phy_reg << 16);
214
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
216 if (ret_val || (phy_reg == 0xFFFF)) {
217 phy_id = 0;
218 continue;
219 }
220 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
221 break;
222 }
223
224 if (hw->phy.id) {
225 if (hw->phy.id == phy_id)
226 goto out;
227 } else if (phy_id) {
228 hw->phy.id = phy_id;
229 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
230 goto out;
231 }
232
233 /* In case the PHY needs to be in mdio slow mode,
234 * set slow mode and try to get the PHY id again.
235 */
236 if (hw->mac.type < e1000_pch_lpt) {
237 hw->phy.ops.release(hw);
238 ret_val = e1000_set_mdio_slow_mode_hv(hw);
239 if (!ret_val)
240 ret_val = e1000_get_phy_id(hw);
241 hw->phy.ops.acquire(hw);
242 }
243
244 if (ret_val)
245 return FALSE;
246 out:
247 if (hw->mac.type >= e1000_pch_lpt) {
248 /* Only unforce SMBus if ME is not active */
249 if (!(E1000_READ_REG(hw, E1000_FWSM) &
250 E1000_ICH_FWSM_FW_VALID)) {
251 /* Unforce SMBus mode in PHY */
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
255
256 /* Unforce SMBus mode in MAC */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
260 }
261 }
262
263 return TRUE;
264 }
265
266 /**
267 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
268 * @hw: pointer to the HW structure
269 *
270 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
271 * used to reset the PHY to a quiescent state when necessary.
272 **/
e1000_toggle_lanphypc_pch_lpt(struct e1000_hw * hw)273 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
274 {
275 u32 mac_reg;
276
277 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
278
279 /* Set Phy Config Counter to 50msec */
280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
281 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
282 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
284
285 /* Toggle LANPHYPC Value bit */
286 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
287 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
288 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
290 E1000_WRITE_FLUSH(hw);
291 msec_delay(1);
292 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
294 E1000_WRITE_FLUSH(hw);
295
296 if (hw->mac.type < e1000_pch_lpt) {
297 msec_delay(50);
298 } else {
299 u16 count = 20;
300
301 do {
302 msec_delay(5);
303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
304 E1000_CTRL_EXT_LPCD) && count--);
305
306 msec_delay(30);
307 }
308 }
309
310 /**
311 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
312 * @hw: pointer to the HW structure
313 *
314 * Workarounds/flow necessary for PHY initialization during driver load
315 * and resume paths.
316 **/
e1000_init_phy_workarounds_pchlan(struct e1000_hw * hw)317 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
318 {
319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
320 s32 ret_val;
321
322 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
323
324 /* Gate automatic PHY configuration by hardware on managed and
325 * non-managed 82579 and newer adapters.
326 */
327 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
328
329 /* It is not possible to be certain of the current state of ULP
330 * so forcibly disable it.
331 */
332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
333 e1000_disable_ulp_lpt_lp(hw, TRUE);
334
335 ret_val = hw->phy.ops.acquire(hw);
336 if (ret_val) {
337 DEBUGOUT("Failed to initialize PHY flow\n");
338 goto out;
339 }
340
341 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
342 * inaccessible and resetting the PHY is not blocked, toggle the
343 * LANPHYPC Value bit to force the interconnect to PCIe mode.
344 */
345 switch (hw->mac.type) {
346 case e1000_pch_lpt:
347 case e1000_pch_spt:
348 case e1000_pch_cnp:
349 if (e1000_phy_is_accessible_pchlan(hw))
350 break;
351
352 /* Before toggling LANPHYPC, see if PHY is accessible by
353 * forcing MAC to SMBus mode first.
354 */
355 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
356 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
357 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
358
359 /* Wait 50 milliseconds for MAC to finish any retries
360 * that it might be trying to perform from previous
361 * attempts to acknowledge any phy read requests.
362 */
363 msec_delay(50);
364
365 /* fall-through */
366 case e1000_pch2lan:
367 if (e1000_phy_is_accessible_pchlan(hw))
368 break;
369
370 /* fall-through */
371 case e1000_pchlan:
372 if ((hw->mac.type == e1000_pchlan) &&
373 (fwsm & E1000_ICH_FWSM_FW_VALID))
374 break;
375
376 if (hw->phy.ops.check_reset_block(hw)) {
377 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
378 ret_val = -E1000_ERR_PHY;
379 break;
380 }
381
382 /* Toggle LANPHYPC Value bit */
383 e1000_toggle_lanphypc_pch_lpt(hw);
384 if (hw->mac.type >= e1000_pch_lpt) {
385 if (e1000_phy_is_accessible_pchlan(hw))
386 break;
387
388 /* Toggling LANPHYPC brings the PHY out of SMBus mode
389 * so ensure that the MAC is also out of SMBus mode
390 */
391 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
392 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
393 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
394
395 if (e1000_phy_is_accessible_pchlan(hw))
396 break;
397
398 ret_val = -E1000_ERR_PHY;
399 }
400 break;
401 default:
402 break;
403 }
404
405 hw->phy.ops.release(hw);
406 if (!ret_val) {
407
408 /* Check to see if able to reset PHY. Print error if not */
409 if (hw->phy.ops.check_reset_block(hw)) {
410 ERROR_REPORT("Reset blocked by ME\n");
411 goto out;
412 }
413
414 /* Reset the PHY before any access to it. Doing so, ensures
415 * that the PHY is in a known good state before we read/write
416 * PHY registers. The generic reset is sufficient here,
417 * because we haven't determined the PHY type yet.
418 */
419 ret_val = e1000_phy_hw_reset_generic(hw);
420 if (ret_val)
421 goto out;
422
423 /* On a successful reset, possibly need to wait for the PHY
424 * to quiesce to an accessible state before returning control
425 * to the calling function. If the PHY does not quiesce, then
426 * return E1000E_BLK_PHY_RESET, as this is the condition that
427 * the PHY is in.
428 */
429 ret_val = hw->phy.ops.check_reset_block(hw);
430 if (ret_val)
431 ERROR_REPORT("ME blocked access to PHY after reset\n");
432 }
433
434 out:
435 /* Ungate automatic PHY configuration on non-managed 82579 */
436 if ((hw->mac.type == e1000_pch2lan) &&
437 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
438 msec_delay(10);
439 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
440 }
441
442 return ret_val;
443 }
444
445 /**
446 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
447 * @hw: pointer to the HW structure
448 *
449 * Initialize family-specific PHY parameters and function pointers.
450 **/
e1000_init_phy_params_pchlan(struct e1000_hw * hw)451 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
452 {
453 struct e1000_phy_info *phy = &hw->phy;
454 s32 ret_val;
455
456 DEBUGFUNC("e1000_init_phy_params_pchlan");
457
458 phy->addr = 1;
459 phy->reset_delay_us = 100;
460
461 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
462 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
463 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
464 phy->ops.set_page = e1000_set_page_igp;
465 phy->ops.read_reg = e1000_read_phy_reg_hv;
466 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
467 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
468 phy->ops.release = e1000_release_swflag_ich8lan;
469 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
470 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
471 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
472 phy->ops.write_reg = e1000_write_phy_reg_hv;
473 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
474 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
475 phy->ops.power_up = e1000_power_up_phy_copper;
476 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
477 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
478
479 phy->id = e1000_phy_unknown;
480
481 ret_val = e1000_init_phy_workarounds_pchlan(hw);
482 if (ret_val)
483 return ret_val;
484
485 if (phy->id == e1000_phy_unknown)
486 switch (hw->mac.type) {
487 default:
488 ret_val = e1000_get_phy_id(hw);
489 if (ret_val)
490 return ret_val;
491 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
492 break;
493 /* fall-through */
494 case e1000_pch2lan:
495 case e1000_pch_lpt:
496 case e1000_pch_spt:
497 case e1000_pch_cnp:
498 /* In case the PHY needs to be in mdio slow mode,
499 * set slow mode and try to get the PHY id again.
500 */
501 ret_val = e1000_set_mdio_slow_mode_hv(hw);
502 if (ret_val)
503 return ret_val;
504 ret_val = e1000_get_phy_id(hw);
505 if (ret_val)
506 return ret_val;
507 break;
508 }
509 phy->type = e1000_get_phy_type_from_id(phy->id);
510
511 switch (phy->type) {
512 case e1000_phy_82577:
513 case e1000_phy_82579:
514 case e1000_phy_i217:
515 phy->ops.check_polarity = e1000_check_polarity_82577;
516 phy->ops.force_speed_duplex =
517 e1000_phy_force_speed_duplex_82577;
518 phy->ops.get_cable_length = e1000_get_cable_length_82577;
519 phy->ops.get_info = e1000_get_phy_info_82577;
520 phy->ops.commit = e1000_phy_sw_reset_generic;
521 break;
522 case e1000_phy_82578:
523 phy->ops.check_polarity = e1000_check_polarity_m88;
524 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
525 phy->ops.get_cable_length = e1000_get_cable_length_m88;
526 phy->ops.get_info = e1000_get_phy_info_m88;
527 break;
528 default:
529 ret_val = -E1000_ERR_PHY;
530 break;
531 }
532
533 return ret_val;
534 }
535
536 /**
537 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
538 * @hw: pointer to the HW structure
539 *
540 * Initialize family-specific PHY parameters and function pointers.
541 **/
e1000_init_phy_params_ich8lan(struct e1000_hw * hw)542 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
543 {
544 struct e1000_phy_info *phy = &hw->phy;
545 s32 ret_val;
546 u16 i = 0;
547
548 DEBUGFUNC("e1000_init_phy_params_ich8lan");
549
550 phy->addr = 1;
551 phy->reset_delay_us = 100;
552
553 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
554 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
555 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
556 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
557 phy->ops.read_reg = e1000_read_phy_reg_igp;
558 phy->ops.release = e1000_release_swflag_ich8lan;
559 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
560 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
561 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
562 phy->ops.write_reg = e1000_write_phy_reg_igp;
563 phy->ops.power_up = e1000_power_up_phy_copper;
564 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
565
566 /* We may need to do this twice - once for IGP and if that fails,
567 * we'll set BM func pointers and try again
568 */
569 ret_val = e1000_determine_phy_address(hw);
570 if (ret_val) {
571 phy->ops.write_reg = e1000_write_phy_reg_bm;
572 phy->ops.read_reg = e1000_read_phy_reg_bm;
573 ret_val = e1000_determine_phy_address(hw);
574 if (ret_val) {
575 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
576 return ret_val;
577 }
578 }
579
580 phy->id = 0;
581 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
582 (i++ < 100)) {
583 msec_delay(1);
584 ret_val = e1000_get_phy_id(hw);
585 if (ret_val)
586 return ret_val;
587 }
588
589 /* Verify phy id */
590 switch (phy->id) {
591 case IGP03E1000_E_PHY_ID:
592 phy->type = e1000_phy_igp_3;
593 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
594 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
595 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
596 phy->ops.get_info = e1000_get_phy_info_igp;
597 phy->ops.check_polarity = e1000_check_polarity_igp;
598 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
599 break;
600 case IFE_E_PHY_ID:
601 case IFE_PLUS_E_PHY_ID:
602 case IFE_C_E_PHY_ID:
603 phy->type = e1000_phy_ife;
604 phy->autoneg_mask = E1000_ALL_NOT_GIG;
605 phy->ops.get_info = e1000_get_phy_info_ife;
606 phy->ops.check_polarity = e1000_check_polarity_ife;
607 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
608 break;
609 case BME1000_E_PHY_ID:
610 phy->type = e1000_phy_bm;
611 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
612 phy->ops.read_reg = e1000_read_phy_reg_bm;
613 phy->ops.write_reg = e1000_write_phy_reg_bm;
614 phy->ops.commit = e1000_phy_sw_reset_generic;
615 phy->ops.get_info = e1000_get_phy_info_m88;
616 phy->ops.check_polarity = e1000_check_polarity_m88;
617 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
618 break;
619 default:
620 return -E1000_ERR_PHY;
621 break;
622 }
623
624 return E1000_SUCCESS;
625 }
626
627 /**
628 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
629 * @hw: pointer to the HW structure
630 *
631 * Initialize family-specific NVM parameters and function
632 * pointers.
633 **/
e1000_init_nvm_params_ich8lan(struct e1000_hw * hw)634 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
635 {
636 struct e1000_nvm_info *nvm = &hw->nvm;
637 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
638 u32 gfpreg, sector_base_addr, sector_end_addr;
639 u16 i;
640 u32 nvm_size;
641
642 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
643
644 nvm->type = e1000_nvm_flash_sw;
645
646 if (hw->mac.type >= e1000_pch_spt) {
647 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
648 * STRAP register. This is because in SPT the GbE Flash region
649 * is no longer accessed through the flash registers. Instead,
650 * the mechanism has changed, and the Flash region access
651 * registers are now implemented in GbE memory space.
652 */
653 nvm->flash_base_addr = 0;
654 nvm_size =
655 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
656 * NVM_SIZE_MULTIPLIER;
657 nvm->flash_bank_size = nvm_size / 2;
658 /* Adjust to word count */
659 nvm->flash_bank_size /= sizeof(u16);
660 /* Set the base address for flash register access */
661 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
662 } else {
663 /* Can't read flash registers if register set isn't mapped. */
664 if (!hw->flash_address) {
665 DEBUGOUT("ERROR: Flash registers not mapped\n");
666 return -E1000_ERR_CONFIG;
667 }
668
669 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
670
671 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
672 * Add 1 to sector_end_addr since this sector is included in
673 * the overall size.
674 */
675 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
676 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
677
678 /* flash_base_addr is byte-aligned */
679 nvm->flash_base_addr = sector_base_addr
680 << FLASH_SECTOR_ADDR_SHIFT;
681
682 /* find total size of the NVM, then cut in half since the total
683 * size represents two separate NVM banks.
684 */
685 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
686 << FLASH_SECTOR_ADDR_SHIFT);
687 nvm->flash_bank_size /= 2;
688 /* Adjust to word count */
689 nvm->flash_bank_size /= sizeof(u16);
690 }
691
692 nvm->word_size = E1000_SHADOW_RAM_WORDS;
693
694 /* Clear shadow ram */
695 for (i = 0; i < nvm->word_size; i++) {
696 dev_spec->shadow_ram[i].modified = FALSE;
697 dev_spec->shadow_ram[i].value = 0xFFFF;
698 }
699
700 /* Function Pointers */
701 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
702 nvm->ops.release = e1000_release_nvm_ich8lan;
703 if (hw->mac.type >= e1000_pch_spt) {
704 nvm->ops.read = e1000_read_nvm_spt;
705 nvm->ops.update = e1000_update_nvm_checksum_spt;
706 } else {
707 nvm->ops.read = e1000_read_nvm_ich8lan;
708 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
709 }
710 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
711 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
712 nvm->ops.write = e1000_write_nvm_ich8lan;
713
714 return E1000_SUCCESS;
715 }
716
717 /**
718 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
719 * @hw: pointer to the HW structure
720 *
721 * Initialize family-specific MAC parameters and function
722 * pointers.
723 **/
e1000_init_mac_params_ich8lan(struct e1000_hw * hw)724 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
725 {
726 struct e1000_mac_info *mac = &hw->mac;
727
728 DEBUGFUNC("e1000_init_mac_params_ich8lan");
729
730 /* Set media type function pointer */
731 hw->phy.media_type = e1000_media_type_copper;
732
733 /* Set mta register count */
734 mac->mta_reg_count = 32;
735 /* Set rar entry count */
736 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
737 if (mac->type == e1000_ich8lan)
738 mac->rar_entry_count--;
739 /* Set if part includes ASF firmware */
740 mac->asf_firmware_present = TRUE;
741 /* FWSM register */
742 mac->has_fwsm = TRUE;
743 /* ARC subsystem not supported */
744 mac->arc_subsystem_valid = FALSE;
745 /* Adaptive IFS supported */
746 mac->adaptive_ifs = TRUE;
747
748 /* Function pointers */
749
750 /* bus type/speed/width */
751 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
752 /* function id */
753 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
754 /* reset */
755 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
756 /* hw initialization */
757 mac->ops.init_hw = e1000_init_hw_ich8lan;
758 /* link setup */
759 mac->ops.setup_link = e1000_setup_link_ich8lan;
760 /* physical interface setup */
761 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
762 /* check for link */
763 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
764 /* link info */
765 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
766 /* multicast address update */
767 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
768 /* clear hardware counters */
769 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
770
771 /* LED and other operations */
772 switch (mac->type) {
773 case e1000_ich8lan:
774 case e1000_ich9lan:
775 case e1000_ich10lan:
776 /* check management mode */
777 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
778 /* ID LED init */
779 mac->ops.id_led_init = e1000_id_led_init_generic;
780 /* blink LED */
781 mac->ops.blink_led = e1000_blink_led_generic;
782 /* setup LED */
783 mac->ops.setup_led = e1000_setup_led_generic;
784 /* cleanup LED */
785 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
786 /* turn on/off LED */
787 mac->ops.led_on = e1000_led_on_ich8lan;
788 mac->ops.led_off = e1000_led_off_ich8lan;
789 break;
790 case e1000_pch2lan:
791 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
792 mac->ops.rar_set = e1000_rar_set_pch2lan;
793 /* fall-through */
794 case e1000_pch_lpt:
795 case e1000_pch_spt:
796 case e1000_pch_cnp:
797 /* multicast address update for pch2 */
798 mac->ops.update_mc_addr_list =
799 e1000_update_mc_addr_list_pch2lan;
800 /* fall-through */
801 case e1000_pchlan:
802 /* check management mode */
803 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
804 /* ID LED init */
805 mac->ops.id_led_init = e1000_id_led_init_pchlan;
806 /* setup LED */
807 mac->ops.setup_led = e1000_setup_led_pchlan;
808 /* cleanup LED */
809 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
810 /* turn on/off LED */
811 mac->ops.led_on = e1000_led_on_pchlan;
812 mac->ops.led_off = e1000_led_off_pchlan;
813 break;
814 default:
815 break;
816 }
817
818 if (mac->type >= e1000_pch_lpt) {
819 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
820 mac->ops.rar_set = e1000_rar_set_pch_lpt;
821 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
822 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
823 }
824
825 /* Enable PCS Lock-loss workaround for ICH8 */
826 if (mac->type == e1000_ich8lan)
827 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
828
829 return E1000_SUCCESS;
830 }
831
832 /**
833 * __e1000_access_emi_reg_locked - Read/write EMI register
834 * @hw: pointer to the HW structure
835 * @addr: EMI address to program
836 * @data: pointer to value to read/write from/to the EMI address
837 * @read: boolean flag to indicate read or write
838 *
839 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
840 **/
__e1000_access_emi_reg_locked(struct e1000_hw * hw,u16 address,u16 * data,bool read)841 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
842 u16 *data, bool read)
843 {
844 s32 ret_val;
845
846 DEBUGFUNC("__e1000_access_emi_reg_locked");
847
848 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
849 if (ret_val)
850 return ret_val;
851
852 if (read)
853 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
854 data);
855 else
856 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
857 *data);
858
859 return ret_val;
860 }
861
862 /**
863 * e1000_read_emi_reg_locked - Read Extended Management Interface register
864 * @hw: pointer to the HW structure
865 * @addr: EMI address to program
866 * @data: value to be read from the EMI address
867 *
868 * Assumes the SW/FW/HW Semaphore is already acquired.
869 **/
e1000_read_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 * data)870 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
871 {
872 DEBUGFUNC("e1000_read_emi_reg_locked");
873
874 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
875 }
876
877 /**
878 * e1000_write_emi_reg_locked - Write Extended Management Interface register
879 * @hw: pointer to the HW structure
880 * @addr: EMI address to program
881 * @data: value to be written to the EMI address
882 *
883 * Assumes the SW/FW/HW Semaphore is already acquired.
884 **/
e1000_write_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 data)885 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
886 {
887 DEBUGFUNC("e1000_read_emi_reg_locked");
888
889 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
890 }
891
892 /**
893 * e1000_set_eee_pchlan - Enable/disable EEE support
894 * @hw: pointer to the HW structure
895 *
896 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
897 * the link and the EEE capabilities of the link partner. The LPI Control
898 * register bits will remain set only if/when link is up.
899 *
900 * EEE LPI must not be asserted earlier than one second after link is up.
901 * On 82579, EEE LPI should not be enabled until such time otherwise there
902 * can be link issues with some switches. Other devices can have EEE LPI
903 * enabled immediately upon link up since they have a timer in hardware which
904 * prevents LPI from being asserted too early.
905 **/
e1000_set_eee_pchlan(struct e1000_hw * hw)906 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
907 {
908 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
909 s32 ret_val;
910 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
911
912 DEBUGFUNC("e1000_set_eee_pchlan");
913
914 switch (hw->phy.type) {
915 case e1000_phy_82579:
916 lpa = I82579_EEE_LP_ABILITY;
917 pcs_status = I82579_EEE_PCS_STATUS;
918 adv_addr = I82579_EEE_ADVERTISEMENT;
919 break;
920 case e1000_phy_i217:
921 lpa = I217_EEE_LP_ABILITY;
922 pcs_status = I217_EEE_PCS_STATUS;
923 adv_addr = I217_EEE_ADVERTISEMENT;
924 break;
925 default:
926 return E1000_SUCCESS;
927 }
928
929 ret_val = hw->phy.ops.acquire(hw);
930 if (ret_val)
931 return ret_val;
932
933 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
934 if (ret_val)
935 goto release;
936
937 /* Clear bits that enable EEE in various speeds */
938 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
939
940 /* Enable EEE if not disabled by user */
941 if (!dev_spec->eee_disable) {
942 /* Save off link partner's EEE ability */
943 ret_val = e1000_read_emi_reg_locked(hw, lpa,
944 &dev_spec->eee_lp_ability);
945 if (ret_val)
946 goto release;
947
948 /* Read EEE advertisement */
949 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
950 if (ret_val)
951 goto release;
952
953 /* Enable EEE only for speeds in which the link partner is
954 * EEE capable and for which we advertise EEE.
955 */
956 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
957 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
958
959 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
960 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
961 if (data & NWAY_LPAR_100TX_FD_CAPS)
962 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
963 else
964 /* EEE is not supported in 100Half, so ignore
965 * partner's EEE in 100 ability if full-duplex
966 * is not advertised.
967 */
968 dev_spec->eee_lp_ability &=
969 ~I82579_EEE_100_SUPPORTED;
970 }
971 }
972
973 if (hw->phy.type == e1000_phy_82579) {
974 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
975 &data);
976 if (ret_val)
977 goto release;
978
979 data &= ~I82579_LPI_100_PLL_SHUT;
980 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
981 data);
982 }
983
984 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
985 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
986 if (ret_val)
987 goto release;
988
989 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
990 release:
991 hw->phy.ops.release(hw);
992
993 return ret_val;
994 }
995
996 /**
997 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
998 * @hw: pointer to the HW structure
999 * @link: link up bool flag
1000 *
1001 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1002 * preventing further DMA write requests. Workaround the issue by disabling
1003 * the de-assertion of the clock request when in 1Gpbs mode.
1004 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1005 * speeds in order to avoid Tx hangs.
1006 **/
e1000_k1_workaround_lpt_lp(struct e1000_hw * hw,bool link)1007 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1008 {
1009 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1010 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1011 s32 ret_val = E1000_SUCCESS;
1012 u16 reg;
1013
1014 if (link && (status & E1000_STATUS_SPEED_1000)) {
1015 ret_val = hw->phy.ops.acquire(hw);
1016 if (ret_val)
1017 return ret_val;
1018
1019 ret_val =
1020 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1021 ®);
1022 if (ret_val)
1023 goto release;
1024
1025 ret_val =
1026 e1000_write_kmrn_reg_locked(hw,
1027 E1000_KMRNCTRLSTA_K1_CONFIG,
1028 reg &
1029 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1030 if (ret_val)
1031 goto release;
1032
1033 usec_delay(10);
1034
1035 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1036 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1037
1038 ret_val =
1039 e1000_write_kmrn_reg_locked(hw,
1040 E1000_KMRNCTRLSTA_K1_CONFIG,
1041 reg);
1042 release:
1043 hw->phy.ops.release(hw);
1044 } else {
1045 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1046 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1047
1048 if ((hw->phy.revision > 5) || !link ||
1049 ((status & E1000_STATUS_SPEED_100) &&
1050 (status & E1000_STATUS_FD)))
1051 goto update_fextnvm6;
1052
1053 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1054 if (ret_val)
1055 return ret_val;
1056
1057 /* Clear link status transmit timeout */
1058 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1059
1060 if (status & E1000_STATUS_SPEED_100) {
1061 /* Set inband Tx timeout to 5x10us for 100Half */
1062 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1063
1064 /* Do not extend the K1 entry latency for 100Half */
1065 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1066 } else {
1067 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1068 reg |= 50 <<
1069 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1070
1071 /* Extend the K1 entry latency for 10 Mbps */
1072 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1073 }
1074
1075 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1076 if (ret_val)
1077 return ret_val;
1078
1079 update_fextnvm6:
1080 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1081 }
1082
1083 return ret_val;
1084 }
1085
e1000_ltr2ns(u16 ltr)1086 static u64 e1000_ltr2ns(u16 ltr)
1087 {
1088 u32 value, scale;
1089
1090 /* Determine the latency in nsec based on the LTR value & scale */
1091 value = ltr & E1000_LTRV_VALUE_MASK;
1092 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1093
1094 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1095 }
1096
1097 /**
1098 * e1000_platform_pm_pch_lpt - Set platform power management values
1099 * @hw: pointer to the HW structure
1100 * @link: bool indicating link status
1101 *
1102 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1103 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1104 * when link is up (which must not exceed the maximum latency supported
1105 * by the platform), otherwise specify there is no LTR requirement.
1106 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1107 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1108 * Capability register set, on this device LTR is set by writing the
1109 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1110 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1111 * message to the PMC.
1112 *
1113 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1114 * high-water mark.
1115 **/
e1000_platform_pm_pch_lpt(struct e1000_hw * hw,bool link)1116 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1117 {
1118 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1119 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1120 u16 lat_enc = 0; /* latency encoded */
1121 s32 obff_hwm = 0;
1122
1123 DEBUGFUNC("e1000_platform_pm_pch_lpt");
1124
1125 if (link) {
1126 u16 speed, duplex, scale = 0;
1127 u16 max_snoop, max_nosnoop;
1128 u16 max_ltr_enc; /* max LTR latency encoded */
1129 s64 lat_ns;
1130 s64 value;
1131 u32 rxa;
1132
1133 if (!hw->mac.max_frame_size) {
1134 DEBUGOUT("max_frame_size not set.\n");
1135 return -E1000_ERR_CONFIG;
1136 }
1137
1138 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1139 if (!speed) {
1140 DEBUGOUT("Speed not set.\n");
1141 return -E1000_ERR_CONFIG;
1142 }
1143
1144 /* Rx Packet Buffer Allocation size (KB) */
1145 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1146
1147 /* Determine the maximum latency tolerated by the device.
1148 *
1149 * Per the PCIe spec, the tolerated latencies are encoded as
1150 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1151 * a 10-bit value (0-1023) to provide a range from 1 ns to
1152 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1153 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1154 */
1155 lat_ns = ((s64)rxa * 1024 -
1156 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1157 if (lat_ns < 0)
1158 lat_ns = 0;
1159 else
1160 lat_ns /= speed;
1161 value = lat_ns;
1162
1163 while (value > E1000_LTRV_VALUE_MASK) {
1164 scale++;
1165 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1166 }
1167 if (scale > E1000_LTRV_SCALE_MAX) {
1168 DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1169 return -E1000_ERR_CONFIG;
1170 }
1171 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1172
1173 /* Determine the maximum latency tolerated by the platform */
1174 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1175 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1176 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1177
1178 if (lat_enc > max_ltr_enc) {
1179 lat_enc = max_ltr_enc;
1180 lat_ns = e1000_ltr2ns(max_ltr_enc);
1181 }
1182
1183 if (lat_ns) {
1184 lat_ns *= speed * 1000;
1185 lat_ns /= 8;
1186 lat_ns /= 1000000000;
1187 obff_hwm = (s32)(rxa - lat_ns);
1188 }
1189 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1190 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1191 return -E1000_ERR_CONFIG;
1192 }
1193 }
1194
1195 /* Set Snoop and No-Snoop latencies the same */
1196 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1197 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1198
1199 /* Set OBFF high water mark */
1200 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1201 reg |= obff_hwm;
1202 E1000_WRITE_REG(hw, E1000_SVT, reg);
1203
1204 /* Enable OBFF */
1205 reg = E1000_READ_REG(hw, E1000_SVCR);
1206 reg |= E1000_SVCR_OFF_EN;
1207 /* Always unblock interrupts to the CPU even when the system is
1208 * in OBFF mode. This ensures that small round-robin traffic
1209 * (like ping) does not get dropped or experience long latency.
1210 */
1211 reg |= E1000_SVCR_OFF_MASKINT;
1212 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1213
1214 return E1000_SUCCESS;
1215 }
1216
1217 /**
1218 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1219 * @hw: pointer to the HW structure
1220 * @itr: interrupt throttling rate
1221 *
1222 * Configure OBFF with the updated interrupt rate.
1223 **/
e1000_set_obff_timer_pch_lpt(struct e1000_hw * hw,u32 itr)1224 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1225 {
1226 u32 svcr;
1227 s32 timer;
1228
1229 DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1230
1231 /* Convert ITR value into microseconds for OBFF timer */
1232 timer = itr & E1000_ITR_MASK;
1233 timer = (timer * E1000_ITR_MULT) / 1000;
1234
1235 if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1236 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1237 return -E1000_ERR_CONFIG;
1238 }
1239
1240 svcr = E1000_READ_REG(hw, E1000_SVCR);
1241 svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1242 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1243 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1244
1245 return E1000_SUCCESS;
1246 }
1247
1248 /**
1249 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1250 * @hw: pointer to the HW structure
1251 * @to_sx: boolean indicating a system power state transition to Sx
1252 *
1253 * When link is down, configure ULP mode to significantly reduce the power
1254 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1255 * ME firmware to start the ULP configuration. If not on an ME enabled
1256 * system, configure the ULP mode by software.
1257 */
e1000_enable_ulp_lpt_lp(struct e1000_hw * hw,bool to_sx)1258 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1259 {
1260 u32 mac_reg;
1261 s32 ret_val = E1000_SUCCESS;
1262 u16 phy_reg;
1263 u16 oem_reg = 0;
1264
1265 if ((hw->mac.type < e1000_pch_lpt) ||
1266 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1267 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1268 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1269 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1270 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1271 return 0;
1272
1273 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1274 /* Request ME configure ULP mode in the PHY */
1275 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1276 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1277 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1278
1279 goto out;
1280 }
1281
1282 if (!to_sx) {
1283 int i = 0;
1284
1285 /* Poll up to 5 seconds for Cable Disconnected indication */
1286 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1287 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1288 /* Bail if link is re-acquired */
1289 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1290 return -E1000_ERR_PHY;
1291
1292 if (i++ == 100)
1293 break;
1294
1295 msec_delay(50);
1296 }
1297 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1298 (E1000_READ_REG(hw, E1000_FEXT) &
1299 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1300 i * 50);
1301 }
1302
1303 ret_val = hw->phy.ops.acquire(hw);
1304 if (ret_val)
1305 goto out;
1306
1307 /* Force SMBus mode in PHY */
1308 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1309 if (ret_val)
1310 goto release;
1311 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1312 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1313
1314 /* Force SMBus mode in MAC */
1315 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1316 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1317 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1318
1319 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1320 * LPLU and disable Gig speed when entering ULP
1321 */
1322 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1324 &oem_reg);
1325 if (ret_val)
1326 goto release;
1327
1328 phy_reg = oem_reg;
1329 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1330
1331 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1332 phy_reg);
1333
1334 if (ret_val)
1335 goto release;
1336 }
1337
1338 /* Set Inband ULP Exit, Reset to SMBus mode and
1339 * Disable SMBus Release on PERST# in PHY
1340 */
1341 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1342 if (ret_val)
1343 goto release;
1344 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1345 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1346 if (to_sx) {
1347 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1348 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1349 else
1350 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1351
1352 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1353 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1354 } else {
1355 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1356 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1357 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1358 }
1359 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1360
1361 /* Set Disable SMBus Release on PERST# in MAC */
1362 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1363 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1364 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1365
1366 /* Commit ULP changes in PHY by starting auto ULP configuration */
1367 phy_reg |= I218_ULP_CONFIG1_START;
1368 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1369
1370 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1371 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1372 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1373 oem_reg);
1374 if (ret_val)
1375 goto release;
1376 }
1377
1378 release:
1379 hw->phy.ops.release(hw);
1380 out:
1381 if (ret_val)
1382 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1383 else
1384 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1385
1386 return ret_val;
1387 }
1388
1389 /**
1390 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1391 * @hw: pointer to the HW structure
1392 * @force: boolean indicating whether or not to force disabling ULP
1393 *
1394 * Un-configure ULP mode when link is up, the system is transitioned from
1395 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1396 * system, poll for an indication from ME that ULP has been un-configured.
1397 * If not on an ME enabled system, un-configure the ULP mode by software.
1398 *
1399 * During nominal operation, this function is called when link is acquired
1400 * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1401 * the driver or during Sx->S0 transitions, this is called with force=TRUE
1402 * to forcibly disable ULP.
1403 */
e1000_disable_ulp_lpt_lp(struct e1000_hw * hw,bool force)1404 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1405 {
1406 s32 ret_val = E1000_SUCCESS;
1407 u32 mac_reg;
1408 u16 phy_reg;
1409 int i = 0;
1410
1411 if ((hw->mac.type < e1000_pch_lpt) ||
1412 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1413 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1414 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1415 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1416 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1417 return 0;
1418
1419 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1420 if (force) {
1421 /* Request ME un-configure ULP mode in the PHY */
1422 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1423 mac_reg &= ~E1000_H2ME_ULP;
1424 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1425 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1426 }
1427
1428 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1429 while (E1000_READ_REG(hw, E1000_FWSM) &
1430 E1000_FWSM_ULP_CFG_DONE) {
1431 if (i++ == 30) {
1432 ret_val = -E1000_ERR_PHY;
1433 goto out;
1434 }
1435
1436 msec_delay(10);
1437 }
1438 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1439
1440 if (force) {
1441 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1442 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1443 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1444 } else {
1445 /* Clear H2ME.ULP after ME ULP configuration */
1446 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1447 mac_reg &= ~E1000_H2ME_ULP;
1448 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1449 }
1450
1451 goto out;
1452 }
1453
1454 ret_val = hw->phy.ops.acquire(hw);
1455 if (ret_val)
1456 goto out;
1457
1458 if (force)
1459 /* Toggle LANPHYPC Value bit */
1460 e1000_toggle_lanphypc_pch_lpt(hw);
1461
1462 /* Unforce SMBus mode in PHY */
1463 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1464 if (ret_val) {
1465 /* The MAC might be in PCIe mode, so temporarily force to
1466 * SMBus mode in order to access the PHY.
1467 */
1468 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1469 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1470 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1471
1472 msec_delay(50);
1473
1474 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1475 &phy_reg);
1476 if (ret_val)
1477 goto release;
1478 }
1479 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1480 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1481
1482 /* Unforce SMBus mode in MAC */
1483 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1484 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1485 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1486
1487 /* When ULP mode was previously entered, K1 was disabled by the
1488 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1489 */
1490 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1491 if (ret_val)
1492 goto release;
1493 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1494 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1495
1496 /* Clear ULP enabled configuration */
1497 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1498 if (ret_val)
1499 goto release;
1500 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1501 I218_ULP_CONFIG1_STICKY_ULP |
1502 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1503 I218_ULP_CONFIG1_WOL_HOST |
1504 I218_ULP_CONFIG1_INBAND_EXIT |
1505 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1506 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1507 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1508 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1509
1510 /* Commit ULP changes by starting auto ULP configuration */
1511 phy_reg |= I218_ULP_CONFIG1_START;
1512 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1513
1514 /* Clear Disable SMBus Release on PERST# in MAC */
1515 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1516 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1517 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1518
1519 release:
1520 hw->phy.ops.release(hw);
1521 if (force) {
1522 hw->phy.ops.reset(hw);
1523 msec_delay(50);
1524 }
1525 out:
1526 if (ret_val)
1527 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1528 else
1529 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1530
1531 return ret_val;
1532 }
1533
1534 /**
1535 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1536 * @hw: pointer to the HW structure
1537 *
1538 * Checks to see of the link status of the hardware has changed. If a
1539 * change in link status has been detected, then we read the PHY registers
1540 * to get the current speed/duplex if link exists.
1541 **/
e1000_check_for_copper_link_ich8lan(struct e1000_hw * hw)1542 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1543 {
1544 struct e1000_mac_info *mac = &hw->mac;
1545 s32 ret_val, tipg_reg = 0;
1546 u16 emi_addr, emi_val = 0;
1547 bool link;
1548 u16 phy_reg;
1549
1550 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1551
1552 /* We only want to go out to the PHY registers to see if Auto-Neg
1553 * has completed and/or if our link status has changed. The
1554 * get_link_status flag is set upon receiving a Link Status
1555 * Change or Rx Sequence Error interrupt.
1556 */
1557 if (!mac->get_link_status)
1558 return E1000_SUCCESS;
1559
1560 /* First we want to see if the MII Status Register reports
1561 * link. If so, then we want to get the current speed/duplex
1562 * of the PHY.
1563 */
1564 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1565 if (ret_val)
1566 return ret_val;
1567
1568 if (hw->mac.type == e1000_pchlan) {
1569 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1570 if (ret_val)
1571 return ret_val;
1572 }
1573
1574 /* When connected at 10Mbps half-duplex, some parts are excessively
1575 * aggressive resulting in many collisions. To avoid this, increase
1576 * the IPG and reduce Rx latency in the PHY.
1577 */
1578 if ((hw->mac.type >= e1000_pch2lan) && link) {
1579 u16 speed, duplex;
1580
1581 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1582 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1583 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1584
1585 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1586 tipg_reg |= 0xFF;
1587 /* Reduce Rx latency in analog PHY */
1588 emi_val = 0;
1589 } else if (hw->mac.type >= e1000_pch_spt &&
1590 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1591 tipg_reg |= 0xC;
1592 emi_val = 1;
1593 } else {
1594 /* Roll back the default values */
1595 tipg_reg |= 0x08;
1596 emi_val = 1;
1597 }
1598
1599 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1600
1601 ret_val = hw->phy.ops.acquire(hw);
1602 if (ret_val)
1603 return ret_val;
1604
1605 if (hw->mac.type == e1000_pch2lan)
1606 emi_addr = I82579_RX_CONFIG;
1607 else
1608 emi_addr = I217_RX_CONFIG;
1609 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1610
1611
1612 if (hw->mac.type >= e1000_pch_lpt) {
1613 u16 phy_reg;
1614
1615 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1616 &phy_reg);
1617 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1618 if (speed == SPEED_100 || speed == SPEED_10)
1619 phy_reg |= 0x3E8;
1620 else
1621 phy_reg |= 0xFA;
1622 hw->phy.ops.write_reg_locked(hw,
1623 I217_PLL_CLOCK_GATE_REG,
1624 phy_reg);
1625
1626 if (speed == SPEED_1000) {
1627 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1628 &phy_reg);
1629
1630 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1631
1632 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1633 phy_reg);
1634 }
1635 }
1636 hw->phy.ops.release(hw);
1637
1638 if (ret_val)
1639 return ret_val;
1640
1641 if (hw->mac.type >= e1000_pch_spt) {
1642 u16 data;
1643 u16 ptr_gap;
1644
1645 if (speed == SPEED_1000) {
1646 ret_val = hw->phy.ops.acquire(hw);
1647 if (ret_val)
1648 return ret_val;
1649
1650 ret_val = hw->phy.ops.read_reg_locked(hw,
1651 PHY_REG(776, 20),
1652 &data);
1653 if (ret_val) {
1654 hw->phy.ops.release(hw);
1655 return ret_val;
1656 }
1657
1658 ptr_gap = (data & (0x3FF << 2)) >> 2;
1659 if (ptr_gap < 0x18) {
1660 data &= ~(0x3FF << 2);
1661 data |= (0x18 << 2);
1662 ret_val =
1663 hw->phy.ops.write_reg_locked(hw,
1664 PHY_REG(776, 20), data);
1665 }
1666 hw->phy.ops.release(hw);
1667 if (ret_val)
1668 return ret_val;
1669 } else {
1670 ret_val = hw->phy.ops.acquire(hw);
1671 if (ret_val)
1672 return ret_val;
1673
1674 ret_val = hw->phy.ops.write_reg_locked(hw,
1675 PHY_REG(776, 20),
1676 0xC023);
1677 hw->phy.ops.release(hw);
1678 if (ret_val)
1679 return ret_val;
1680
1681 }
1682 }
1683 }
1684
1685 /* I217 Packet Loss issue:
1686 * ensure that FEXTNVM4 Beacon Duration is set correctly
1687 * on power up.
1688 * Set the Beacon Duration for I217 to 8 usec
1689 */
1690 if (hw->mac.type >= e1000_pch_lpt) {
1691 u32 mac_reg;
1692
1693 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1694 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1695 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1696 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1697 }
1698
1699 /* Work-around I218 hang issue */
1700 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1701 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1702 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1703 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1704 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1705 if (ret_val)
1706 return ret_val;
1707 }
1708 if (hw->mac.type >= e1000_pch_lpt) {
1709 /* Set platform power management values for
1710 * Latency Tolerance Reporting (LTR)
1711 * Optimized Buffer Flush/Fill (OBFF)
1712 */
1713 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1714 if (ret_val)
1715 return ret_val;
1716 }
1717
1718 /* Clear link partner's EEE ability */
1719 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1720
1721 if (hw->mac.type >= e1000_pch_lpt) {
1722 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1723
1724 if (hw->mac.type == e1000_pch_spt) {
1725 /* FEXTNVM6 K1-off workaround - for SPT only */
1726 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1727
1728 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1729 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1730 else
1731 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1732 }
1733
1734 if (hw->dev_spec.ich8lan.disable_k1_off == TRUE)
1735 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1736
1737 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1738 }
1739
1740 if (!link)
1741 return E1000_SUCCESS; /* No link detected */
1742
1743 mac->get_link_status = FALSE;
1744
1745 switch (hw->mac.type) {
1746 case e1000_pch2lan:
1747 ret_val = e1000_k1_workaround_lv(hw);
1748 if (ret_val)
1749 return ret_val;
1750 /* fall-thru */
1751 case e1000_pchlan:
1752 if (hw->phy.type == e1000_phy_82578) {
1753 ret_val = e1000_link_stall_workaround_hv(hw);
1754 if (ret_val)
1755 return ret_val;
1756 }
1757
1758 /* Workaround for PCHx parts in half-duplex:
1759 * Set the number of preambles removed from the packet
1760 * when it is passed from the PHY to the MAC to prevent
1761 * the MAC from misinterpreting the packet type.
1762 */
1763 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1764 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1765
1766 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1767 E1000_STATUS_FD)
1768 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1769
1770 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1771 break;
1772 default:
1773 break;
1774 }
1775
1776 /* Check if there was DownShift, must be checked
1777 * immediately after link-up
1778 */
1779 e1000_check_downshift_generic(hw);
1780
1781 /* Enable/Disable EEE after link up */
1782 if (hw->phy.type > e1000_phy_82579) {
1783 ret_val = e1000_set_eee_pchlan(hw);
1784 if (ret_val)
1785 return ret_val;
1786 }
1787
1788 /* If we are forcing speed/duplex, then we simply return since
1789 * we have already determined whether we have link or not.
1790 */
1791 if (!mac->autoneg)
1792 return -E1000_ERR_CONFIG;
1793
1794 /* Auto-Neg is enabled. Auto Speed Detection takes care
1795 * of MAC speed/duplex configuration. So we only need to
1796 * configure Collision Distance in the MAC.
1797 */
1798 mac->ops.config_collision_dist(hw);
1799
1800 /* Configure Flow Control now that Auto-Neg has completed.
1801 * First, we need to restore the desired flow control
1802 * settings because we may have had to re-autoneg with a
1803 * different link partner.
1804 */
1805 ret_val = e1000_config_fc_after_link_up_generic(hw);
1806 if (ret_val)
1807 DEBUGOUT("Error configuring flow control\n");
1808
1809 return ret_val;
1810 }
1811
1812 /**
1813 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1814 * @hw: pointer to the HW structure
1815 *
1816 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1817 **/
e1000_init_function_pointers_ich8lan(struct e1000_hw * hw)1818 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1819 {
1820 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1821
1822 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1823 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1824 switch (hw->mac.type) {
1825 case e1000_ich8lan:
1826 case e1000_ich9lan:
1827 case e1000_ich10lan:
1828 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1829 break;
1830 case e1000_pchlan:
1831 case e1000_pch2lan:
1832 case e1000_pch_lpt:
1833 case e1000_pch_spt:
1834 case e1000_pch_cnp:
1835 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1836 break;
1837 default:
1838 break;
1839 }
1840 }
1841
1842 /**
1843 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1844 * @hw: pointer to the HW structure
1845 *
1846 * Acquires the mutex for performing NVM operations.
1847 **/
e1000_acquire_nvm_ich8lan(struct e1000_hw * hw)1848 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1849 {
1850 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1851
1852 ASSERT_CTX_LOCK_HELD(hw);
1853
1854 return E1000_SUCCESS;
1855 }
1856
1857 /**
1858 * e1000_release_nvm_ich8lan - Release NVM mutex
1859 * @hw: pointer to the HW structure
1860 *
1861 * Releases the mutex used while performing NVM operations.
1862 **/
e1000_release_nvm_ich8lan(struct e1000_hw * hw)1863 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1864 {
1865 DEBUGFUNC("e1000_release_nvm_ich8lan");
1866
1867 ASSERT_CTX_LOCK_HELD(hw);
1868 }
1869
1870 /**
1871 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1872 * @hw: pointer to the HW structure
1873 *
1874 * Acquires the software control flag for performing PHY and select
1875 * MAC CSR accesses.
1876 **/
e1000_acquire_swflag_ich8lan(struct e1000_hw * hw)1877 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1878 {
1879 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1880 s32 ret_val = E1000_SUCCESS;
1881
1882 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1883
1884 ASSERT_CTX_LOCK_HELD(hw);
1885
1886 while (timeout) {
1887 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1888 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1889 break;
1890
1891 msec_delay_irq(1);
1892 timeout--;
1893 }
1894
1895 if (!timeout) {
1896 DEBUGOUT("SW has already locked the resource.\n");
1897 ret_val = -E1000_ERR_CONFIG;
1898 goto out;
1899 }
1900
1901 timeout = SW_FLAG_TIMEOUT;
1902
1903 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1904 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1905
1906 while (timeout) {
1907 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1908 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1909 break;
1910
1911 msec_delay_irq(1);
1912 timeout--;
1913 }
1914
1915 if (!timeout) {
1916 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1917 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1918 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1919 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1920 ret_val = -E1000_ERR_CONFIG;
1921 goto out;
1922 }
1923
1924 out:
1925 return ret_val;
1926 }
1927
1928 /**
1929 * e1000_release_swflag_ich8lan - Release software control flag
1930 * @hw: pointer to the HW structure
1931 *
1932 * Releases the software control flag for performing PHY and select
1933 * MAC CSR accesses.
1934 **/
e1000_release_swflag_ich8lan(struct e1000_hw * hw)1935 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1936 {
1937 u32 extcnf_ctrl;
1938
1939 DEBUGFUNC("e1000_release_swflag_ich8lan");
1940
1941 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1942
1943 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1944 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1945 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1946 } else {
1947 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1948 }
1949 }
1950
1951 /**
1952 * e1000_check_mng_mode_ich8lan - Checks management mode
1953 * @hw: pointer to the HW structure
1954 *
1955 * This checks if the adapter has any manageability enabled.
1956 * This is a function pointer entry point only called by read/write
1957 * routines for the PHY and NVM parts.
1958 **/
e1000_check_mng_mode_ich8lan(struct e1000_hw * hw)1959 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1960 {
1961 u32 fwsm;
1962
1963 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1964
1965 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1966
1967 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1968 ((fwsm & E1000_FWSM_MODE_MASK) ==
1969 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1970 }
1971
1972 /**
1973 * e1000_check_mng_mode_pchlan - Checks management mode
1974 * @hw: pointer to the HW structure
1975 *
1976 * This checks if the adapter has iAMT enabled.
1977 * This is a function pointer entry point only called by read/write
1978 * routines for the PHY and NVM parts.
1979 **/
e1000_check_mng_mode_pchlan(struct e1000_hw * hw)1980 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1981 {
1982 u32 fwsm;
1983
1984 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1985
1986 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1987
1988 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1989 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1990 }
1991
1992 /**
1993 * e1000_rar_set_pch2lan - Set receive address register
1994 * @hw: pointer to the HW structure
1995 * @addr: pointer to the receive address
1996 * @index: receive address array register
1997 *
1998 * Sets the receive address array register at index to the address passed
1999 * in by addr. For 82579, RAR[0] is the base address register that is to
2000 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
2001 * Use SHRA[0-3] in place of those reserved for ME.
2002 **/
e1000_rar_set_pch2lan(struct e1000_hw * hw,u8 * addr,u32 index)2003 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2004 {
2005 u32 rar_low, rar_high;
2006
2007 DEBUGFUNC("e1000_rar_set_pch2lan");
2008
2009 /* HW expects these in little endian so we reverse the byte order
2010 * from network order (big endian) to little endian
2011 */
2012 rar_low = ((u32) addr[0] |
2013 ((u32) addr[1] << 8) |
2014 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2015
2016 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2017
2018 /* If MAC address zero, no need to set the AV bit */
2019 if (rar_low || rar_high)
2020 rar_high |= E1000_RAH_AV;
2021
2022 if (index == 0) {
2023 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2024 E1000_WRITE_FLUSH(hw);
2025 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2026 E1000_WRITE_FLUSH(hw);
2027 return E1000_SUCCESS;
2028 }
2029
2030 /* RAR[1-6] are owned by manageability. Skip those and program the
2031 * next address into the SHRA register array.
2032 */
2033 if (index < (u32) (hw->mac.rar_entry_count)) {
2034 s32 ret_val;
2035
2036 ret_val = e1000_acquire_swflag_ich8lan(hw);
2037 if (ret_val)
2038 goto out;
2039
2040 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2041 E1000_WRITE_FLUSH(hw);
2042 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2043 E1000_WRITE_FLUSH(hw);
2044
2045 e1000_release_swflag_ich8lan(hw);
2046
2047 /* verify the register updates */
2048 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2049 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2050 return E1000_SUCCESS;
2051
2052 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2053 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2054 }
2055
2056 out:
2057 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2058 return -E1000_ERR_CONFIG;
2059 }
2060
2061 /**
2062 * e1000_rar_set_pch_lpt - Set receive address registers
2063 * @hw: pointer to the HW structure
2064 * @addr: pointer to the receive address
2065 * @index: receive address array register
2066 *
2067 * Sets the receive address register array at index to the address passed
2068 * in by addr. For LPT, RAR[0] is the base address register that is to
2069 * contain the MAC address. SHRA[0-10] are the shared receive address
2070 * registers that are shared between the Host and manageability engine (ME).
2071 **/
e1000_rar_set_pch_lpt(struct e1000_hw * hw,u8 * addr,u32 index)2072 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2073 {
2074 u32 rar_low, rar_high;
2075 u32 wlock_mac;
2076
2077 DEBUGFUNC("e1000_rar_set_pch_lpt");
2078
2079 /* HW expects these in little endian so we reverse the byte order
2080 * from network order (big endian) to little endian
2081 */
2082 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2083 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2084
2085 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2086
2087 /* If MAC address zero, no need to set the AV bit */
2088 if (rar_low || rar_high)
2089 rar_high |= E1000_RAH_AV;
2090
2091 if (index == 0) {
2092 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2093 E1000_WRITE_FLUSH(hw);
2094 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2095 E1000_WRITE_FLUSH(hw);
2096 return E1000_SUCCESS;
2097 }
2098
2099 /* The manageability engine (ME) can lock certain SHRAR registers that
2100 * it is using - those registers are unavailable for use.
2101 */
2102 if (index < hw->mac.rar_entry_count) {
2103 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2104 E1000_FWSM_WLOCK_MAC_MASK;
2105 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2106
2107 /* Check if all SHRAR registers are locked */
2108 if (wlock_mac == 1)
2109 goto out;
2110
2111 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2112 s32 ret_val;
2113
2114 ret_val = e1000_acquire_swflag_ich8lan(hw);
2115
2116 if (ret_val)
2117 goto out;
2118
2119 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2120 rar_low);
2121 E1000_WRITE_FLUSH(hw);
2122 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2123 rar_high);
2124 E1000_WRITE_FLUSH(hw);
2125
2126 e1000_release_swflag_ich8lan(hw);
2127
2128 /* verify the register updates */
2129 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2130 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2131 return E1000_SUCCESS;
2132 }
2133 }
2134
2135 out:
2136 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2137 return -E1000_ERR_CONFIG;
2138 }
2139
2140 /**
2141 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2142 * @hw: pointer to the HW structure
2143 * @mc_addr_list: array of multicast addresses to program
2144 * @mc_addr_count: number of multicast addresses to program
2145 *
2146 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2147 * The caller must have a packed mc_addr_list of multicast addresses.
2148 **/
e1000_update_mc_addr_list_pch2lan(struct e1000_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)2149 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2150 u8 *mc_addr_list,
2151 u32 mc_addr_count)
2152 {
2153 u16 phy_reg = 0;
2154 int i;
2155 s32 ret_val;
2156
2157 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2158
2159 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2160
2161 ret_val = hw->phy.ops.acquire(hw);
2162 if (ret_val)
2163 return;
2164
2165 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2166 if (ret_val)
2167 goto release;
2168
2169 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2170 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2171 (u16)(hw->mac.mta_shadow[i] &
2172 0xFFFF));
2173 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2174 (u16)((hw->mac.mta_shadow[i] >> 16) &
2175 0xFFFF));
2176 }
2177
2178 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2179
2180 release:
2181 hw->phy.ops.release(hw);
2182 }
2183
2184 /**
2185 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2186 * @hw: pointer to the HW structure
2187 *
2188 * Checks if firmware is blocking the reset of the PHY.
2189 * This is a function pointer entry point only called by
2190 * reset routines.
2191 **/
e1000_check_reset_block_ich8lan(struct e1000_hw * hw)2192 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2193 {
2194 u32 fwsm;
2195 bool blocked = FALSE;
2196 int i = 0;
2197
2198 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2199
2200 do {
2201 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2202 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2203 blocked = TRUE;
2204 msec_delay(10);
2205 continue;
2206 }
2207 blocked = FALSE;
2208 } while (blocked && (i++ < 30));
2209 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2210 }
2211
2212 /**
2213 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2214 * @hw: pointer to the HW structure
2215 *
2216 * Assumes semaphore already acquired.
2217 *
2218 **/
e1000_write_smbus_addr(struct e1000_hw * hw)2219 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2220 {
2221 u16 phy_data;
2222 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2223 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2224 E1000_STRAP_SMT_FREQ_SHIFT;
2225 s32 ret_val;
2226
2227 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2228
2229 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2230 if (ret_val)
2231 return ret_val;
2232
2233 phy_data &= ~HV_SMB_ADDR_MASK;
2234 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2235 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2236
2237 if (hw->phy.type == e1000_phy_i217) {
2238 /* Restore SMBus frequency */
2239 if (freq--) {
2240 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2241 phy_data |= (freq & (1 << 0)) <<
2242 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2243 phy_data |= (freq & (1 << 1)) <<
2244 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2245 } else {
2246 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2247 }
2248 }
2249
2250 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2251 }
2252
2253 /**
2254 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2255 * @hw: pointer to the HW structure
2256 *
2257 * SW should configure the LCD from the NVM extended configuration region
2258 * as a workaround for certain parts.
2259 **/
e1000_sw_lcd_config_ich8lan(struct e1000_hw * hw)2260 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2261 {
2262 struct e1000_phy_info *phy = &hw->phy;
2263 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2264 s32 ret_val = E1000_SUCCESS;
2265 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2266
2267 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2268
2269 /* Initialize the PHY from the NVM on ICH platforms. This
2270 * is needed due to an issue where the NVM configuration is
2271 * not properly autoloaded after power transitions.
2272 * Therefore, after each PHY reset, we will load the
2273 * configuration data out of the NVM manually.
2274 */
2275 switch (hw->mac.type) {
2276 case e1000_ich8lan:
2277 if (phy->type != e1000_phy_igp_3)
2278 return ret_val;
2279
2280 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2281 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2282 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2283 break;
2284 }
2285 /* Fall-thru */
2286 case e1000_pchlan:
2287 case e1000_pch2lan:
2288 case e1000_pch_lpt:
2289 case e1000_pch_spt:
2290 case e1000_pch_cnp:
2291 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2292 break;
2293 default:
2294 return ret_val;
2295 }
2296
2297 ret_val = hw->phy.ops.acquire(hw);
2298 if (ret_val)
2299 return ret_val;
2300
2301 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2302 if (!(data & sw_cfg_mask))
2303 goto release;
2304
2305 /* Make sure HW does not configure LCD from PHY
2306 * extended configuration before SW configuration
2307 */
2308 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2309 if ((hw->mac.type < e1000_pch2lan) &&
2310 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2311 goto release;
2312
2313 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2314 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2315 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2316 if (!cnf_size)
2317 goto release;
2318
2319 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2320 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2321
2322 if (((hw->mac.type == e1000_pchlan) &&
2323 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2324 (hw->mac.type > e1000_pchlan)) {
2325 /* HW configures the SMBus address and LEDs when the
2326 * OEM and LCD Write Enable bits are set in the NVM.
2327 * When both NVM bits are cleared, SW will configure
2328 * them instead.
2329 */
2330 ret_val = e1000_write_smbus_addr(hw);
2331 if (ret_val)
2332 goto release;
2333
2334 data = E1000_READ_REG(hw, E1000_LEDCTL);
2335 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2336 (u16)data);
2337 if (ret_val)
2338 goto release;
2339 }
2340
2341 /* Configure LCD from extended configuration region. */
2342
2343 /* cnf_base_addr is in DWORD */
2344 word_addr = (u16)(cnf_base_addr << 1);
2345
2346 for (i = 0; i < cnf_size; i++) {
2347 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2348 ®_data);
2349 if (ret_val)
2350 goto release;
2351
2352 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2353 1, ®_addr);
2354 if (ret_val)
2355 goto release;
2356
2357 /* Save off the PHY page for future writes. */
2358 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2359 phy_page = reg_data;
2360 continue;
2361 }
2362
2363 reg_addr &= PHY_REG_MASK;
2364 reg_addr |= phy_page;
2365
2366 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2367 reg_data);
2368 if (ret_val)
2369 goto release;
2370 }
2371
2372 release:
2373 hw->phy.ops.release(hw);
2374 return ret_val;
2375 }
2376
2377 /**
2378 * e1000_k1_gig_workaround_hv - K1 Si workaround
2379 * @hw: pointer to the HW structure
2380 * @link: link up bool flag
2381 *
2382 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2383 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2384 * If link is down, the function will restore the default K1 setting located
2385 * in the NVM.
2386 **/
e1000_k1_gig_workaround_hv(struct e1000_hw * hw,bool link)2387 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2388 {
2389 s32 ret_val = E1000_SUCCESS;
2390 u16 status_reg = 0;
2391 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2392
2393 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2394
2395 if (hw->mac.type != e1000_pchlan)
2396 return E1000_SUCCESS;
2397
2398 /* Wrap the whole flow with the sw flag */
2399 ret_val = hw->phy.ops.acquire(hw);
2400 if (ret_val)
2401 return ret_val;
2402
2403 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2404 if (link) {
2405 if (hw->phy.type == e1000_phy_82578) {
2406 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2407 &status_reg);
2408 if (ret_val)
2409 goto release;
2410
2411 status_reg &= (BM_CS_STATUS_LINK_UP |
2412 BM_CS_STATUS_RESOLVED |
2413 BM_CS_STATUS_SPEED_MASK);
2414
2415 if (status_reg == (BM_CS_STATUS_LINK_UP |
2416 BM_CS_STATUS_RESOLVED |
2417 BM_CS_STATUS_SPEED_1000))
2418 k1_enable = FALSE;
2419 }
2420
2421 if (hw->phy.type == e1000_phy_82577) {
2422 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2423 &status_reg);
2424 if (ret_val)
2425 goto release;
2426
2427 status_reg &= (HV_M_STATUS_LINK_UP |
2428 HV_M_STATUS_AUTONEG_COMPLETE |
2429 HV_M_STATUS_SPEED_MASK);
2430
2431 if (status_reg == (HV_M_STATUS_LINK_UP |
2432 HV_M_STATUS_AUTONEG_COMPLETE |
2433 HV_M_STATUS_SPEED_1000))
2434 k1_enable = FALSE;
2435 }
2436
2437 /* Link stall fix for link up */
2438 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2439 0x0100);
2440 if (ret_val)
2441 goto release;
2442
2443 } else {
2444 /* Link stall fix for link down */
2445 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2446 0x4100);
2447 if (ret_val)
2448 goto release;
2449 }
2450
2451 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2452
2453 release:
2454 hw->phy.ops.release(hw);
2455
2456 return ret_val;
2457 }
2458
2459 /**
2460 * e1000_configure_k1_ich8lan - Configure K1 power state
2461 * @hw: pointer to the HW structure
2462 * @enable: K1 state to configure
2463 *
2464 * Configure the K1 power state based on the provided parameter.
2465 * Assumes semaphore already acquired.
2466 *
2467 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2468 **/
e1000_configure_k1_ich8lan(struct e1000_hw * hw,bool k1_enable)2469 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2470 {
2471 s32 ret_val;
2472 u32 ctrl_reg = 0;
2473 u32 ctrl_ext = 0;
2474 u32 reg = 0;
2475 u16 kmrn_reg = 0;
2476
2477 DEBUGFUNC("e1000_configure_k1_ich8lan");
2478
2479 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2480 &kmrn_reg);
2481 if (ret_val)
2482 return ret_val;
2483
2484 if (k1_enable)
2485 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2486 else
2487 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2488
2489 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2490 kmrn_reg);
2491 if (ret_val)
2492 return ret_val;
2493
2494 usec_delay(20);
2495 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2496 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2497
2498 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2499 reg |= E1000_CTRL_FRCSPD;
2500 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2501
2502 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2503 E1000_WRITE_FLUSH(hw);
2504 usec_delay(20);
2505 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2506 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2507 E1000_WRITE_FLUSH(hw);
2508 usec_delay(20);
2509
2510 return E1000_SUCCESS;
2511 }
2512
2513 /**
2514 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2515 * @hw: pointer to the HW structure
2516 * @d0_state: boolean if entering d0 or d3 device state
2517 *
2518 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2519 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2520 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2521 **/
e1000_oem_bits_config_ich8lan(struct e1000_hw * hw,bool d0_state)2522 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2523 {
2524 s32 ret_val = 0;
2525 u32 mac_reg;
2526 u16 oem_reg;
2527
2528 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2529
2530 if (hw->mac.type < e1000_pchlan)
2531 return ret_val;
2532
2533 ret_val = hw->phy.ops.acquire(hw);
2534 if (ret_val)
2535 return ret_val;
2536
2537 if (hw->mac.type == e1000_pchlan) {
2538 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2539 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2540 goto release;
2541 }
2542
2543 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2544 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2545 goto release;
2546
2547 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2548
2549 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2550 if (ret_val)
2551 goto release;
2552
2553 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2554
2555 if (d0_state) {
2556 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2557 oem_reg |= HV_OEM_BITS_GBE_DIS;
2558
2559 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2560 oem_reg |= HV_OEM_BITS_LPLU;
2561 } else {
2562 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2563 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2564 oem_reg |= HV_OEM_BITS_GBE_DIS;
2565
2566 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2567 E1000_PHY_CTRL_NOND0A_LPLU))
2568 oem_reg |= HV_OEM_BITS_LPLU;
2569 }
2570
2571 /* Set Restart auto-neg to activate the bits */
2572 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2573 !hw->phy.ops.check_reset_block(hw))
2574 oem_reg |= HV_OEM_BITS_RESTART_AN;
2575
2576 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2577
2578 release:
2579 hw->phy.ops.release(hw);
2580
2581 return ret_val;
2582 }
2583
2584
2585 /**
2586 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2587 * @hw: pointer to the HW structure
2588 **/
e1000_set_mdio_slow_mode_hv(struct e1000_hw * hw)2589 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2590 {
2591 s32 ret_val;
2592 u16 data;
2593
2594 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2595
2596 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2597 if (ret_val)
2598 return ret_val;
2599
2600 data |= HV_KMRN_MDIO_SLOW;
2601
2602 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2603
2604 return ret_val;
2605 }
2606
2607 /**
2608 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2609 * done after every PHY reset.
2610 **/
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw * hw)2611 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2612 {
2613 s32 ret_val = E1000_SUCCESS;
2614 u16 phy_data;
2615
2616 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2617
2618 if (hw->mac.type != e1000_pchlan)
2619 return E1000_SUCCESS;
2620
2621 /* Set MDIO slow mode before any other MDIO access */
2622 if (hw->phy.type == e1000_phy_82577) {
2623 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2624 if (ret_val)
2625 return ret_val;
2626 }
2627
2628 if (((hw->phy.type == e1000_phy_82577) &&
2629 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2630 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2631 /* Disable generation of early preamble */
2632 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2633 if (ret_val)
2634 return ret_val;
2635
2636 /* Preamble tuning for SSC */
2637 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2638 0xA204);
2639 if (ret_val)
2640 return ret_val;
2641 }
2642
2643 if (hw->phy.type == e1000_phy_82578) {
2644 /* Return registers to default by doing a soft reset then
2645 * writing 0x3140 to the control register.
2646 */
2647 if (hw->phy.revision < 2) {
2648 e1000_phy_sw_reset_generic(hw);
2649 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2650 0x3140);
2651 if (ret_val)
2652 return ret_val;
2653 }
2654 }
2655
2656 /* Select page 0 */
2657 ret_val = hw->phy.ops.acquire(hw);
2658 if (ret_val)
2659 return ret_val;
2660
2661 hw->phy.addr = 1;
2662 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2663 hw->phy.ops.release(hw);
2664 if (ret_val)
2665 return ret_val;
2666
2667 /* Configure the K1 Si workaround during phy reset assuming there is
2668 * link so that it disables K1 if link is in 1Gbps.
2669 */
2670 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2671 if (ret_val)
2672 return ret_val;
2673
2674 /* Workaround for link disconnects on a busy hub in half duplex */
2675 ret_val = hw->phy.ops.acquire(hw);
2676 if (ret_val)
2677 return ret_val;
2678 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2679 if (ret_val)
2680 goto release;
2681 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2682 phy_data & 0x00FF);
2683 if (ret_val)
2684 goto release;
2685
2686 /* set MSE higher to enable link to stay up when noise is high */
2687 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2688 release:
2689 hw->phy.ops.release(hw);
2690
2691 return ret_val;
2692 }
2693
2694 /**
2695 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2696 * @hw: pointer to the HW structure
2697 **/
e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw * hw)2698 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2699 {
2700 u32 mac_reg;
2701 u16 i, phy_reg = 0;
2702 s32 ret_val;
2703
2704 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2705
2706 ret_val = hw->phy.ops.acquire(hw);
2707 if (ret_val)
2708 return;
2709 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2710 if (ret_val)
2711 goto release;
2712
2713 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2714 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2715 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2716 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2717 (u16)(mac_reg & 0xFFFF));
2718 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2719 (u16)((mac_reg >> 16) & 0xFFFF));
2720
2721 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2722 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2723 (u16)(mac_reg & 0xFFFF));
2724 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2725 (u16)((mac_reg & E1000_RAH_AV)
2726 >> 16));
2727 }
2728
2729 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2730
2731 release:
2732 hw->phy.ops.release(hw);
2733 }
2734
e1000_calc_rx_da_crc(u8 mac[])2735 static u32 e1000_calc_rx_da_crc(u8 mac[])
2736 {
2737 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2738 u32 i, j, mask, crc;
2739
2740 DEBUGFUNC("e1000_calc_rx_da_crc");
2741
2742 crc = 0xffffffff;
2743 for (i = 0; i < 6; i++) {
2744 crc = crc ^ mac[i];
2745 for (j = 8; j > 0; j--) {
2746 mask = (crc & 1) * (-1);
2747 crc = (crc >> 1) ^ (poly & mask);
2748 }
2749 }
2750 return ~crc;
2751 }
2752
2753 /**
2754 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2755 * with 82579 PHY
2756 * @hw: pointer to the HW structure
2757 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2758 **/
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw * hw,bool enable)2759 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2760 {
2761 s32 ret_val = E1000_SUCCESS;
2762 u16 phy_reg, data;
2763 u32 mac_reg;
2764 u16 i;
2765
2766 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2767
2768 if (hw->mac.type < e1000_pch2lan)
2769 return E1000_SUCCESS;
2770
2771 /* disable Rx path while enabling/disabling workaround */
2772 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2773 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2774 phy_reg | (1 << 14));
2775 if (ret_val)
2776 return ret_val;
2777
2778 if (enable) {
2779 /* Write Rx addresses (rar_entry_count for RAL/H, and
2780 * SHRAL/H) and initial CRC values to the MAC
2781 */
2782 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2783 u8 mac_addr[ETH_ADDR_LEN] = {0};
2784 u32 addr_high, addr_low;
2785
2786 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2787 if (!(addr_high & E1000_RAH_AV))
2788 continue;
2789 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2790 mac_addr[0] = (addr_low & 0xFF);
2791 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2792 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2793 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2794 mac_addr[4] = (addr_high & 0xFF);
2795 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2796
2797 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2798 e1000_calc_rx_da_crc(mac_addr));
2799 }
2800
2801 /* Write Rx addresses to the PHY */
2802 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2803
2804 /* Enable jumbo frame workaround in the MAC */
2805 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2806 mac_reg &= ~(1 << 14);
2807 mac_reg |= (7 << 15);
2808 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2809
2810 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2811 mac_reg |= E1000_RCTL_SECRC;
2812 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2813
2814 ret_val = e1000_read_kmrn_reg_generic(hw,
2815 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2816 &data);
2817 if (ret_val)
2818 return ret_val;
2819 ret_val = e1000_write_kmrn_reg_generic(hw,
2820 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2821 data | (1 << 0));
2822 if (ret_val)
2823 return ret_val;
2824 ret_val = e1000_read_kmrn_reg_generic(hw,
2825 E1000_KMRNCTRLSTA_HD_CTRL,
2826 &data);
2827 if (ret_val)
2828 return ret_val;
2829 data &= ~(0xF << 8);
2830 data |= (0xB << 8);
2831 ret_val = e1000_write_kmrn_reg_generic(hw,
2832 E1000_KMRNCTRLSTA_HD_CTRL,
2833 data);
2834 if (ret_val)
2835 return ret_val;
2836
2837 /* Enable jumbo frame workaround in the PHY */
2838 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2839 data &= ~(0x7F << 5);
2840 data |= (0x37 << 5);
2841 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2842 if (ret_val)
2843 return ret_val;
2844 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2845 data &= ~(1 << 13);
2846 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2847 if (ret_val)
2848 return ret_val;
2849 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2850 data &= ~(0x3FF << 2);
2851 data |= (E1000_TX_PTR_GAP << 2);
2852 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2853 if (ret_val)
2854 return ret_val;
2855 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2856 if (ret_val)
2857 return ret_val;
2858 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2859 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2860 (1 << 10));
2861 if (ret_val)
2862 return ret_val;
2863 } else {
2864 /* Write MAC register values back to h/w defaults */
2865 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2866 mac_reg &= ~(0xF << 14);
2867 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2868
2869 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2870 mac_reg &= ~E1000_RCTL_SECRC;
2871 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2872
2873 ret_val = e1000_read_kmrn_reg_generic(hw,
2874 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2875 &data);
2876 if (ret_val)
2877 return ret_val;
2878 ret_val = e1000_write_kmrn_reg_generic(hw,
2879 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2880 data & ~(1 << 0));
2881 if (ret_val)
2882 return ret_val;
2883 ret_val = e1000_read_kmrn_reg_generic(hw,
2884 E1000_KMRNCTRLSTA_HD_CTRL,
2885 &data);
2886 if (ret_val)
2887 return ret_val;
2888 data &= ~(0xF << 8);
2889 data |= (0xB << 8);
2890 ret_val = e1000_write_kmrn_reg_generic(hw,
2891 E1000_KMRNCTRLSTA_HD_CTRL,
2892 data);
2893 if (ret_val)
2894 return ret_val;
2895
2896 /* Write PHY register values back to h/w defaults */
2897 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2898 data &= ~(0x7F << 5);
2899 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2900 if (ret_val)
2901 return ret_val;
2902 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2903 data |= (1 << 13);
2904 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2905 if (ret_val)
2906 return ret_val;
2907 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2908 data &= ~(0x3FF << 2);
2909 data |= (0x8 << 2);
2910 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2911 if (ret_val)
2912 return ret_val;
2913 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2914 if (ret_val)
2915 return ret_val;
2916 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2917 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2918 ~(1 << 10));
2919 if (ret_val)
2920 return ret_val;
2921 }
2922
2923 /* re-enable Rx path after enabling/disabling workaround */
2924 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2925 ~(1 << 14));
2926 }
2927
2928 /**
2929 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2930 * done after every PHY reset.
2931 **/
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw * hw)2932 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2933 {
2934 s32 ret_val = E1000_SUCCESS;
2935
2936 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2937
2938 if (hw->mac.type != e1000_pch2lan)
2939 return E1000_SUCCESS;
2940
2941 /* Set MDIO slow mode before any other MDIO access */
2942 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2943 if (ret_val)
2944 return ret_val;
2945
2946 ret_val = hw->phy.ops.acquire(hw);
2947 if (ret_val)
2948 return ret_val;
2949 /* set MSE higher to enable link to stay up when noise is high */
2950 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2951 if (ret_val)
2952 goto release;
2953 /* drop link after 5 times MSE threshold was reached */
2954 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2955 release:
2956 hw->phy.ops.release(hw);
2957
2958 return ret_val;
2959 }
2960
2961 /**
2962 * e1000_k1_gig_workaround_lv - K1 Si workaround
2963 * @hw: pointer to the HW structure
2964 *
2965 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2966 * Disable K1 for 1000 and 100 speeds
2967 **/
e1000_k1_workaround_lv(struct e1000_hw * hw)2968 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2969 {
2970 s32 ret_val = E1000_SUCCESS;
2971 u16 status_reg = 0;
2972
2973 DEBUGFUNC("e1000_k1_workaround_lv");
2974
2975 if (hw->mac.type != e1000_pch2lan)
2976 return E1000_SUCCESS;
2977
2978 /* Set K1 beacon duration based on 10Mbs speed */
2979 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2980 if (ret_val)
2981 return ret_val;
2982
2983 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2984 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2985 if (status_reg &
2986 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2987 u16 pm_phy_reg;
2988
2989 /* LV 1G/100 Packet drop issue wa */
2990 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2991 &pm_phy_reg);
2992 if (ret_val)
2993 return ret_val;
2994 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2995 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2996 pm_phy_reg);
2997 if (ret_val)
2998 return ret_val;
2999 } else {
3000 u32 mac_reg;
3001 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3002 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
3003 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
3004 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3005 }
3006 }
3007
3008 return ret_val;
3009 }
3010
3011 /**
3012 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
3013 * @hw: pointer to the HW structure
3014 * @gate: boolean set to TRUE to gate, FALSE to ungate
3015 *
3016 * Gate/ungate the automatic PHY configuration via hardware; perform
3017 * the configuration via software instead.
3018 **/
e1000_gate_hw_phy_config_ich8lan(struct e1000_hw * hw,bool gate)3019 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3020 {
3021 u32 extcnf_ctrl;
3022
3023 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
3024
3025 if (hw->mac.type < e1000_pch2lan)
3026 return;
3027
3028 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3029
3030 if (gate)
3031 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3032 else
3033 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3034
3035 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3036 }
3037
3038 /**
3039 * e1000_lan_init_done_ich8lan - Check for PHY config completion
3040 * @hw: pointer to the HW structure
3041 *
3042 * Check the appropriate indication the MAC has finished configuring the
3043 * PHY after a software reset.
3044 **/
e1000_lan_init_done_ich8lan(struct e1000_hw * hw)3045 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3046 {
3047 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3048
3049 DEBUGFUNC("e1000_lan_init_done_ich8lan");
3050
3051 /* Wait for basic configuration completes before proceeding */
3052 do {
3053 data = E1000_READ_REG(hw, E1000_STATUS);
3054 data &= E1000_STATUS_LAN_INIT_DONE;
3055 usec_delay(100);
3056 } while ((!data) && --loop);
3057
3058 /* If basic configuration is incomplete before the above loop
3059 * count reaches 0, loading the configuration from NVM will
3060 * leave the PHY in a bad state possibly resulting in no link.
3061 */
3062 if (loop == 0)
3063 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3064
3065 /* Clear the Init Done bit for the next init event */
3066 data = E1000_READ_REG(hw, E1000_STATUS);
3067 data &= ~E1000_STATUS_LAN_INIT_DONE;
3068 E1000_WRITE_REG(hw, E1000_STATUS, data);
3069 }
3070
3071 /**
3072 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3073 * @hw: pointer to the HW structure
3074 **/
e1000_post_phy_reset_ich8lan(struct e1000_hw * hw)3075 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3076 {
3077 s32 ret_val = E1000_SUCCESS;
3078 u16 reg;
3079
3080 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3081
3082 if (hw->phy.ops.check_reset_block(hw))
3083 return E1000_SUCCESS;
3084
3085 /* Allow time for h/w to get to quiescent state after reset */
3086 msec_delay(10);
3087
3088 /* Perform any necessary post-reset workarounds */
3089 switch (hw->mac.type) {
3090 case e1000_pchlan:
3091 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3092 if (ret_val)
3093 return ret_val;
3094 break;
3095 case e1000_pch2lan:
3096 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3097 if (ret_val)
3098 return ret_val;
3099 break;
3100 default:
3101 break;
3102 }
3103
3104 /* Clear the host wakeup bit after lcd reset */
3105 if (hw->mac.type >= e1000_pchlan) {
3106 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3107 reg &= ~BM_WUC_HOST_WU_BIT;
3108 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3109 }
3110
3111 /* Configure the LCD with the extended configuration region in NVM */
3112 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3113 if (ret_val)
3114 return ret_val;
3115
3116 /* Configure the LCD with the OEM bits in NVM */
3117 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3118
3119 if (hw->mac.type == e1000_pch2lan) {
3120 /* Ungate automatic PHY configuration on non-managed 82579 */
3121 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3122 E1000_ICH_FWSM_FW_VALID)) {
3123 msec_delay(10);
3124 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
3125 }
3126
3127 /* Set EEE LPI Update Timer to 200usec */
3128 ret_val = hw->phy.ops.acquire(hw);
3129 if (ret_val)
3130 return ret_val;
3131 ret_val = e1000_write_emi_reg_locked(hw,
3132 I82579_LPI_UPDATE_TIMER,
3133 0x1387);
3134 hw->phy.ops.release(hw);
3135 }
3136
3137 return ret_val;
3138 }
3139
3140 /**
3141 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3142 * @hw: pointer to the HW structure
3143 *
3144 * Resets the PHY
3145 * This is a function pointer entry point called by drivers
3146 * or other shared routines.
3147 **/
e1000_phy_hw_reset_ich8lan(struct e1000_hw * hw)3148 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3149 {
3150 s32 ret_val = E1000_SUCCESS;
3151
3152 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3153
3154 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3155 if ((hw->mac.type == e1000_pch2lan) &&
3156 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3157 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3158
3159 ret_val = e1000_phy_hw_reset_generic(hw);
3160 if (ret_val)
3161 return ret_val;
3162
3163 return e1000_post_phy_reset_ich8lan(hw);
3164 }
3165
3166 /**
3167 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3168 * @hw: pointer to the HW structure
3169 * @active: TRUE to enable LPLU, FALSE to disable
3170 *
3171 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3172 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3173 * the phy speed. This function will manually set the LPLU bit and restart
3174 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3175 * since it configures the same bit.
3176 **/
e1000_set_lplu_state_pchlan(struct e1000_hw * hw,bool active)3177 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3178 {
3179 s32 ret_val;
3180 u16 oem_reg;
3181
3182 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3183 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3184 if (ret_val)
3185 return ret_val;
3186
3187 if (active)
3188 oem_reg |= HV_OEM_BITS_LPLU;
3189 else
3190 oem_reg &= ~HV_OEM_BITS_LPLU;
3191
3192 if (!hw->phy.ops.check_reset_block(hw))
3193 oem_reg |= HV_OEM_BITS_RESTART_AN;
3194
3195 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3196 }
3197
3198 /**
3199 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3200 * @hw: pointer to the HW structure
3201 * @active: TRUE to enable LPLU, FALSE to disable
3202 *
3203 * Sets the LPLU D0 state according to the active flag. When
3204 * activating LPLU this function also disables smart speed
3205 * and vice versa. LPLU will not be activated unless the
3206 * device autonegotiation advertisement meets standards of
3207 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3208 * This is a function pointer entry point only called by
3209 * PHY setup routines.
3210 **/
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3211 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3212 {
3213 struct e1000_phy_info *phy = &hw->phy;
3214 u32 phy_ctrl;
3215 s32 ret_val = E1000_SUCCESS;
3216 u16 data;
3217
3218 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3219
3220 if (phy->type == e1000_phy_ife)
3221 return E1000_SUCCESS;
3222
3223 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3224
3225 if (active) {
3226 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3227 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3228
3229 if (phy->type != e1000_phy_igp_3)
3230 return E1000_SUCCESS;
3231
3232 /* Call gig speed drop workaround on LPLU before accessing
3233 * any PHY registers
3234 */
3235 if (hw->mac.type == e1000_ich8lan)
3236 e1000_gig_downshift_workaround_ich8lan(hw);
3237
3238 /* When LPLU is enabled, we should disable SmartSpeed */
3239 ret_val = phy->ops.read_reg(hw,
3240 IGP01E1000_PHY_PORT_CONFIG,
3241 &data);
3242 if (ret_val)
3243 return ret_val;
3244 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3245 ret_val = phy->ops.write_reg(hw,
3246 IGP01E1000_PHY_PORT_CONFIG,
3247 data);
3248 if (ret_val)
3249 return ret_val;
3250 } else {
3251 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3252 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3253
3254 if (phy->type != e1000_phy_igp_3)
3255 return E1000_SUCCESS;
3256
3257 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3258 * during Dx states where the power conservation is most
3259 * important. During driver activity we should enable
3260 * SmartSpeed, so performance is maintained.
3261 */
3262 if (phy->smart_speed == e1000_smart_speed_on) {
3263 ret_val = phy->ops.read_reg(hw,
3264 IGP01E1000_PHY_PORT_CONFIG,
3265 &data);
3266 if (ret_val)
3267 return ret_val;
3268
3269 data |= IGP01E1000_PSCFR_SMART_SPEED;
3270 ret_val = phy->ops.write_reg(hw,
3271 IGP01E1000_PHY_PORT_CONFIG,
3272 data);
3273 if (ret_val)
3274 return ret_val;
3275 } else if (phy->smart_speed == e1000_smart_speed_off) {
3276 ret_val = phy->ops.read_reg(hw,
3277 IGP01E1000_PHY_PORT_CONFIG,
3278 &data);
3279 if (ret_val)
3280 return ret_val;
3281
3282 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3283 ret_val = phy->ops.write_reg(hw,
3284 IGP01E1000_PHY_PORT_CONFIG,
3285 data);
3286 if (ret_val)
3287 return ret_val;
3288 }
3289 }
3290
3291 return E1000_SUCCESS;
3292 }
3293
3294 /**
3295 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3296 * @hw: pointer to the HW structure
3297 * @active: TRUE to enable LPLU, FALSE to disable
3298 *
3299 * Sets the LPLU D3 state according to the active flag. When
3300 * activating LPLU this function also disables smart speed
3301 * and vice versa. LPLU will not be activated unless the
3302 * device autonegotiation advertisement meets standards of
3303 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3304 * This is a function pointer entry point only called by
3305 * PHY setup routines.
3306 **/
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3307 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3308 {
3309 struct e1000_phy_info *phy = &hw->phy;
3310 u32 phy_ctrl;
3311 s32 ret_val = E1000_SUCCESS;
3312 u16 data;
3313
3314 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3315
3316 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3317
3318 if (!active) {
3319 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3320 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3321
3322 if (phy->type != e1000_phy_igp_3)
3323 return E1000_SUCCESS;
3324
3325 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3326 * during Dx states where the power conservation is most
3327 * important. During driver activity we should enable
3328 * SmartSpeed, so performance is maintained.
3329 */
3330 if (phy->smart_speed == e1000_smart_speed_on) {
3331 ret_val = phy->ops.read_reg(hw,
3332 IGP01E1000_PHY_PORT_CONFIG,
3333 &data);
3334 if (ret_val)
3335 return ret_val;
3336
3337 data |= IGP01E1000_PSCFR_SMART_SPEED;
3338 ret_val = phy->ops.write_reg(hw,
3339 IGP01E1000_PHY_PORT_CONFIG,
3340 data);
3341 if (ret_val)
3342 return ret_val;
3343 } else if (phy->smart_speed == e1000_smart_speed_off) {
3344 ret_val = phy->ops.read_reg(hw,
3345 IGP01E1000_PHY_PORT_CONFIG,
3346 &data);
3347 if (ret_val)
3348 return ret_val;
3349
3350 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3351 ret_val = phy->ops.write_reg(hw,
3352 IGP01E1000_PHY_PORT_CONFIG,
3353 data);
3354 if (ret_val)
3355 return ret_val;
3356 }
3357 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3358 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3359 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3360 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3361 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3362
3363 if (phy->type != e1000_phy_igp_3)
3364 return E1000_SUCCESS;
3365
3366 /* Call gig speed drop workaround on LPLU before accessing
3367 * any PHY registers
3368 */
3369 if (hw->mac.type == e1000_ich8lan)
3370 e1000_gig_downshift_workaround_ich8lan(hw);
3371
3372 /* When LPLU is enabled, we should disable SmartSpeed */
3373 ret_val = phy->ops.read_reg(hw,
3374 IGP01E1000_PHY_PORT_CONFIG,
3375 &data);
3376 if (ret_val)
3377 return ret_val;
3378
3379 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3380 ret_val = phy->ops.write_reg(hw,
3381 IGP01E1000_PHY_PORT_CONFIG,
3382 data);
3383 }
3384
3385 return ret_val;
3386 }
3387
3388 /**
3389 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3390 * @hw: pointer to the HW structure
3391 * @bank: pointer to the variable that returns the active bank
3392 *
3393 * Reads signature byte from the NVM using the flash access registers.
3394 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3395 **/
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw * hw,u32 * bank)3396 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3397 {
3398 u32 eecd;
3399 struct e1000_nvm_info *nvm = &hw->nvm;
3400 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3401 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3402 u32 nvm_dword = 0;
3403 u8 sig_byte = 0;
3404 s32 ret_val;
3405
3406 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3407
3408 switch (hw->mac.type) {
3409 case e1000_pch_spt:
3410 case e1000_pch_cnp:
3411 bank1_offset = nvm->flash_bank_size;
3412 act_offset = E1000_ICH_NVM_SIG_WORD;
3413
3414 /* set bank to 0 in case flash read fails */
3415 *bank = 0;
3416
3417 /* Check bank 0 */
3418 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3419 &nvm_dword);
3420 if (ret_val)
3421 return ret_val;
3422 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3423 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3424 E1000_ICH_NVM_SIG_VALUE) {
3425 *bank = 0;
3426 return E1000_SUCCESS;
3427 }
3428
3429 /* Check bank 1 */
3430 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3431 bank1_offset,
3432 &nvm_dword);
3433 if (ret_val)
3434 return ret_val;
3435 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3436 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3437 E1000_ICH_NVM_SIG_VALUE) {
3438 *bank = 1;
3439 return E1000_SUCCESS;
3440 }
3441
3442 DEBUGOUT("ERROR: No valid NVM bank present\n");
3443 return -E1000_ERR_NVM;
3444 case e1000_ich8lan:
3445 case e1000_ich9lan:
3446 eecd = E1000_READ_REG(hw, E1000_EECD);
3447 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3448 E1000_EECD_SEC1VAL_VALID_MASK) {
3449 if (eecd & E1000_EECD_SEC1VAL)
3450 *bank = 1;
3451 else
3452 *bank = 0;
3453
3454 return E1000_SUCCESS;
3455 }
3456 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3457 /* fall-thru */
3458 default:
3459 /* set bank to 0 in case flash read fails */
3460 *bank = 0;
3461
3462 /* Check bank 0 */
3463 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3464 &sig_byte);
3465 if (ret_val)
3466 return ret_val;
3467 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3468 E1000_ICH_NVM_SIG_VALUE) {
3469 *bank = 0;
3470 return E1000_SUCCESS;
3471 }
3472
3473 /* Check bank 1 */
3474 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3475 bank1_offset,
3476 &sig_byte);
3477 if (ret_val)
3478 return ret_val;
3479 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3480 E1000_ICH_NVM_SIG_VALUE) {
3481 *bank = 1;
3482 return E1000_SUCCESS;
3483 }
3484
3485 DEBUGOUT("ERROR: No valid NVM bank present\n");
3486 return -E1000_ERR_NVM;
3487 }
3488 }
3489
3490 /**
3491 * e1000_read_nvm_spt - NVM access for SPT
3492 * @hw: pointer to the HW structure
3493 * @offset: The offset (in bytes) of the word(s) to read.
3494 * @words: Size of data to read in words.
3495 * @data: pointer to the word(s) to read at offset.
3496 *
3497 * Reads a word(s) from the NVM
3498 **/
e1000_read_nvm_spt(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3499 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3500 u16 *data)
3501 {
3502 struct e1000_nvm_info *nvm = &hw->nvm;
3503 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3504 u32 act_offset;
3505 s32 ret_val = E1000_SUCCESS;
3506 u32 bank = 0;
3507 u32 dword = 0;
3508 u16 offset_to_read;
3509 u16 i;
3510
3511 DEBUGFUNC("e1000_read_nvm_spt");
3512
3513 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3514 (words == 0)) {
3515 DEBUGOUT("nvm parameter(s) out of bounds\n");
3516 ret_val = -E1000_ERR_NVM;
3517 goto out;
3518 }
3519
3520 nvm->ops.acquire(hw);
3521
3522 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3523 if (ret_val != E1000_SUCCESS) {
3524 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3525 bank = 0;
3526 }
3527
3528 act_offset = (bank) ? nvm->flash_bank_size : 0;
3529 act_offset += offset;
3530
3531 ret_val = E1000_SUCCESS;
3532
3533 for (i = 0; i < words; i += 2) {
3534 if (words - i == 1) {
3535 if (dev_spec->shadow_ram[offset+i].modified) {
3536 data[i] = dev_spec->shadow_ram[offset+i].value;
3537 } else {
3538 offset_to_read = act_offset + i -
3539 ((act_offset + i) % 2);
3540 ret_val =
3541 e1000_read_flash_dword_ich8lan(hw,
3542 offset_to_read,
3543 &dword);
3544 if (ret_val)
3545 break;
3546 if ((act_offset + i) % 2 == 0)
3547 data[i] = (u16)(dword & 0xFFFF);
3548 else
3549 data[i] = (u16)((dword >> 16) & 0xFFFF);
3550 }
3551 } else {
3552 offset_to_read = act_offset + i;
3553 if (!(dev_spec->shadow_ram[offset+i].modified) ||
3554 !(dev_spec->shadow_ram[offset+i+1].modified)) {
3555 ret_val =
3556 e1000_read_flash_dword_ich8lan(hw,
3557 offset_to_read,
3558 &dword);
3559 if (ret_val)
3560 break;
3561 }
3562 if (dev_spec->shadow_ram[offset+i].modified)
3563 data[i] = dev_spec->shadow_ram[offset+i].value;
3564 else
3565 data[i] = (u16) (dword & 0xFFFF);
3566 if (dev_spec->shadow_ram[offset+i].modified)
3567 data[i+1] =
3568 dev_spec->shadow_ram[offset+i+1].value;
3569 else
3570 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3571 }
3572 }
3573
3574 nvm->ops.release(hw);
3575
3576 out:
3577 if (ret_val)
3578 DEBUGOUT1("NVM read error: %d\n", ret_val);
3579
3580 return ret_val;
3581 }
3582
3583 /**
3584 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3585 * @hw: pointer to the HW structure
3586 * @offset: The offset (in bytes) of the word(s) to read.
3587 * @words: Size of data to read in words
3588 * @data: Pointer to the word(s) to read at offset.
3589 *
3590 * Reads a word(s) from the NVM using the flash access registers.
3591 **/
e1000_read_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3592 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3593 u16 *data)
3594 {
3595 struct e1000_nvm_info *nvm = &hw->nvm;
3596 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3597 u32 act_offset;
3598 s32 ret_val = E1000_SUCCESS;
3599 u32 bank = 0;
3600 u16 i, word;
3601
3602 DEBUGFUNC("e1000_read_nvm_ich8lan");
3603
3604 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3605 (words == 0)) {
3606 DEBUGOUT("nvm parameter(s) out of bounds\n");
3607 ret_val = -E1000_ERR_NVM;
3608 goto out;
3609 }
3610
3611 nvm->ops.acquire(hw);
3612
3613 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3614 if (ret_val != E1000_SUCCESS) {
3615 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3616 bank = 0;
3617 }
3618
3619 act_offset = (bank) ? nvm->flash_bank_size : 0;
3620 act_offset += offset;
3621
3622 ret_val = E1000_SUCCESS;
3623 for (i = 0; i < words; i++) {
3624 if (dev_spec->shadow_ram[offset+i].modified) {
3625 data[i] = dev_spec->shadow_ram[offset+i].value;
3626 } else {
3627 ret_val = e1000_read_flash_word_ich8lan(hw,
3628 act_offset + i,
3629 &word);
3630 if (ret_val)
3631 break;
3632 data[i] = word;
3633 }
3634 }
3635
3636 nvm->ops.release(hw);
3637
3638 out:
3639 if (ret_val)
3640 DEBUGOUT1("NVM read error: %d\n", ret_val);
3641
3642 return ret_val;
3643 }
3644
3645 /**
3646 * e1000_flash_cycle_init_ich8lan - Initialize flash
3647 * @hw: pointer to the HW structure
3648 *
3649 * This function does initial flash setup so that a new read/write/erase cycle
3650 * can be started.
3651 **/
e1000_flash_cycle_init_ich8lan(struct e1000_hw * hw)3652 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3653 {
3654 union ich8_hws_flash_status hsfsts;
3655 s32 ret_val = -E1000_ERR_NVM;
3656
3657 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3658
3659 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3660
3661 /* Check if the flash descriptor is valid */
3662 if (!hsfsts.hsf_status.fldesvalid) {
3663 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3664 return -E1000_ERR_NVM;
3665 }
3666
3667 /* Clear FCERR and DAEL in hw status by writing 1 */
3668 hsfsts.hsf_status.flcerr = 1;
3669 hsfsts.hsf_status.dael = 1;
3670 if (hw->mac.type >= e1000_pch_spt)
3671 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3672 hsfsts.regval & 0xFFFF);
3673 else
3674 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3675
3676 /* Either we should have a hardware SPI cycle in progress
3677 * bit to check against, in order to start a new cycle or
3678 * FDONE bit should be changed in the hardware so that it
3679 * is 1 after hardware reset, which can then be used as an
3680 * indication whether a cycle is in progress or has been
3681 * completed.
3682 */
3683
3684 if (!hsfsts.hsf_status.flcinprog) {
3685 /* There is no cycle running at present,
3686 * so we can start a cycle.
3687 * Begin by setting Flash Cycle Done.
3688 */
3689 hsfsts.hsf_status.flcdone = 1;
3690 if (hw->mac.type >= e1000_pch_spt)
3691 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3692 hsfsts.regval & 0xFFFF);
3693 else
3694 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3695 hsfsts.regval);
3696 ret_val = E1000_SUCCESS;
3697 } else {
3698 s32 i;
3699
3700 /* Otherwise poll for sometime so the current
3701 * cycle has a chance to end before giving up.
3702 */
3703 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3704 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3705 ICH_FLASH_HSFSTS);
3706 if (!hsfsts.hsf_status.flcinprog) {
3707 ret_val = E1000_SUCCESS;
3708 break;
3709 }
3710 usec_delay(1);
3711 }
3712 if (ret_val == E1000_SUCCESS) {
3713 /* Successful in waiting for previous cycle to timeout,
3714 * now set the Flash Cycle Done.
3715 */
3716 hsfsts.hsf_status.flcdone = 1;
3717 if (hw->mac.type >= e1000_pch_spt)
3718 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3719 hsfsts.regval & 0xFFFF);
3720 else
3721 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3722 hsfsts.regval);
3723 } else {
3724 DEBUGOUT("Flash controller busy, cannot get access\n");
3725 }
3726 }
3727
3728 return ret_val;
3729 }
3730
3731 /**
3732 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3733 * @hw: pointer to the HW structure
3734 * @timeout: maximum time to wait for completion
3735 *
3736 * This function starts a flash cycle and waits for its completion.
3737 **/
e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout)3738 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3739 {
3740 union ich8_hws_flash_ctrl hsflctl;
3741 union ich8_hws_flash_status hsfsts;
3742 u32 i = 0;
3743
3744 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3745
3746 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3747 if (hw->mac.type >= e1000_pch_spt)
3748 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3749 else
3750 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3751 hsflctl.hsf_ctrl.flcgo = 1;
3752
3753 if (hw->mac.type >= e1000_pch_spt)
3754 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3755 hsflctl.regval << 16);
3756 else
3757 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3758
3759 /* wait till FDONE bit is set to 1 */
3760 do {
3761 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3762 if (hsfsts.hsf_status.flcdone)
3763 break;
3764 usec_delay(1);
3765 } while (i++ < timeout);
3766
3767 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3768 return E1000_SUCCESS;
3769
3770 return -E1000_ERR_NVM;
3771 }
3772
3773 /**
3774 * e1000_read_flash_dword_ich8lan - Read dword from flash
3775 * @hw: pointer to the HW structure
3776 * @offset: offset to data location
3777 * @data: pointer to the location for storing the data
3778 *
3779 * Reads the flash dword at offset into data. Offset is converted
3780 * to bytes before read.
3781 **/
e1000_read_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3782 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3783 u32 *data)
3784 {
3785 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3786
3787 if (!data)
3788 return -E1000_ERR_NVM;
3789
3790 /* Must convert word offset into bytes. */
3791 offset <<= 1;
3792
3793 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3794 }
3795
3796 /**
3797 * e1000_read_flash_word_ich8lan - Read word from flash
3798 * @hw: pointer to the HW structure
3799 * @offset: offset to data location
3800 * @data: pointer to the location for storing the data
3801 *
3802 * Reads the flash word at offset into data. Offset is converted
3803 * to bytes before read.
3804 **/
e1000_read_flash_word_ich8lan(struct e1000_hw * hw,u32 offset,u16 * data)3805 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3806 u16 *data)
3807 {
3808 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3809
3810 if (!data)
3811 return -E1000_ERR_NVM;
3812
3813 /* Must convert offset into bytes. */
3814 offset <<= 1;
3815
3816 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3817 }
3818
3819 /**
3820 * e1000_read_flash_byte_ich8lan - Read byte from flash
3821 * @hw: pointer to the HW structure
3822 * @offset: The offset of the byte to read.
3823 * @data: Pointer to a byte to store the value read.
3824 *
3825 * Reads a single byte from the NVM using the flash access registers.
3826 **/
e1000_read_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 * data)3827 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3828 u8 *data)
3829 {
3830 s32 ret_val;
3831 u16 word = 0;
3832
3833 /* In SPT, only 32 bits access is supported,
3834 * so this function should not be called.
3835 */
3836 if (hw->mac.type >= e1000_pch_spt)
3837 return -E1000_ERR_NVM;
3838 else
3839 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3840
3841 if (ret_val)
3842 return ret_val;
3843
3844 *data = (u8)word;
3845
3846 return E1000_SUCCESS;
3847 }
3848
3849 /**
3850 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3851 * @hw: pointer to the HW structure
3852 * @offset: The offset (in bytes) of the byte or word to read.
3853 * @size: Size of data to read, 1=byte 2=word
3854 * @data: Pointer to the word to store the value read.
3855 *
3856 * Reads a byte or word from the NVM using the flash access registers.
3857 **/
e1000_read_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 * data)3858 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3859 u8 size, u16 *data)
3860 {
3861 union ich8_hws_flash_status hsfsts;
3862 union ich8_hws_flash_ctrl hsflctl;
3863 u32 flash_linear_addr;
3864 u32 flash_data = 0;
3865 s32 ret_val = -E1000_ERR_NVM;
3866 u8 count = 0;
3867
3868 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3869
3870 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3871 return -E1000_ERR_NVM;
3872 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3873 hw->nvm.flash_base_addr);
3874
3875 do {
3876 usec_delay(1);
3877 /* Steps */
3878 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3879 if (ret_val != E1000_SUCCESS)
3880 break;
3881 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3882
3883 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3884 hsflctl.hsf_ctrl.fldbcount = size - 1;
3885 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3886 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3887 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3888
3889 ret_val = e1000_flash_cycle_ich8lan(hw,
3890 ICH_FLASH_READ_COMMAND_TIMEOUT);
3891
3892 /* Check if FCERR is set to 1, if set to 1, clear it
3893 * and try the whole sequence a few more times, else
3894 * read in (shift in) the Flash Data0, the order is
3895 * least significant byte first msb to lsb
3896 */
3897 if (ret_val == E1000_SUCCESS) {
3898 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3899 if (size == 1)
3900 *data = (u8)(flash_data & 0x000000FF);
3901 else if (size == 2)
3902 *data = (u16)(flash_data & 0x0000FFFF);
3903 break;
3904 } else {
3905 /* If we've gotten here, then things are probably
3906 * completely hosed, but if the error condition is
3907 * detected, it won't hurt to give it another try...
3908 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3909 */
3910 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3911 ICH_FLASH_HSFSTS);
3912 if (hsfsts.hsf_status.flcerr) {
3913 /* Repeat for some time before giving up. */
3914 continue;
3915 } else if (!hsfsts.hsf_status.flcdone) {
3916 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3917 break;
3918 }
3919 }
3920 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3921
3922 return ret_val;
3923 }
3924
3925 /**
3926 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3927 * @hw: pointer to the HW structure
3928 * @offset: The offset (in bytes) of the dword to read.
3929 * @data: Pointer to the dword to store the value read.
3930 *
3931 * Reads a byte or word from the NVM using the flash access registers.
3932 **/
e1000_read_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3933 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3934 u32 *data)
3935 {
3936 union ich8_hws_flash_status hsfsts;
3937 union ich8_hws_flash_ctrl hsflctl;
3938 u32 flash_linear_addr;
3939 s32 ret_val = -E1000_ERR_NVM;
3940 u8 count = 0;
3941
3942 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3943
3944 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3945 hw->mac.type < e1000_pch_spt)
3946 return -E1000_ERR_NVM;
3947 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3948 hw->nvm.flash_base_addr);
3949
3950 do {
3951 usec_delay(1);
3952 /* Steps */
3953 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3954 if (ret_val != E1000_SUCCESS)
3955 break;
3956 /* In SPT, This register is in Lan memory space, not flash.
3957 * Therefore, only 32 bit access is supported
3958 */
3959 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3960
3961 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3962 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3963 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3964 /* In SPT, This register is in Lan memory space, not flash.
3965 * Therefore, only 32 bit access is supported
3966 */
3967 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3968 (u32)hsflctl.regval << 16);
3969 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3970
3971 ret_val = e1000_flash_cycle_ich8lan(hw,
3972 ICH_FLASH_READ_COMMAND_TIMEOUT);
3973
3974 /* Check if FCERR is set to 1, if set to 1, clear it
3975 * and try the whole sequence a few more times, else
3976 * read in (shift in) the Flash Data0, the order is
3977 * least significant byte first msb to lsb
3978 */
3979 if (ret_val == E1000_SUCCESS) {
3980 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3981 break;
3982 } else {
3983 /* If we've gotten here, then things are probably
3984 * completely hosed, but if the error condition is
3985 * detected, it won't hurt to give it another try...
3986 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3987 */
3988 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3989 ICH_FLASH_HSFSTS);
3990 if (hsfsts.hsf_status.flcerr) {
3991 /* Repeat for some time before giving up. */
3992 continue;
3993 } else if (!hsfsts.hsf_status.flcdone) {
3994 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3995 break;
3996 }
3997 }
3998 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3999
4000 return ret_val;
4001 }
4002
4003 /**
4004 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
4005 * @hw: pointer to the HW structure
4006 * @offset: The offset (in bytes) of the word(s) to write.
4007 * @words: Size of data to write in words
4008 * @data: Pointer to the word(s) to write at offset.
4009 *
4010 * Writes a byte or word to the NVM using the flash access registers.
4011 **/
e1000_write_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)4012 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4013 u16 *data)
4014 {
4015 struct e1000_nvm_info *nvm = &hw->nvm;
4016 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4017 u16 i;
4018
4019 DEBUGFUNC("e1000_write_nvm_ich8lan");
4020
4021 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4022 (words == 0)) {
4023 DEBUGOUT("nvm parameter(s) out of bounds\n");
4024 return -E1000_ERR_NVM;
4025 }
4026
4027 nvm->ops.acquire(hw);
4028
4029 for (i = 0; i < words; i++) {
4030 dev_spec->shadow_ram[offset+i].modified = TRUE;
4031 dev_spec->shadow_ram[offset+i].value = data[i];
4032 }
4033
4034 nvm->ops.release(hw);
4035
4036 return E1000_SUCCESS;
4037 }
4038
4039 /**
4040 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
4041 * @hw: pointer to the HW structure
4042 *
4043 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4044 * which writes the checksum to the shadow ram. The changes in the shadow
4045 * ram are then committed to the EEPROM by processing each bank at a time
4046 * checking for the modified bit and writing only the pending changes.
4047 * After a successful commit, the shadow ram is cleared and is ready for
4048 * future writes.
4049 **/
e1000_update_nvm_checksum_spt(struct e1000_hw * hw)4050 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4051 {
4052 struct e1000_nvm_info *nvm = &hw->nvm;
4053 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4054 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4055 s32 ret_val;
4056 u32 dword = 0;
4057
4058 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4059
4060 ret_val = e1000_update_nvm_checksum_generic(hw);
4061 if (ret_val)
4062 goto out;
4063
4064 if (nvm->type != e1000_nvm_flash_sw)
4065 goto out;
4066
4067 nvm->ops.acquire(hw);
4068
4069 /* We're writing to the opposite bank so if we're on bank 1,
4070 * write to bank 0 etc. We also need to erase the segment that
4071 * is going to be written
4072 */
4073 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4074 if (ret_val != E1000_SUCCESS) {
4075 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4076 bank = 0;
4077 }
4078
4079 if (bank == 0) {
4080 new_bank_offset = nvm->flash_bank_size;
4081 old_bank_offset = 0;
4082 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4083 if (ret_val)
4084 goto release;
4085 } else {
4086 old_bank_offset = nvm->flash_bank_size;
4087 new_bank_offset = 0;
4088 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4089 if (ret_val)
4090 goto release;
4091 }
4092 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4093 /* Determine whether to write the value stored
4094 * in the other NVM bank or a modified value stored
4095 * in the shadow RAM
4096 */
4097 ret_val = e1000_read_flash_dword_ich8lan(hw,
4098 i + old_bank_offset,
4099 &dword);
4100
4101 if (dev_spec->shadow_ram[i].modified) {
4102 dword &= 0xffff0000;
4103 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4104 }
4105 if (dev_spec->shadow_ram[i + 1].modified) {
4106 dword &= 0x0000ffff;
4107 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4108 << 16);
4109 }
4110 if (ret_val)
4111 break;
4112
4113 /* If the word is 0x13, then make sure the signature bits
4114 * (15:14) are 11b until the commit has completed.
4115 * This will allow us to write 10b which indicates the
4116 * signature is valid. We want to do this after the write
4117 * has completed so that we don't mark the segment valid
4118 * while the write is still in progress
4119 */
4120 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4121 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4122
4123 /* Convert offset to bytes. */
4124 act_offset = (i + new_bank_offset) << 1;
4125
4126 usec_delay(100);
4127
4128 /* Write the data to the new bank. Offset in words*/
4129 act_offset = i + new_bank_offset;
4130 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4131 dword);
4132 if (ret_val)
4133 break;
4134 }
4135
4136 /* Don't bother writing the segment valid bits if sector
4137 * programming failed.
4138 */
4139 if (ret_val) {
4140 DEBUGOUT("Flash commit failed.\n");
4141 goto release;
4142 }
4143
4144 /* Finally validate the new segment by setting bit 15:14
4145 * to 10b in word 0x13 , this can be done without an
4146 * erase as well since these bits are 11 to start with
4147 * and we need to change bit 14 to 0b
4148 */
4149 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4150
4151 /*offset in words but we read dword*/
4152 --act_offset;
4153 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4154
4155 if (ret_val)
4156 goto release;
4157
4158 dword &= 0xBFFFFFFF;
4159 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4160
4161 if (ret_val)
4162 goto release;
4163
4164 /* And invalidate the previously valid segment by setting
4165 * its signature word (0x13) high_byte to 0b. This can be
4166 * done without an erase because flash erase sets all bits
4167 * to 1's. We can write 1's to 0's without an erase
4168 */
4169 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4170
4171 /* offset in words but we read dword*/
4172 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4173 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4174
4175 if (ret_val)
4176 goto release;
4177
4178 dword &= 0x00FFFFFF;
4179 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4180
4181 if (ret_val)
4182 goto release;
4183
4184 /* Great! Everything worked, we can now clear the cached entries. */
4185 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4186 dev_spec->shadow_ram[i].modified = FALSE;
4187 dev_spec->shadow_ram[i].value = 0xFFFF;
4188 }
4189
4190 release:
4191 nvm->ops.release(hw);
4192
4193 /* Reload the EEPROM, or else modifications will not appear
4194 * until after the next adapter reset.
4195 */
4196 if (!ret_val) {
4197 nvm->ops.reload(hw);
4198 msec_delay(10);
4199 }
4200
4201 out:
4202 if (ret_val)
4203 DEBUGOUT1("NVM update error: %d\n", ret_val);
4204
4205 return ret_val;
4206 }
4207
4208 /**
4209 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4210 * @hw: pointer to the HW structure
4211 *
4212 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4213 * which writes the checksum to the shadow ram. The changes in the shadow
4214 * ram are then committed to the EEPROM by processing each bank at a time
4215 * checking for the modified bit and writing only the pending changes.
4216 * After a successful commit, the shadow ram is cleared and is ready for
4217 * future writes.
4218 **/
e1000_update_nvm_checksum_ich8lan(struct e1000_hw * hw)4219 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4220 {
4221 struct e1000_nvm_info *nvm = &hw->nvm;
4222 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4223 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4224 s32 ret_val;
4225 u16 data = 0;
4226
4227 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4228
4229 ret_val = e1000_update_nvm_checksum_generic(hw);
4230 if (ret_val)
4231 goto out;
4232
4233 if (nvm->type != e1000_nvm_flash_sw)
4234 goto out;
4235
4236 nvm->ops.acquire(hw);
4237
4238 /* We're writing to the opposite bank so if we're on bank 1,
4239 * write to bank 0 etc. We also need to erase the segment that
4240 * is going to be written
4241 */
4242 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4243 if (ret_val != E1000_SUCCESS) {
4244 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4245 bank = 0;
4246 }
4247
4248 if (bank == 0) {
4249 new_bank_offset = nvm->flash_bank_size;
4250 old_bank_offset = 0;
4251 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4252 if (ret_val)
4253 goto release;
4254 } else {
4255 old_bank_offset = nvm->flash_bank_size;
4256 new_bank_offset = 0;
4257 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4258 if (ret_val)
4259 goto release;
4260 }
4261 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4262 if (dev_spec->shadow_ram[i].modified) {
4263 data = dev_spec->shadow_ram[i].value;
4264 } else {
4265 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4266 old_bank_offset,
4267 &data);
4268 if (ret_val)
4269 break;
4270 }
4271 /* If the word is 0x13, then make sure the signature bits
4272 * (15:14) are 11b until the commit has completed.
4273 * This will allow us to write 10b which indicates the
4274 * signature is valid. We want to do this after the write
4275 * has completed so that we don't mark the segment valid
4276 * while the write is still in progress
4277 */
4278 if (i == E1000_ICH_NVM_SIG_WORD)
4279 data |= E1000_ICH_NVM_SIG_MASK;
4280
4281 /* Convert offset to bytes. */
4282 act_offset = (i + new_bank_offset) << 1;
4283
4284 usec_delay(100);
4285
4286 /* Write the bytes to the new bank. */
4287 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4288 act_offset,
4289 (u8)data);
4290 if (ret_val)
4291 break;
4292
4293 usec_delay(100);
4294 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4295 act_offset + 1,
4296 (u8)(data >> 8));
4297 if (ret_val)
4298 break;
4299 }
4300
4301 /* Don't bother writing the segment valid bits if sector
4302 * programming failed.
4303 */
4304 if (ret_val) {
4305 DEBUGOUT("Flash commit failed.\n");
4306 goto release;
4307 }
4308
4309 /* Finally validate the new segment by setting bit 15:14
4310 * to 10b in word 0x13 , this can be done without an
4311 * erase as well since these bits are 11 to start with
4312 * and we need to change bit 14 to 0b
4313 */
4314 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4315 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4316 if (ret_val)
4317 goto release;
4318
4319 data &= 0xBFFF;
4320 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4321 (u8)(data >> 8));
4322 if (ret_val)
4323 goto release;
4324
4325 /* And invalidate the previously valid segment by setting
4326 * its signature word (0x13) high_byte to 0b. This can be
4327 * done without an erase because flash erase sets all bits
4328 * to 1's. We can write 1's to 0's without an erase
4329 */
4330 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4331
4332 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4333
4334 if (ret_val)
4335 goto release;
4336
4337 /* Great! Everything worked, we can now clear the cached entries. */
4338 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4339 dev_spec->shadow_ram[i].modified = FALSE;
4340 dev_spec->shadow_ram[i].value = 0xFFFF;
4341 }
4342
4343 release:
4344 nvm->ops.release(hw);
4345
4346 /* Reload the EEPROM, or else modifications will not appear
4347 * until after the next adapter reset.
4348 */
4349 if (!ret_val) {
4350 nvm->ops.reload(hw);
4351 msec_delay(10);
4352 }
4353
4354 out:
4355 if (ret_val)
4356 DEBUGOUT1("NVM update error: %d\n", ret_val);
4357
4358 return ret_val;
4359 }
4360
4361 /**
4362 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4363 * @hw: pointer to the HW structure
4364 *
4365 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4366 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4367 * calculated, in which case we need to calculate the checksum and set bit 6.
4368 **/
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw * hw)4369 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4370 {
4371 s32 ret_val;
4372 u16 data;
4373 u16 word;
4374 u16 valid_csum_mask;
4375
4376 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4377
4378 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4379 * the checksum needs to be fixed. This bit is an indication that
4380 * the NVM was prepared by OEM software and did not calculate
4381 * the checksum...a likely scenario.
4382 */
4383 switch (hw->mac.type) {
4384 case e1000_pch_lpt:
4385 case e1000_pch_spt:
4386 case e1000_pch_cnp:
4387 word = NVM_COMPAT;
4388 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4389 break;
4390 default:
4391 word = NVM_FUTURE_INIT_WORD1;
4392 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4393 break;
4394 }
4395
4396 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4397 if (ret_val)
4398 return ret_val;
4399
4400 if (!(data & valid_csum_mask)) {
4401 data |= valid_csum_mask;
4402 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4403 if (ret_val)
4404 return ret_val;
4405 ret_val = hw->nvm.ops.update(hw);
4406 if (ret_val)
4407 return ret_val;
4408 }
4409
4410 return e1000_validate_nvm_checksum_generic(hw);
4411 }
4412
4413 /**
4414 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4415 * @hw: pointer to the HW structure
4416 * @offset: The offset (in bytes) of the byte/word to read.
4417 * @size: Size of data to read, 1=byte 2=word
4418 * @data: The byte(s) to write to the NVM.
4419 *
4420 * Writes one/two bytes to the NVM using the flash access registers.
4421 **/
e1000_write_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 data)4422 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4423 u8 size, u16 data)
4424 {
4425 union ich8_hws_flash_status hsfsts;
4426 union ich8_hws_flash_ctrl hsflctl;
4427 u32 flash_linear_addr;
4428 u32 flash_data = 0;
4429 s32 ret_val;
4430 u8 count = 0;
4431
4432 DEBUGFUNC("e1000_write_ich8_data");
4433
4434 if (hw->mac.type >= e1000_pch_spt) {
4435 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4436 return -E1000_ERR_NVM;
4437 } else {
4438 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4439 return -E1000_ERR_NVM;
4440 }
4441
4442 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4443 hw->nvm.flash_base_addr);
4444
4445 do {
4446 usec_delay(1);
4447 /* Steps */
4448 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4449 if (ret_val != E1000_SUCCESS)
4450 break;
4451 /* In SPT, This register is in Lan memory space, not
4452 * flash. Therefore, only 32 bit access is supported
4453 */
4454 if (hw->mac.type >= e1000_pch_spt)
4455 hsflctl.regval =
4456 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4457 else
4458 hsflctl.regval =
4459 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4460
4461 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4462 hsflctl.hsf_ctrl.fldbcount = size - 1;
4463 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4464 /* In SPT, This register is in Lan memory space,
4465 * not flash. Therefore, only 32 bit access is
4466 * supported
4467 */
4468 if (hw->mac.type >= e1000_pch_spt)
4469 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4470 hsflctl.regval << 16);
4471 else
4472 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4473 hsflctl.regval);
4474
4475 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4476
4477 if (size == 1)
4478 flash_data = (u32)data & 0x00FF;
4479 else
4480 flash_data = (u32)data;
4481
4482 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4483
4484 /* check if FCERR is set to 1 , if set to 1, clear it
4485 * and try the whole sequence a few more times else done
4486 */
4487 ret_val =
4488 e1000_flash_cycle_ich8lan(hw,
4489 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4490 if (ret_val == E1000_SUCCESS)
4491 break;
4492
4493 /* If we're here, then things are most likely
4494 * completely hosed, but if the error condition
4495 * is detected, it won't hurt to give it another
4496 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4497 */
4498 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4499 if (hsfsts.hsf_status.flcerr)
4500 /* Repeat for some time before giving up. */
4501 continue;
4502 if (!hsfsts.hsf_status.flcdone) {
4503 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4504 break;
4505 }
4506 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4507
4508 return ret_val;
4509 }
4510
4511 /**
4512 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4513 * @hw: pointer to the HW structure
4514 * @offset: The offset (in bytes) of the dwords to read.
4515 * @data: The 4 bytes to write to the NVM.
4516 *
4517 * Writes one/two/four bytes to the NVM using the flash access registers.
4518 **/
e1000_write_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 data)4519 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4520 u32 data)
4521 {
4522 union ich8_hws_flash_status hsfsts;
4523 union ich8_hws_flash_ctrl hsflctl;
4524 u32 flash_linear_addr;
4525 s32 ret_val;
4526 u8 count = 0;
4527
4528 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4529
4530 if (hw->mac.type >= e1000_pch_spt) {
4531 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4532 return -E1000_ERR_NVM;
4533 }
4534 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4535 hw->nvm.flash_base_addr);
4536 do {
4537 usec_delay(1);
4538 /* Steps */
4539 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4540 if (ret_val != E1000_SUCCESS)
4541 break;
4542
4543 /* In SPT, This register is in Lan memory space, not
4544 * flash. Therefore, only 32 bit access is supported
4545 */
4546 if (hw->mac.type >= e1000_pch_spt)
4547 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4548 ICH_FLASH_HSFSTS)
4549 >> 16;
4550 else
4551 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4552 ICH_FLASH_HSFCTL);
4553
4554 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4555 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4556
4557 /* In SPT, This register is in Lan memory space,
4558 * not flash. Therefore, only 32 bit access is
4559 * supported
4560 */
4561 if (hw->mac.type >= e1000_pch_spt)
4562 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4563 hsflctl.regval << 16);
4564 else
4565 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4566 hsflctl.regval);
4567
4568 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4569
4570 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4571
4572 /* check if FCERR is set to 1 , if set to 1, clear it
4573 * and try the whole sequence a few more times else done
4574 */
4575 ret_val = e1000_flash_cycle_ich8lan(hw,
4576 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4577
4578 if (ret_val == E1000_SUCCESS)
4579 break;
4580
4581 /* If we're here, then things are most likely
4582 * completely hosed, but if the error condition
4583 * is detected, it won't hurt to give it another
4584 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4585 */
4586 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4587
4588 if (hsfsts.hsf_status.flcerr)
4589 /* Repeat for some time before giving up. */
4590 continue;
4591 if (!hsfsts.hsf_status.flcdone) {
4592 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4593 break;
4594 }
4595 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4596
4597 return ret_val;
4598 }
4599
4600 /**
4601 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4602 * @hw: pointer to the HW structure
4603 * @offset: The index of the byte to read.
4604 * @data: The byte to write to the NVM.
4605 *
4606 * Writes a single byte to the NVM using the flash access registers.
4607 **/
e1000_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 data)4608 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4609 u8 data)
4610 {
4611 u16 word = (u16)data;
4612
4613 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4614
4615 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4616 }
4617
4618 /**
4619 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4620 * @hw: pointer to the HW structure
4621 * @offset: The offset of the word to write.
4622 * @dword: The dword to write to the NVM.
4623 *
4624 * Writes a single dword to the NVM using the flash access registers.
4625 * Goes through a retry algorithm before giving up.
4626 **/
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 dword)4627 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4628 u32 offset, u32 dword)
4629 {
4630 s32 ret_val;
4631 u16 program_retries;
4632
4633 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4634
4635 /* Must convert word offset into bytes. */
4636 offset <<= 1;
4637
4638 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4639
4640 if (!ret_val)
4641 return ret_val;
4642 for (program_retries = 0; program_retries < 100; program_retries++) {
4643 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4644 usec_delay(100);
4645 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4646 if (ret_val == E1000_SUCCESS)
4647 break;
4648 }
4649 if (program_retries == 100)
4650 return -E1000_ERR_NVM;
4651
4652 return E1000_SUCCESS;
4653 }
4654
4655 /**
4656 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4657 * @hw: pointer to the HW structure
4658 * @offset: The offset of the byte to write.
4659 * @byte: The byte to write to the NVM.
4660 *
4661 * Writes a single byte to the NVM using the flash access registers.
4662 * Goes through a retry algorithm before giving up.
4663 **/
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 byte)4664 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4665 u32 offset, u8 byte)
4666 {
4667 s32 ret_val;
4668 u16 program_retries;
4669
4670 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4671
4672 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4673 if (!ret_val)
4674 return ret_val;
4675
4676 for (program_retries = 0; program_retries < 100; program_retries++) {
4677 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4678 usec_delay(100);
4679 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4680 if (ret_val == E1000_SUCCESS)
4681 break;
4682 }
4683 if (program_retries == 100)
4684 return -E1000_ERR_NVM;
4685
4686 return E1000_SUCCESS;
4687 }
4688
4689 /**
4690 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4691 * @hw: pointer to the HW structure
4692 * @bank: 0 for first bank, 1 for second bank, etc.
4693 *
4694 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4695 * bank N is 4096 * N + flash_reg_addr.
4696 **/
e1000_erase_flash_bank_ich8lan(struct e1000_hw * hw,u32 bank)4697 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4698 {
4699 struct e1000_nvm_info *nvm = &hw->nvm;
4700 union ich8_hws_flash_status hsfsts;
4701 union ich8_hws_flash_ctrl hsflctl;
4702 u32 flash_linear_addr;
4703 /* bank size is in 16bit words - adjust to bytes */
4704 u32 flash_bank_size = nvm->flash_bank_size * 2;
4705 s32 ret_val;
4706 s32 count = 0;
4707 s32 j, iteration, sector_size;
4708
4709 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4710
4711 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4712
4713 /* Determine HW Sector size: Read BERASE bits of hw flash status
4714 * register
4715 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4716 * consecutive sectors. The start index for the nth Hw sector
4717 * can be calculated as = bank * 4096 + n * 256
4718 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4719 * The start index for the nth Hw sector can be calculated
4720 * as = bank * 4096
4721 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4722 * (ich9 only, otherwise error condition)
4723 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4724 */
4725 switch (hsfsts.hsf_status.berasesz) {
4726 case 0:
4727 /* Hw sector size 256 */
4728 sector_size = ICH_FLASH_SEG_SIZE_256;
4729 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4730 break;
4731 case 1:
4732 sector_size = ICH_FLASH_SEG_SIZE_4K;
4733 iteration = 1;
4734 break;
4735 case 2:
4736 sector_size = ICH_FLASH_SEG_SIZE_8K;
4737 iteration = 1;
4738 break;
4739 case 3:
4740 sector_size = ICH_FLASH_SEG_SIZE_64K;
4741 iteration = 1;
4742 break;
4743 default:
4744 return -E1000_ERR_NVM;
4745 }
4746
4747 /* Start with the base address, then add the sector offset. */
4748 flash_linear_addr = hw->nvm.flash_base_addr;
4749 flash_linear_addr += (bank) ? flash_bank_size : 0;
4750
4751 for (j = 0; j < iteration; j++) {
4752 do {
4753 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4754
4755 /* Steps */
4756 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4757 if (ret_val)
4758 return ret_val;
4759
4760 /* Write a value 11 (block Erase) in Flash
4761 * Cycle field in hw flash control
4762 */
4763 if (hw->mac.type >= e1000_pch_spt)
4764 hsflctl.regval =
4765 E1000_READ_FLASH_REG(hw,
4766 ICH_FLASH_HSFSTS)>>16;
4767 else
4768 hsflctl.regval =
4769 E1000_READ_FLASH_REG16(hw,
4770 ICH_FLASH_HSFCTL);
4771
4772 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4773 if (hw->mac.type >= e1000_pch_spt)
4774 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4775 hsflctl.regval << 16);
4776 else
4777 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4778 hsflctl.regval);
4779
4780 /* Write the last 24 bits of an index within the
4781 * block into Flash Linear address field in Flash
4782 * Address.
4783 */
4784 flash_linear_addr += (j * sector_size);
4785 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4786 flash_linear_addr);
4787
4788 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4789 if (ret_val == E1000_SUCCESS)
4790 break;
4791
4792 /* Check if FCERR is set to 1. If 1,
4793 * clear it and try the whole sequence
4794 * a few more times else Done
4795 */
4796 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4797 ICH_FLASH_HSFSTS);
4798 if (hsfsts.hsf_status.flcerr)
4799 /* repeat for some time before giving up */
4800 continue;
4801 else if (!hsfsts.hsf_status.flcdone)
4802 return ret_val;
4803 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4804 }
4805
4806 return E1000_SUCCESS;
4807 }
4808
4809 /**
4810 * e1000_valid_led_default_ich8lan - Set the default LED settings
4811 * @hw: pointer to the HW structure
4812 * @data: Pointer to the LED settings
4813 *
4814 * Reads the LED default settings from the NVM to data. If the NVM LED
4815 * settings is all 0's or F's, set the LED default to a valid LED default
4816 * setting.
4817 **/
e1000_valid_led_default_ich8lan(struct e1000_hw * hw,u16 * data)4818 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4819 {
4820 s32 ret_val;
4821
4822 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4823
4824 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4825 if (ret_val) {
4826 DEBUGOUT("NVM Read Error\n");
4827 return ret_val;
4828 }
4829
4830 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4831 *data = ID_LED_DEFAULT_ICH8LAN;
4832
4833 return E1000_SUCCESS;
4834 }
4835
4836 /**
4837 * e1000_id_led_init_pchlan - store LED configurations
4838 * @hw: pointer to the HW structure
4839 *
4840 * PCH does not control LEDs via the LEDCTL register, rather it uses
4841 * the PHY LED configuration register.
4842 *
4843 * PCH also does not have an "always on" or "always off" mode which
4844 * complicates the ID feature. Instead of using the "on" mode to indicate
4845 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4846 * use "link_up" mode. The LEDs will still ID on request if there is no
4847 * link based on logic in e1000_led_[on|off]_pchlan().
4848 **/
e1000_id_led_init_pchlan(struct e1000_hw * hw)4849 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4850 {
4851 struct e1000_mac_info *mac = &hw->mac;
4852 s32 ret_val;
4853 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4854 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4855 u16 data, i, temp, shift;
4856
4857 DEBUGFUNC("e1000_id_led_init_pchlan");
4858
4859 /* Get default ID LED modes */
4860 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4861 if (ret_val)
4862 return ret_val;
4863
4864 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4865 mac->ledctl_mode1 = mac->ledctl_default;
4866 mac->ledctl_mode2 = mac->ledctl_default;
4867
4868 for (i = 0; i < 4; i++) {
4869 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4870 shift = (i * 5);
4871 switch (temp) {
4872 case ID_LED_ON1_DEF2:
4873 case ID_LED_ON1_ON2:
4874 case ID_LED_ON1_OFF2:
4875 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4876 mac->ledctl_mode1 |= (ledctl_on << shift);
4877 break;
4878 case ID_LED_OFF1_DEF2:
4879 case ID_LED_OFF1_ON2:
4880 case ID_LED_OFF1_OFF2:
4881 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4882 mac->ledctl_mode1 |= (ledctl_off << shift);
4883 break;
4884 default:
4885 /* Do nothing */
4886 break;
4887 }
4888 switch (temp) {
4889 case ID_LED_DEF1_ON2:
4890 case ID_LED_ON1_ON2:
4891 case ID_LED_OFF1_ON2:
4892 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4893 mac->ledctl_mode2 |= (ledctl_on << shift);
4894 break;
4895 case ID_LED_DEF1_OFF2:
4896 case ID_LED_ON1_OFF2:
4897 case ID_LED_OFF1_OFF2:
4898 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4899 mac->ledctl_mode2 |= (ledctl_off << shift);
4900 break;
4901 default:
4902 /* Do nothing */
4903 break;
4904 }
4905 }
4906
4907 return E1000_SUCCESS;
4908 }
4909
4910 /**
4911 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4912 * @hw: pointer to the HW structure
4913 *
4914 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4915 * register, so the bus width is hard coded.
4916 **/
e1000_get_bus_info_ich8lan(struct e1000_hw * hw)4917 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4918 {
4919 struct e1000_bus_info *bus = &hw->bus;
4920 s32 ret_val;
4921
4922 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4923
4924 ret_val = e1000_get_bus_info_pcie_generic(hw);
4925
4926 /* ICH devices are "PCI Express"-ish. They have
4927 * a configuration space, but do not contain
4928 * PCI Express Capability registers, so bus width
4929 * must be hardcoded.
4930 */
4931 if (bus->width == e1000_bus_width_unknown)
4932 bus->width = e1000_bus_width_pcie_x1;
4933
4934 return ret_val;
4935 }
4936
4937 /**
4938 * e1000_reset_hw_ich8lan - Reset the hardware
4939 * @hw: pointer to the HW structure
4940 *
4941 * Does a full reset of the hardware which includes a reset of the PHY and
4942 * MAC.
4943 **/
e1000_reset_hw_ich8lan(struct e1000_hw * hw)4944 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4945 {
4946 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4947 u16 kum_cfg;
4948 u32 ctrl, reg;
4949 s32 ret_val;
4950
4951 DEBUGFUNC("e1000_reset_hw_ich8lan");
4952
4953 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4954 * on the last TLP read/write transaction when MAC is reset.
4955 */
4956 ret_val = e1000_disable_pcie_master_generic(hw);
4957 if (ret_val)
4958 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4959
4960 DEBUGOUT("Masking off all interrupts\n");
4961 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4962
4963 /* Disable the Transmit and Receive units. Then delay to allow
4964 * any pending transactions to complete before we hit the MAC
4965 * with the global reset.
4966 */
4967 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4968 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4969 E1000_WRITE_FLUSH(hw);
4970
4971 msec_delay(10);
4972
4973 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4974 if (hw->mac.type == e1000_ich8lan) {
4975 /* Set Tx and Rx buffer allocation to 8k apiece. */
4976 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4977 /* Set Packet Buffer Size to 16k. */
4978 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4979 }
4980
4981 if (hw->mac.type == e1000_pchlan) {
4982 /* Save the NVM K1 bit setting*/
4983 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4984 if (ret_val)
4985 return ret_val;
4986
4987 if (kum_cfg & E1000_NVM_K1_ENABLE)
4988 dev_spec->nvm_k1_enabled = TRUE;
4989 else
4990 dev_spec->nvm_k1_enabled = FALSE;
4991 }
4992
4993 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4994
4995 if (!hw->phy.ops.check_reset_block(hw)) {
4996 /* Full-chip reset requires MAC and PHY reset at the same
4997 * time to make sure the interface between MAC and the
4998 * external PHY is reset.
4999 */
5000 ctrl |= E1000_CTRL_PHY_RST;
5001
5002 /* Gate automatic PHY configuration by hardware on
5003 * non-managed 82579
5004 */
5005 if ((hw->mac.type == e1000_pch2lan) &&
5006 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5007 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
5008 }
5009 ret_val = e1000_acquire_swflag_ich8lan(hw);
5010 DEBUGOUT("Issuing a global reset to ich8lan\n");
5011 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5012 /* cannot issue a flush here because it hangs the hardware */
5013 msec_delay(20);
5014
5015 /* Set Phy Config Counter to 50msec */
5016 if (hw->mac.type == e1000_pch2lan) {
5017 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5018 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
5019 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
5020 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5021 }
5022
5023
5024 if (ctrl & E1000_CTRL_PHY_RST) {
5025 ret_val = hw->phy.ops.get_cfg_done(hw);
5026 if (ret_val)
5027 return ret_val;
5028
5029 ret_val = e1000_post_phy_reset_ich8lan(hw);
5030 if (ret_val)
5031 return ret_val;
5032 }
5033
5034 /* For PCH, this write will make sure that any noise
5035 * will be detected as a CRC error and be dropped rather than show up
5036 * as a bad packet to the DMA engine.
5037 */
5038 if (hw->mac.type == e1000_pchlan)
5039 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5040
5041 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5042 E1000_READ_REG(hw, E1000_ICR);
5043
5044 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5045 reg |= E1000_KABGTXD_BGSQLBIAS;
5046 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5047
5048 return E1000_SUCCESS;
5049 }
5050
5051 /**
5052 * e1000_init_hw_ich8lan - Initialize the hardware
5053 * @hw: pointer to the HW structure
5054 *
5055 * Prepares the hardware for transmit and receive by doing the following:
5056 * - initialize hardware bits
5057 * - initialize LED identification
5058 * - setup receive address registers
5059 * - setup flow control
5060 * - setup transmit descriptors
5061 * - clear statistics
5062 **/
e1000_init_hw_ich8lan(struct e1000_hw * hw)5063 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5064 {
5065 struct e1000_mac_info *mac = &hw->mac;
5066 u32 ctrl_ext, txdctl, snoop;
5067 s32 ret_val;
5068 u16 i;
5069
5070 DEBUGFUNC("e1000_init_hw_ich8lan");
5071
5072 e1000_initialize_hw_bits_ich8lan(hw);
5073
5074 /* Initialize identification LED */
5075 ret_val = mac->ops.id_led_init(hw);
5076 /* An error is not fatal and we should not stop init due to this */
5077 if (ret_val)
5078 DEBUGOUT("Error initializing identification LED\n");
5079
5080 /* Setup the receive address. */
5081 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5082
5083 /* Zero out the Multicast HASH table */
5084 DEBUGOUT("Zeroing the MTA\n");
5085 for (i = 0; i < mac->mta_reg_count; i++)
5086 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5087
5088 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5089 * the ME. Disable wakeup by clearing the host wakeup bit.
5090 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5091 */
5092 if (hw->phy.type == e1000_phy_82578) {
5093 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5094 i &= ~BM_WUC_HOST_WU_BIT;
5095 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5096 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5097 if (ret_val)
5098 return ret_val;
5099 }
5100
5101 /* Setup link and flow control */
5102 ret_val = mac->ops.setup_link(hw);
5103
5104 /* Set the transmit descriptor write-back policy for both queues */
5105 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5106 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5107 E1000_TXDCTL_FULL_TX_DESC_WB);
5108 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5109 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5110 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5111 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5112 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5113 E1000_TXDCTL_FULL_TX_DESC_WB);
5114 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5115 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5116 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5117
5118 /* ICH8 has opposite polarity of no_snoop bits.
5119 * By default, we should use snoop behavior.
5120 */
5121 if (mac->type == e1000_ich8lan)
5122 snoop = PCIE_ICH8_SNOOP_ALL;
5123 else
5124 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5125 e1000_set_pcie_no_snoop_generic(hw, snoop);
5126
5127 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5128 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5129 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5130
5131 /* Clear all of the statistics registers (clear on read). It is
5132 * important that we do this after we have tried to establish link
5133 * because the symbol error count will increment wildly if there
5134 * is no link.
5135 */
5136 e1000_clear_hw_cntrs_ich8lan(hw);
5137
5138 return ret_val;
5139 }
5140
5141 /**
5142 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5143 * @hw: pointer to the HW structure
5144 *
5145 * Sets/Clears required hardware bits necessary for correctly setting up the
5146 * hardware for transmit and receive.
5147 **/
e1000_initialize_hw_bits_ich8lan(struct e1000_hw * hw)5148 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5149 {
5150 u32 reg;
5151
5152 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5153
5154 /* Extended Device Control */
5155 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5156 reg |= (1 << 22);
5157 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5158 if (hw->mac.type >= e1000_pchlan)
5159 reg |= E1000_CTRL_EXT_PHYPDEN;
5160 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5161
5162 /* Transmit Descriptor Control 0 */
5163 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5164 reg |= (1 << 22);
5165 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5166
5167 /* Transmit Descriptor Control 1 */
5168 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5169 reg |= (1 << 22);
5170 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5171
5172 /* Transmit Arbitration Control 0 */
5173 reg = E1000_READ_REG(hw, E1000_TARC(0));
5174 if (hw->mac.type == e1000_ich8lan)
5175 reg |= (1 << 28) | (1 << 29);
5176 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5177 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5178
5179 /* Transmit Arbitration Control 1 */
5180 reg = E1000_READ_REG(hw, E1000_TARC(1));
5181 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5182 reg &= ~(1 << 28);
5183 else
5184 reg |= (1 << 28);
5185 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5186 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5187
5188 /* Device Status */
5189 if (hw->mac.type == e1000_ich8lan) {
5190 reg = E1000_READ_REG(hw, E1000_STATUS);
5191 reg &= ~(1U << 31);
5192 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5193 }
5194
5195 /* work-around descriptor data corruption issue during nfs v2 udp
5196 * traffic, just disable the nfs filtering capability
5197 */
5198 reg = E1000_READ_REG(hw, E1000_RFCTL);
5199 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5200
5201 /* Disable IPv6 extension header parsing because some malformed
5202 * IPv6 headers can hang the Rx.
5203 */
5204 if (hw->mac.type == e1000_ich8lan)
5205 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5206 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5207
5208 /* Enable ECC on Lynxpoint */
5209 if (hw->mac.type >= e1000_pch_lpt) {
5210 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5211 reg |= E1000_PBECCSTS_ECC_ENABLE;
5212 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5213
5214 reg = E1000_READ_REG(hw, E1000_CTRL);
5215 reg |= E1000_CTRL_MEHE;
5216 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5217 }
5218
5219 return;
5220 }
5221
5222 /**
5223 * e1000_setup_link_ich8lan - Setup flow control and link settings
5224 * @hw: pointer to the HW structure
5225 *
5226 * Determines which flow control settings to use, then configures flow
5227 * control. Calls the appropriate media-specific link configuration
5228 * function. Assuming the adapter has a valid link partner, a valid link
5229 * should be established. Assumes the hardware has previously been reset
5230 * and the transmitter and receiver are not enabled.
5231 **/
e1000_setup_link_ich8lan(struct e1000_hw * hw)5232 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5233 {
5234 s32 ret_val;
5235
5236 DEBUGFUNC("e1000_setup_link_ich8lan");
5237
5238 if (hw->phy.ops.check_reset_block(hw))
5239 return E1000_SUCCESS;
5240
5241 /* ICH parts do not have a word in the NVM to determine
5242 * the default flow control setting, so we explicitly
5243 * set it to full.
5244 */
5245 if (hw->fc.requested_mode == e1000_fc_default)
5246 hw->fc.requested_mode = e1000_fc_full;
5247
5248 /* Save off the requested flow control mode for use later. Depending
5249 * on the link partner's capabilities, we may or may not use this mode.
5250 */
5251 hw->fc.current_mode = hw->fc.requested_mode;
5252
5253 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5254 hw->fc.current_mode);
5255
5256 /* Continue to configure the copper link. */
5257 ret_val = hw->mac.ops.setup_physical_interface(hw);
5258 if (ret_val)
5259 return ret_val;
5260
5261 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5262 if ((hw->phy.type == e1000_phy_82578) ||
5263 (hw->phy.type == e1000_phy_82579) ||
5264 (hw->phy.type == e1000_phy_i217) ||
5265 (hw->phy.type == e1000_phy_82577)) {
5266 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5267
5268 ret_val = hw->phy.ops.write_reg(hw,
5269 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5270 hw->fc.pause_time);
5271 if (ret_val)
5272 return ret_val;
5273 }
5274
5275 return e1000_set_fc_watermarks_generic(hw);
5276 }
5277
5278 /**
5279 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5280 * @hw: pointer to the HW structure
5281 *
5282 * Configures the kumeran interface to the PHY to wait the appropriate time
5283 * when polling the PHY, then call the generic setup_copper_link to finish
5284 * configuring the copper link.
5285 **/
e1000_setup_copper_link_ich8lan(struct e1000_hw * hw)5286 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5287 {
5288 u32 ctrl;
5289 s32 ret_val;
5290 u16 reg_data;
5291
5292 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5293
5294 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5295 ctrl |= E1000_CTRL_SLU;
5296 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5297 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5298
5299 /* Set the mac to wait the maximum time between each iteration
5300 * and increase the max iterations when polling the phy;
5301 * this fixes erroneous timeouts at 10Mbps.
5302 */
5303 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5304 0xFFFF);
5305 if (ret_val)
5306 return ret_val;
5307 ret_val = e1000_read_kmrn_reg_generic(hw,
5308 E1000_KMRNCTRLSTA_INBAND_PARAM,
5309 ®_data);
5310 if (ret_val)
5311 return ret_val;
5312 reg_data |= 0x3F;
5313 ret_val = e1000_write_kmrn_reg_generic(hw,
5314 E1000_KMRNCTRLSTA_INBAND_PARAM,
5315 reg_data);
5316 if (ret_val)
5317 return ret_val;
5318
5319 switch (hw->phy.type) {
5320 case e1000_phy_igp_3:
5321 ret_val = e1000_copper_link_setup_igp(hw);
5322 if (ret_val)
5323 return ret_val;
5324 break;
5325 case e1000_phy_bm:
5326 case e1000_phy_82578:
5327 ret_val = e1000_copper_link_setup_m88(hw);
5328 if (ret_val)
5329 return ret_val;
5330 break;
5331 case e1000_phy_82577:
5332 case e1000_phy_82579:
5333 ret_val = e1000_copper_link_setup_82577(hw);
5334 if (ret_val)
5335 return ret_val;
5336 break;
5337 case e1000_phy_ife:
5338 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5339 ®_data);
5340 if (ret_val)
5341 return ret_val;
5342
5343 reg_data &= ~IFE_PMC_AUTO_MDIX;
5344
5345 switch (hw->phy.mdix) {
5346 case 1:
5347 reg_data &= ~IFE_PMC_FORCE_MDIX;
5348 break;
5349 case 2:
5350 reg_data |= IFE_PMC_FORCE_MDIX;
5351 break;
5352 case 0:
5353 default:
5354 reg_data |= IFE_PMC_AUTO_MDIX;
5355 break;
5356 }
5357 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5358 reg_data);
5359 if (ret_val)
5360 return ret_val;
5361 break;
5362 default:
5363 break;
5364 }
5365
5366 return e1000_setup_copper_link_generic(hw);
5367 }
5368
5369 /**
5370 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5371 * @hw: pointer to the HW structure
5372 *
5373 * Calls the PHY specific link setup function and then calls the
5374 * generic setup_copper_link to finish configuring the link for
5375 * Lynxpoint PCH devices
5376 **/
e1000_setup_copper_link_pch_lpt(struct e1000_hw * hw)5377 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5378 {
5379 u32 ctrl;
5380 s32 ret_val;
5381
5382 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5383
5384 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5385 ctrl |= E1000_CTRL_SLU;
5386 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5387 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5388
5389 ret_val = e1000_copper_link_setup_82577(hw);
5390 if (ret_val)
5391 return ret_val;
5392
5393 return e1000_setup_copper_link_generic(hw);
5394 }
5395
5396 /**
5397 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5398 * @hw: pointer to the HW structure
5399 * @speed: pointer to store current link speed
5400 * @duplex: pointer to store the current link duplex
5401 *
5402 * Calls the generic get_speed_and_duplex to retrieve the current link
5403 * information and then calls the Kumeran lock loss workaround for links at
5404 * gigabit speeds.
5405 **/
e1000_get_link_up_info_ich8lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)5406 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5407 u16 *duplex)
5408 {
5409 s32 ret_val;
5410
5411 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5412
5413 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5414 if (ret_val)
5415 return ret_val;
5416
5417 if ((hw->mac.type == e1000_ich8lan) &&
5418 (hw->phy.type == e1000_phy_igp_3) &&
5419 (*speed == SPEED_1000)) {
5420 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5421 }
5422
5423 return ret_val;
5424 }
5425
5426 /**
5427 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5428 * @hw: pointer to the HW structure
5429 *
5430 * Work-around for 82566 Kumeran PCS lock loss:
5431 * On link status change (i.e. PCI reset, speed change) and link is up and
5432 * speed is gigabit-
5433 * 0) if workaround is optionally disabled do nothing
5434 * 1) wait 1ms for Kumeran link to come up
5435 * 2) check Kumeran Diagnostic register PCS lock loss bit
5436 * 3) if not set the link is locked (all is good), otherwise...
5437 * 4) reset the PHY
5438 * 5) repeat up to 10 times
5439 * Note: this is only called for IGP3 copper when speed is 1gb.
5440 **/
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw)5441 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5442 {
5443 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5444 u32 phy_ctrl;
5445 s32 ret_val;
5446 u16 i, data;
5447 bool link;
5448
5449 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5450
5451 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5452 return E1000_SUCCESS;
5453
5454 /* Make sure link is up before proceeding. If not just return.
5455 * Attempting this while link is negotiating fouled up link
5456 * stability
5457 */
5458 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5459 if (!link)
5460 return E1000_SUCCESS;
5461
5462 for (i = 0; i < 10; i++) {
5463 /* read once to clear */
5464 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5465 if (ret_val)
5466 return ret_val;
5467 /* and again to get new status */
5468 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5469 if (ret_val)
5470 return ret_val;
5471
5472 /* check for PCS lock */
5473 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5474 return E1000_SUCCESS;
5475
5476 /* Issue PHY reset */
5477 hw->phy.ops.reset(hw);
5478 msec_delay_irq(5);
5479 }
5480 /* Disable GigE link negotiation */
5481 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5482 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5483 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5484 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5485
5486 /* Call gig speed drop workaround on Gig disable before accessing
5487 * any PHY registers
5488 */
5489 e1000_gig_downshift_workaround_ich8lan(hw);
5490
5491 /* unable to acquire PCS lock */
5492 return -E1000_ERR_PHY;
5493 }
5494
5495 /**
5496 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5497 * @hw: pointer to the HW structure
5498 * @state: boolean value used to set the current Kumeran workaround state
5499 *
5500 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
5501 * /disabled - FALSE).
5502 **/
e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw,bool state)5503 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5504 bool state)
5505 {
5506 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5507
5508 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5509
5510 if (hw->mac.type != e1000_ich8lan) {
5511 DEBUGOUT("Workaround applies to ICH8 only.\n");
5512 return;
5513 }
5514
5515 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5516
5517 return;
5518 }
5519
5520 /**
5521 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5522 * @hw: pointer to the HW structure
5523 *
5524 * Workaround for 82566 power-down on D3 entry:
5525 * 1) disable gigabit link
5526 * 2) write VR power-down enable
5527 * 3) read it back
5528 * Continue if successful, else issue LCD reset and repeat
5529 **/
e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw * hw)5530 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5531 {
5532 u32 reg;
5533 u16 data;
5534 u8 retry = 0;
5535
5536 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5537
5538 if (hw->phy.type != e1000_phy_igp_3)
5539 return;
5540
5541 /* Try the workaround twice (if needed) */
5542 do {
5543 /* Disable link */
5544 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5545 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5546 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5547 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5548
5549 /* Call gig speed drop workaround on Gig disable before
5550 * accessing any PHY registers
5551 */
5552 if (hw->mac.type == e1000_ich8lan)
5553 e1000_gig_downshift_workaround_ich8lan(hw);
5554
5555 /* Write VR power-down enable */
5556 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5557 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5558 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5559 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5560
5561 /* Read it back and test */
5562 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5563 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5564 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5565 break;
5566
5567 /* Issue PHY reset and repeat at most one more time */
5568 reg = E1000_READ_REG(hw, E1000_CTRL);
5569 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5570 retry++;
5571 } while (retry);
5572 }
5573
5574 /**
5575 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5576 * @hw: pointer to the HW structure
5577 *
5578 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5579 * LPLU, Gig disable, MDIC PHY reset):
5580 * 1) Set Kumeran Near-end loopback
5581 * 2) Clear Kumeran Near-end loopback
5582 * Should only be called for ICH8[m] devices with any 1G Phy.
5583 **/
e1000_gig_downshift_workaround_ich8lan(struct e1000_hw * hw)5584 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5585 {
5586 s32 ret_val;
5587 u16 reg_data;
5588
5589 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5590
5591 if ((hw->mac.type != e1000_ich8lan) ||
5592 (hw->phy.type == e1000_phy_ife))
5593 return;
5594
5595 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5596 ®_data);
5597 if (ret_val)
5598 return;
5599 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5600 ret_val = e1000_write_kmrn_reg_generic(hw,
5601 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5602 reg_data);
5603 if (ret_val)
5604 return;
5605 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5606 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5607 reg_data);
5608 }
5609
5610 /**
5611 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5612 * @hw: pointer to the HW structure
5613 *
5614 * During S0 to Sx transition, it is possible the link remains at gig
5615 * instead of negotiating to a lower speed. Before going to Sx, set
5616 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5617 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5618 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5619 * needs to be written.
5620 * Parts that support (and are linked to a partner which support) EEE in
5621 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5622 * than 10Mbps w/o EEE.
5623 **/
e1000_suspend_workarounds_ich8lan(struct e1000_hw * hw)5624 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5625 {
5626 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5627 u32 phy_ctrl;
5628 s32 ret_val;
5629
5630 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5631
5632 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5633 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5634
5635 if (hw->phy.type == e1000_phy_i217) {
5636 u16 phy_reg, device_id = hw->device_id;
5637
5638 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5639 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5640 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5641 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5642 (hw->mac.type >= e1000_pch_spt)) {
5643 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5644
5645 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5646 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5647 }
5648
5649 ret_val = hw->phy.ops.acquire(hw);
5650 if (ret_val)
5651 goto out;
5652
5653 if (!dev_spec->eee_disable) {
5654 u16 eee_advert;
5655
5656 ret_val =
5657 e1000_read_emi_reg_locked(hw,
5658 I217_EEE_ADVERTISEMENT,
5659 &eee_advert);
5660 if (ret_val)
5661 goto release;
5662
5663 /* Disable LPLU if both link partners support 100BaseT
5664 * EEE and 100Full is advertised on both ends of the
5665 * link, and enable Auto Enable LPI since there will
5666 * be no driver to enable LPI while in Sx.
5667 */
5668 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5669 (dev_spec->eee_lp_ability &
5670 I82579_EEE_100_SUPPORTED) &&
5671 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5672 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5673 E1000_PHY_CTRL_NOND0A_LPLU);
5674
5675 /* Set Auto Enable LPI after link up */
5676 hw->phy.ops.read_reg_locked(hw,
5677 I217_LPI_GPIO_CTRL,
5678 &phy_reg);
5679 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5680 hw->phy.ops.write_reg_locked(hw,
5681 I217_LPI_GPIO_CTRL,
5682 phy_reg);
5683 }
5684 }
5685
5686 /* For i217 Intel Rapid Start Technology support,
5687 * when the system is going into Sx and no manageability engine
5688 * is present, the driver must configure proxy to reset only on
5689 * power good. LPI (Low Power Idle) state must also reset only
5690 * on power good, as well as the MTA (Multicast table array).
5691 * The SMBus release must also be disabled on LCD reset.
5692 */
5693 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5694 E1000_ICH_FWSM_FW_VALID)) {
5695 /* Enable proxy to reset only on power good. */
5696 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5697 &phy_reg);
5698 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5699 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5700 phy_reg);
5701
5702 /* Set bit enable LPI (EEE) to reset only on
5703 * power good.
5704 */
5705 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5706 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5707 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5708
5709 /* Disable the SMB release on LCD reset. */
5710 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5711 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5712 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5713 }
5714
5715 /* Enable MTA to reset for Intel Rapid Start Technology
5716 * Support
5717 */
5718 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5719 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5720 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5721
5722 release:
5723 hw->phy.ops.release(hw);
5724 }
5725 out:
5726 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5727
5728 if (hw->mac.type == e1000_ich8lan)
5729 e1000_gig_downshift_workaround_ich8lan(hw);
5730
5731 if (hw->mac.type >= e1000_pchlan) {
5732 e1000_oem_bits_config_ich8lan(hw, FALSE);
5733
5734 /* Reset PHY to activate OEM bits on 82577/8 */
5735 if (hw->mac.type == e1000_pchlan)
5736 e1000_phy_hw_reset_generic(hw);
5737
5738 ret_val = hw->phy.ops.acquire(hw);
5739 if (ret_val)
5740 return;
5741 e1000_write_smbus_addr(hw);
5742 hw->phy.ops.release(hw);
5743 }
5744
5745 return;
5746 }
5747
5748 /**
5749 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5750 * @hw: pointer to the HW structure
5751 *
5752 * During Sx to S0 transitions on non-managed devices or managed devices
5753 * on which PHY resets are not blocked, if the PHY registers cannot be
5754 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5755 * the PHY.
5756 * On i217, setup Intel Rapid Start Technology.
5757 **/
e1000_resume_workarounds_pchlan(struct e1000_hw * hw)5758 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5759 {
5760 s32 ret_val;
5761
5762 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5763 if (hw->mac.type < e1000_pch2lan)
5764 return E1000_SUCCESS;
5765
5766 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5767 if (ret_val) {
5768 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5769 return ret_val;
5770 }
5771
5772 /* For i217 Intel Rapid Start Technology support when the system
5773 * is transitioning from Sx and no manageability engine is present
5774 * configure SMBus to restore on reset, disable proxy, and enable
5775 * the reset on MTA (Multicast table array).
5776 */
5777 if (hw->phy.type == e1000_phy_i217) {
5778 u16 phy_reg;
5779
5780 ret_val = hw->phy.ops.acquire(hw);
5781 if (ret_val) {
5782 DEBUGOUT("Failed to setup iRST\n");
5783 return ret_val;
5784 }
5785
5786 /* Clear Auto Enable LPI after link up */
5787 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5788 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5789 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5790
5791 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5792 E1000_ICH_FWSM_FW_VALID)) {
5793 /* Restore clear on SMB if no manageability engine
5794 * is present
5795 */
5796 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5797 &phy_reg);
5798 if (ret_val)
5799 goto release;
5800 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5801 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5802
5803 /* Disable Proxy */
5804 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5805 }
5806 /* Enable reset on MTA */
5807 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5808 &phy_reg);
5809 if (ret_val)
5810 goto release;
5811 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5812 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5813 release:
5814 if (ret_val)
5815 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5816 hw->phy.ops.release(hw);
5817 return ret_val;
5818 }
5819 return E1000_SUCCESS;
5820 }
5821
5822 /**
5823 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5824 * @hw: pointer to the HW structure
5825 *
5826 * Return the LED back to the default configuration.
5827 **/
e1000_cleanup_led_ich8lan(struct e1000_hw * hw)5828 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5829 {
5830 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5831
5832 if (hw->phy.type == e1000_phy_ife)
5833 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5834 0);
5835
5836 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5837 return E1000_SUCCESS;
5838 }
5839
5840 /**
5841 * e1000_led_on_ich8lan - Turn LEDs on
5842 * @hw: pointer to the HW structure
5843 *
5844 * Turn on the LEDs.
5845 **/
e1000_led_on_ich8lan(struct e1000_hw * hw)5846 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5847 {
5848 DEBUGFUNC("e1000_led_on_ich8lan");
5849
5850 if (hw->phy.type == e1000_phy_ife)
5851 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5852 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5853
5854 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5855 return E1000_SUCCESS;
5856 }
5857
5858 /**
5859 * e1000_led_off_ich8lan - Turn LEDs off
5860 * @hw: pointer to the HW structure
5861 *
5862 * Turn off the LEDs.
5863 **/
e1000_led_off_ich8lan(struct e1000_hw * hw)5864 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5865 {
5866 DEBUGFUNC("e1000_led_off_ich8lan");
5867
5868 if (hw->phy.type == e1000_phy_ife)
5869 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5870 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5871
5872 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5873 return E1000_SUCCESS;
5874 }
5875
5876 /**
5877 * e1000_setup_led_pchlan - Configures SW controllable LED
5878 * @hw: pointer to the HW structure
5879 *
5880 * This prepares the SW controllable LED for use.
5881 **/
e1000_setup_led_pchlan(struct e1000_hw * hw)5882 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5883 {
5884 DEBUGFUNC("e1000_setup_led_pchlan");
5885
5886 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5887 (u16)hw->mac.ledctl_mode1);
5888 }
5889
5890 /**
5891 * e1000_cleanup_led_pchlan - Restore the default LED operation
5892 * @hw: pointer to the HW structure
5893 *
5894 * Return the LED back to the default configuration.
5895 **/
e1000_cleanup_led_pchlan(struct e1000_hw * hw)5896 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5897 {
5898 DEBUGFUNC("e1000_cleanup_led_pchlan");
5899
5900 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5901 (u16)hw->mac.ledctl_default);
5902 }
5903
5904 /**
5905 * e1000_led_on_pchlan - Turn LEDs on
5906 * @hw: pointer to the HW structure
5907 *
5908 * Turn on the LEDs.
5909 **/
e1000_led_on_pchlan(struct e1000_hw * hw)5910 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5911 {
5912 u16 data = (u16)hw->mac.ledctl_mode2;
5913 u32 i, led;
5914
5915 DEBUGFUNC("e1000_led_on_pchlan");
5916
5917 /* If no link, then turn LED on by setting the invert bit
5918 * for each LED that's mode is "link_up" in ledctl_mode2.
5919 */
5920 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5921 for (i = 0; i < 3; i++) {
5922 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5923 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5924 E1000_LEDCTL_MODE_LINK_UP)
5925 continue;
5926 if (led & E1000_PHY_LED0_IVRT)
5927 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5928 else
5929 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5930 }
5931 }
5932
5933 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5934 }
5935
5936 /**
5937 * e1000_led_off_pchlan - Turn LEDs off
5938 * @hw: pointer to the HW structure
5939 *
5940 * Turn off the LEDs.
5941 **/
e1000_led_off_pchlan(struct e1000_hw * hw)5942 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5943 {
5944 u16 data = (u16)hw->mac.ledctl_mode1;
5945 u32 i, led;
5946
5947 DEBUGFUNC("e1000_led_off_pchlan");
5948
5949 /* If no link, then turn LED off by clearing the invert bit
5950 * for each LED that's mode is "link_up" in ledctl_mode1.
5951 */
5952 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5953 for (i = 0; i < 3; i++) {
5954 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5955 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5956 E1000_LEDCTL_MODE_LINK_UP)
5957 continue;
5958 if (led & E1000_PHY_LED0_IVRT)
5959 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5960 else
5961 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5962 }
5963 }
5964
5965 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5966 }
5967
5968 /**
5969 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5970 * @hw: pointer to the HW structure
5971 *
5972 * Read appropriate register for the config done bit for completion status
5973 * and configure the PHY through s/w for EEPROM-less parts.
5974 *
5975 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5976 * config done bit, so only an error is logged and continues. If we were
5977 * to return with error, EEPROM-less silicon would not be able to be reset
5978 * or change link.
5979 **/
e1000_get_cfg_done_ich8lan(struct e1000_hw * hw)5980 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5981 {
5982 s32 ret_val = E1000_SUCCESS;
5983 u32 bank = 0;
5984 u32 status;
5985
5986 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5987
5988 e1000_get_cfg_done_generic(hw);
5989
5990 /* Wait for indication from h/w that it has completed basic config */
5991 if (hw->mac.type >= e1000_ich10lan) {
5992 e1000_lan_init_done_ich8lan(hw);
5993 } else {
5994 ret_val = e1000_get_auto_rd_done_generic(hw);
5995 if (ret_val) {
5996 /* When auto config read does not complete, do not
5997 * return with an error. This can happen in situations
5998 * where there is no eeprom and prevents getting link.
5999 */
6000 DEBUGOUT("Auto Read Done did not complete\n");
6001 ret_val = E1000_SUCCESS;
6002 }
6003 }
6004
6005 /* Clear PHY Reset Asserted bit */
6006 status = E1000_READ_REG(hw, E1000_STATUS);
6007 if (status & E1000_STATUS_PHYRA)
6008 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6009 else
6010 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
6011
6012 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
6013 if (hw->mac.type <= e1000_ich9lan) {
6014 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6015 (hw->phy.type == e1000_phy_igp_3)) {
6016 e1000_phy_init_script_igp3(hw);
6017 }
6018 } else {
6019 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6020 /* Maybe we should do a basic PHY config */
6021 DEBUGOUT("EEPROM not present\n");
6022 ret_val = -E1000_ERR_CONFIG;
6023 }
6024 }
6025
6026 return ret_val;
6027 }
6028
6029 /**
6030 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6031 * @hw: pointer to the HW structure
6032 *
6033 * In the case of a PHY power down to save power, or to turn off link during a
6034 * driver unload, or wake on lan is not enabled, remove the link.
6035 **/
e1000_power_down_phy_copper_ich8lan(struct e1000_hw * hw)6036 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6037 {
6038 /* If the management interface is not enabled, then power down */
6039 if (!(hw->mac.ops.check_mng_mode(hw) ||
6040 hw->phy.ops.check_reset_block(hw)))
6041 e1000_power_down_phy_copper(hw);
6042
6043 return;
6044 }
6045
6046 /**
6047 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6048 * @hw: pointer to the HW structure
6049 *
6050 * Clears hardware counters specific to the silicon family and calls
6051 * clear_hw_cntrs_generic to clear all general purpose counters.
6052 **/
e1000_clear_hw_cntrs_ich8lan(struct e1000_hw * hw)6053 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6054 {
6055 u16 phy_data;
6056 s32 ret_val;
6057
6058 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6059
6060 e1000_clear_hw_cntrs_base_generic(hw);
6061
6062 E1000_READ_REG(hw, E1000_ALGNERRC);
6063 E1000_READ_REG(hw, E1000_RXERRC);
6064 E1000_READ_REG(hw, E1000_TNCRS);
6065 E1000_READ_REG(hw, E1000_CEXTERR);
6066 E1000_READ_REG(hw, E1000_TSCTC);
6067 E1000_READ_REG(hw, E1000_TSCTFC);
6068
6069 E1000_READ_REG(hw, E1000_MGTPRC);
6070 E1000_READ_REG(hw, E1000_MGTPDC);
6071 E1000_READ_REG(hw, E1000_MGTPTC);
6072
6073 E1000_READ_REG(hw, E1000_IAC);
6074 E1000_READ_REG(hw, E1000_ICRXOC);
6075
6076 /* Clear PHY statistics registers */
6077 if ((hw->phy.type == e1000_phy_82578) ||
6078 (hw->phy.type == e1000_phy_82579) ||
6079 (hw->phy.type == e1000_phy_i217) ||
6080 (hw->phy.type == e1000_phy_82577)) {
6081 ret_val = hw->phy.ops.acquire(hw);
6082 if (ret_val)
6083 return;
6084 ret_val = hw->phy.ops.set_page(hw,
6085 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6086 if (ret_val)
6087 goto release;
6088 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6089 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6090 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6091 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6092 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6093 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6094 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6095 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6096 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6097 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6098 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6099 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6100 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6101 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6102 release:
6103 hw->phy.ops.release(hw);
6104 }
6105 }
6106
6107