1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 /*
6 * 82575EB Gigabit Network Connection
7 * 82575EB Gigabit Backplane Connection
8 * 82575GB Gigabit Network Connection
9 * 82576 Gigabit Network Connection
10 * 82576 Quad Port Gigabit Mezzanine Adapter
11 * 82580 Gigabit Network Connection
12 * I350 Gigabit Network Connection
13 */
14
15 #include "e1000_api.h"
16 #include "e1000_i210.h"
17
18 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
19 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
20 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
21 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
22 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
23 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
24 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
25 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
26 u16 *duplex);
27 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
28 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
29 u16 *data);
30 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
31 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw);
32 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
33 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
34 u32 offset, u16 *data);
35 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
36 u32 offset, u16 data);
37 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
38 bool active);
39 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
40 bool active);
41 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
42 bool active);
43 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
44 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
45 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
46 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
47 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
48 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
49 u32 offset, u16 data);
50 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
52 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
53 u16 *speed, u16 *duplex);
54 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
55 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
56 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
57 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
58 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
59 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
60 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
61 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
62 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
63 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
64 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
65 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
66 u16 offset);
67 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
68 u16 offset);
69 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
70 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
71 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
72
73 STATIC void e1000_i2c_start(struct e1000_hw *hw);
74 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
75 STATIC void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
76 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
77 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
78 STATIC void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
79 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
80 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
81 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
82 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
83 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
84
85 STATIC const u16 e1000_82580_rxpbs_table[] = {
86 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
87 #define E1000_82580_RXPBS_TABLE_SIZE \
88 (sizeof(e1000_82580_rxpbs_table) / \
89 sizeof(e1000_82580_rxpbs_table[0]))
90
91
92 /**
93 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
94 * @hw: pointer to the HW structure
95 *
96 * Called to determine if the I2C pins are being used for I2C or as an
97 * external MDIO interface since the two options are mutually exclusive.
98 **/
e1000_sgmii_uses_mdio_82575(struct e1000_hw * hw)99 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
100 {
101 u32 reg = 0;
102 bool ext_mdio = false;
103
104 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
105
106 switch (hw->mac.type) {
107 case e1000_82575:
108 case e1000_82576:
109 reg = E1000_READ_REG(hw, E1000_MDIC);
110 ext_mdio = !!(reg & E1000_MDIC_DEST);
111 break;
112 case e1000_82580:
113 case e1000_i350:
114 case e1000_i354:
115 case e1000_i210:
116 case e1000_i211:
117 reg = E1000_READ_REG(hw, E1000_MDICNFG);
118 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
119 break;
120 default:
121 break;
122 }
123 return ext_mdio;
124 }
125
126 /**
127 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
128 * @hw: pointer to the HW structure
129 **/
e1000_init_phy_params_82575(struct e1000_hw * hw)130 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
131 {
132 struct e1000_phy_info *phy = &hw->phy;
133 s32 ret_val = E1000_SUCCESS;
134 u32 ctrl_ext;
135
136 DEBUGFUNC("e1000_init_phy_params_82575");
137
138 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
139 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
140
141 if (hw->phy.media_type != e1000_media_type_copper) {
142 phy->type = e1000_phy_none;
143 goto out;
144 }
145
146 phy->ops.power_up = e1000_power_up_phy_copper;
147 phy->ops.power_down = e1000_power_down_phy_copper_base;
148
149 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
150 phy->reset_delay_us = 100;
151
152 phy->ops.acquire = e1000_acquire_phy_base;
153 phy->ops.check_reset_block = e1000_check_reset_block_generic;
154 phy->ops.commit = e1000_phy_sw_reset_generic;
155 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
156 phy->ops.release = e1000_release_phy_base;
157
158 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
159
160 if (e1000_sgmii_active_82575(hw)) {
161 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
162 ctrl_ext |= E1000_CTRL_I2C_ENA;
163 } else {
164 phy->ops.reset = e1000_phy_hw_reset_generic;
165 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
166 }
167
168 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
169 e1000_reset_mdicnfg_82580(hw);
170
171 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
172 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
173 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
174 } else {
175 switch (hw->mac.type) {
176 case e1000_82580:
177 case e1000_i350:
178 case e1000_i354:
179 phy->ops.read_reg = e1000_read_phy_reg_82580;
180 phy->ops.write_reg = e1000_write_phy_reg_82580;
181 break;
182 case e1000_i210:
183 case e1000_i211:
184 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
185 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
186 break;
187 default:
188 phy->ops.read_reg = e1000_read_phy_reg_igp;
189 phy->ops.write_reg = e1000_write_phy_reg_igp;
190 }
191 }
192
193 /* Set phy->phy_addr and phy->id. */
194 ret_val = e1000_get_phy_id_82575(hw);
195
196 /* Verify phy id and set remaining function pointers */
197 switch (phy->id) {
198 case M88E1543_E_PHY_ID:
199 case M88E1512_E_PHY_ID:
200 case I347AT4_E_PHY_ID:
201 case M88E1112_E_PHY_ID:
202 case M88E1340M_E_PHY_ID:
203 phy->type = e1000_phy_m88;
204 phy->ops.check_polarity = e1000_check_polarity_m88;
205 phy->ops.get_info = e1000_get_phy_info_m88;
206 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
207 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
208 break;
209 case M88E1111_I_PHY_ID:
210 phy->type = e1000_phy_m88;
211 phy->ops.check_polarity = e1000_check_polarity_m88;
212 phy->ops.get_info = e1000_get_phy_info_m88;
213 phy->ops.get_cable_length = e1000_get_cable_length_m88;
214 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
215 break;
216 case IGP03E1000_E_PHY_ID:
217 case IGP04E1000_E_PHY_ID:
218 phy->type = e1000_phy_igp_3;
219 phy->ops.check_polarity = e1000_check_polarity_igp;
220 phy->ops.get_info = e1000_get_phy_info_igp;
221 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
222 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
223 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
224 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
225 break;
226 case I82580_I_PHY_ID:
227 case I350_I_PHY_ID:
228 phy->type = e1000_phy_82580;
229 phy->ops.check_polarity = e1000_check_polarity_82577;
230 phy->ops.get_info = e1000_get_phy_info_82577;
231 phy->ops.get_cable_length = e1000_get_cable_length_82577;
232 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
233 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
234 phy->ops.force_speed_duplex =
235 e1000_phy_force_speed_duplex_82577;
236 break;
237 case I210_I_PHY_ID:
238 phy->type = e1000_phy_i210;
239 phy->ops.check_polarity = e1000_check_polarity_m88;
240 phy->ops.get_info = e1000_get_phy_info_m88;
241 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
242 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
243 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
244 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
245 break;
246 case BCM54616_E_PHY_ID:
247 phy->type = e1000_phy_none;
248 break;
249 default:
250 ret_val = -E1000_ERR_PHY;
251 goto out;
252 }
253
254 /* Check if this PHY is configured for media swap. */
255 switch (phy->id) {
256 case M88E1112_E_PHY_ID:
257 {
258 u16 data;
259
260 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
261 if (ret_val)
262 goto out;
263 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
264 &data);
265 if (ret_val)
266 goto out;
267
268 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
269 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
270 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
271 data == E1000_M88E1112_AUTO_COPPER_BASEX)
272 hw->mac.ops.check_for_link =
273 e1000_check_for_link_media_swap;
274 break;
275 }
276 case M88E1512_E_PHY_ID:
277 {
278 ret_val = e1000_initialize_M88E1512_phy(hw);
279 break;
280 }
281 case M88E1543_E_PHY_ID:
282 {
283 ret_val = e1000_initialize_M88E1543_phy(hw);
284 break;
285 }
286 default:
287 goto out;
288 }
289
290 out:
291 return ret_val;
292 }
293
294 /**
295 * e1000_init_mac_params_82575 - Initialize MAC function ptrs
296 * @hw: pointer to the HW structure
297 **/
e1000_init_mac_params_82575(struct e1000_hw * hw)298 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
299 {
300 struct e1000_mac_info *mac = &hw->mac;
301 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
302
303 DEBUGFUNC("e1000_init_mac_params_82575");
304
305 /* Initialize function pointer */
306 e1000_init_mac_ops_generic(hw);
307
308 /* Derives media type */
309 e1000_get_media_type_82575(hw);
310 /* Set MTA register count */
311 mac->mta_reg_count = 128;
312 /* Set UTA register count */
313 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
314 /* Set RAR entry count */
315 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
316 if (mac->type == e1000_82576)
317 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
318 if (mac->type == e1000_82580)
319 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
320 if (mac->type == e1000_i350 || mac->type == e1000_i354)
321 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
322
323 /* Enable EEE default settings for EEE supported devices */
324 if (mac->type >= e1000_i350)
325 dev_spec->eee_disable = false;
326
327 /* Allow a single clear of the SW semaphore on I210 and newer */
328 if (mac->type >= e1000_i210)
329 dev_spec->clear_semaphore_once = true;
330
331 /* Set if part includes ASF firmware */
332 mac->asf_firmware_present = true;
333 /* FWSM register */
334 mac->has_fwsm = true;
335 /* ARC supported; valid only if manageability features are enabled. */
336 mac->arc_subsystem_valid =
337 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
338
339 /* Function pointers */
340
341 /* bus type/speed/width */
342 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
343 /* reset */
344 if (mac->type >= e1000_82580)
345 mac->ops.reset_hw = e1000_reset_hw_82580;
346 else
347 mac->ops.reset_hw = e1000_reset_hw_82575;
348 /* HW initialization */
349 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
350 mac->ops.init_hw = e1000_init_hw_i210;
351 else
352 mac->ops.init_hw = e1000_init_hw_82575;
353 /* link setup */
354 mac->ops.setup_link = e1000_setup_link_generic;
355 /* physical interface link setup */
356 mac->ops.setup_physical_interface =
357 (hw->phy.media_type == e1000_media_type_copper)
358 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
359 /* physical interface shutdown */
360 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
361 /* physical interface power up */
362 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
363 /* check for link */
364 mac->ops.check_for_link = e1000_check_for_link_82575;
365 /* read mac address */
366 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
367 /* configure collision distance */
368 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
369 /* multicast address update */
370 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
371 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
372 /* writing VFTA */
373 mac->ops.write_vfta = e1000_write_vfta_i350;
374 /* clearing VFTA */
375 mac->ops.clear_vfta = e1000_clear_vfta_i350;
376 } else {
377 /* writing VFTA */
378 mac->ops.write_vfta = e1000_write_vfta_generic;
379 /* clearing VFTA */
380 mac->ops.clear_vfta = e1000_clear_vfta_generic;
381 }
382 if (hw->mac.type >= e1000_82580)
383 mac->ops.validate_mdi_setting =
384 e1000_validate_mdi_setting_crossover_generic;
385 /* ID LED init */
386 mac->ops.id_led_init = e1000_id_led_init_generic;
387 /* blink LED */
388 mac->ops.blink_led = e1000_blink_led_generic;
389 /* setup LED */
390 mac->ops.setup_led = e1000_setup_led_generic;
391 /* cleanup LED */
392 mac->ops.cleanup_led = e1000_cleanup_led_generic;
393 /* turn on/off LED */
394 mac->ops.led_on = e1000_led_on_generic;
395 mac->ops.led_off = e1000_led_off_generic;
396 /* clear hardware counters */
397 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
398 /* link info */
399 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
400 /* acquire SW_FW sync */
401 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
402 /* release SW_FW sync */
403 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
404 if (mac->type == e1000_i210 || mac->type == e1000_i211) {
405 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
406 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
407 }
408
409 /* set lan id for port to determine which phy lock to use */
410 hw->mac.ops.set_lan_id(hw);
411
412 return E1000_SUCCESS;
413 }
414
415 /**
416 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs
417 * @hw: pointer to the HW structure
418 **/
e1000_init_nvm_params_82575(struct e1000_hw * hw)419 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
420 {
421 struct e1000_nvm_info *nvm = &hw->nvm;
422 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
423 u16 size;
424
425 DEBUGFUNC("e1000_init_nvm_params_82575");
426
427 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
428 E1000_EECD_SIZE_EX_SHIFT);
429 /* Added to a constant, "size" becomes the left-shift value
430 * for setting word_size.
431 */
432 size += NVM_WORD_SIZE_BASE_SHIFT;
433
434 /* Just in case size is out of range, cap it to the largest
435 * EEPROM size supported
436 */
437 if (size > 15)
438 size = 15;
439
440 nvm->word_size = 1 << size;
441 if (hw->mac.type < e1000_i210) {
442 nvm->opcode_bits = 8;
443 nvm->delay_usec = 1;
444
445 switch (nvm->override) {
446 case e1000_nvm_override_spi_large:
447 nvm->page_size = 32;
448 nvm->address_bits = 16;
449 break;
450 case e1000_nvm_override_spi_small:
451 nvm->page_size = 8;
452 nvm->address_bits = 8;
453 break;
454 default:
455 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
456 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
457 16 : 8;
458 break;
459 }
460 if (nvm->word_size == (1 << 15))
461 nvm->page_size = 128;
462
463 nvm->type = e1000_nvm_eeprom_spi;
464 } else {
465 nvm->type = e1000_nvm_flash_hw;
466 }
467
468 /* Function Pointers */
469 nvm->ops.acquire = e1000_acquire_nvm_82575;
470 nvm->ops.release = e1000_release_nvm_82575;
471 if (nvm->word_size < (1 << 15))
472 nvm->ops.read = e1000_read_nvm_eerd;
473 else
474 nvm->ops.read = e1000_read_nvm_spi;
475
476 nvm->ops.write = e1000_write_nvm_spi;
477 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
478 nvm->ops.update = e1000_update_nvm_checksum_generic;
479 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
480
481 /* override generic family function pointers for specific descendants */
482 switch (hw->mac.type) {
483 case e1000_82580:
484 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
485 nvm->ops.update = e1000_update_nvm_checksum_82580;
486 break;
487 case e1000_i350:
488 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
489 nvm->ops.update = e1000_update_nvm_checksum_i350;
490 break;
491 default:
492 break;
493 }
494
495 return E1000_SUCCESS;
496 }
497
498 /**
499 * e1000_init_function_pointers_82575 - Init func ptrs.
500 * @hw: pointer to the HW structure
501 *
502 * Called to initialize all function pointers and parameters.
503 **/
e1000_init_function_pointers_82575(struct e1000_hw * hw)504 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
505 {
506 DEBUGFUNC("e1000_init_function_pointers_82575");
507
508 hw->mac.ops.init_params = e1000_init_mac_params_82575;
509 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
510 hw->phy.ops.init_params = e1000_init_phy_params_82575;
511 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
512 }
513
514 /**
515 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
516 * @hw: pointer to the HW structure
517 * @offset: register offset to be read
518 * @data: pointer to the read data
519 *
520 * Reads the PHY register at offset using the serial gigabit media independent
521 * interface and stores the retrieved information in data.
522 **/
e1000_read_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 * data)523 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
524 u16 *data)
525 {
526 s32 ret_val = -E1000_ERR_PARAM;
527
528 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
529
530 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
531 DEBUGOUT1("PHY Address %u is out of range\n", offset);
532 goto out;
533 }
534
535 ret_val = hw->phy.ops.acquire(hw);
536 if (ret_val)
537 goto out;
538
539 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
540
541 hw->phy.ops.release(hw);
542
543 out:
544 return ret_val;
545 }
546
547 /**
548 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
549 * @hw: pointer to the HW structure
550 * @offset: register offset to write to
551 * @data: data to write at register offset
552 *
553 * Writes the data to PHY register at the offset using the serial gigabit
554 * media independent interface.
555 **/
e1000_write_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 data)556 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
557 u16 data)
558 {
559 s32 ret_val = -E1000_ERR_PARAM;
560
561 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
562
563 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
564 DEBUGOUT1("PHY Address %d is out of range\n", offset);
565 goto out;
566 }
567
568 ret_val = hw->phy.ops.acquire(hw);
569 if (ret_val)
570 goto out;
571
572 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
573
574 hw->phy.ops.release(hw);
575
576 out:
577 return ret_val;
578 }
579
580 /**
581 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
582 * @hw: pointer to the HW structure
583 *
584 * Retrieves the PHY address and ID for both PHY's which do and do not use
585 * sgmi interface.
586 **/
e1000_get_phy_id_82575(struct e1000_hw * hw)587 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
588 {
589 struct e1000_phy_info *phy = &hw->phy;
590 s32 ret_val = E1000_SUCCESS;
591 u16 phy_id;
592 u32 ctrl_ext;
593 u32 mdic;
594
595 DEBUGFUNC("e1000_get_phy_id_82575");
596
597 /* some i354 devices need an extra read for phy id */
598 if (hw->mac.type == e1000_i354)
599 e1000_get_phy_id(hw);
600
601 /*
602 * For SGMII PHYs, we try the list of possible addresses until
603 * we find one that works. For non-SGMII PHYs
604 * (e.g. integrated copper PHYs), an address of 1 should
605 * work. The result of this function should mean phy->phy_addr
606 * and phy->id are set correctly.
607 */
608 if (!e1000_sgmii_active_82575(hw)) {
609 phy->addr = 1;
610 ret_val = e1000_get_phy_id(hw);
611 goto out;
612 }
613
614 if (e1000_sgmii_uses_mdio_82575(hw)) {
615 switch (hw->mac.type) {
616 case e1000_82575:
617 case e1000_82576:
618 mdic = E1000_READ_REG(hw, E1000_MDIC);
619 mdic &= E1000_MDIC_PHY_MASK;
620 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
621 break;
622 case e1000_82580:
623 case e1000_i350:
624 case e1000_i354:
625 case e1000_i210:
626 case e1000_i211:
627 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
628 mdic &= E1000_MDICNFG_PHY_MASK;
629 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
630 break;
631 default:
632 ret_val = -E1000_ERR_PHY;
633 goto out;
634 break;
635 }
636 ret_val = e1000_get_phy_id(hw);
637 goto out;
638 }
639
640 /* Power on sgmii phy if it is disabled */
641 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
642 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
643 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
644 E1000_WRITE_FLUSH(hw);
645 msec_delay(300);
646
647 /*
648 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
649 * Therefore, we need to test 1-7
650 */
651 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
652 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
653 if (ret_val == E1000_SUCCESS) {
654 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
655 phy_id, phy->addr);
656 /*
657 * At the time of this writing, The M88 part is
658 * the only supported SGMII PHY product.
659 */
660 if (phy_id == M88_VENDOR)
661 break;
662 } else {
663 DEBUGOUT1("PHY address %u was unreadable\n",
664 phy->addr);
665 }
666 }
667
668 /* A valid PHY type couldn't be found. */
669 if (phy->addr == 8) {
670 phy->addr = 0;
671 ret_val = -E1000_ERR_PHY;
672 } else {
673 ret_val = e1000_get_phy_id(hw);
674 }
675
676 /* restore previous sfp cage power state */
677 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
678
679 out:
680 return ret_val;
681 }
682
683 /**
684 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
685 * @hw: pointer to the HW structure
686 *
687 * Resets the PHY using the serial gigabit media independent interface.
688 **/
e1000_phy_hw_reset_sgmii_82575(struct e1000_hw * hw)689 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
690 {
691 s32 ret_val = E1000_SUCCESS;
692 struct e1000_phy_info *phy = &hw->phy;
693
694 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
695
696 /*
697 * This isn't a true "hard" reset, but is the only reset
698 * available to us at this time.
699 */
700
701 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
702
703 if (!(hw->phy.ops.write_reg))
704 goto out;
705
706 /*
707 * SFP documentation requires the following to configure the SPF module
708 * to work on SGMII. No further documentation is given.
709 */
710 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
711 if (ret_val)
712 goto out;
713
714 ret_val = hw->phy.ops.commit(hw);
715 if (ret_val)
716 goto out;
717
718 if (phy->id == M88E1512_E_PHY_ID)
719 ret_val = e1000_initialize_M88E1512_phy(hw);
720 out:
721 return ret_val;
722 }
723
724 /**
725 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
726 * @hw: pointer to the HW structure
727 * @active: true to enable LPLU, false to disable
728 *
729 * Sets the LPLU D0 state according to the active flag. When
730 * activating LPLU this function also disables smart speed
731 * and vice versa. LPLU will not be activated unless the
732 * device autonegotiation advertisement meets standards of
733 * either 10 or 10/100 or 10/100/1000 at all duplexes.
734 * This is a function pointer entry point only called by
735 * PHY setup routines.
736 **/
e1000_set_d0_lplu_state_82575(struct e1000_hw * hw,bool active)737 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
738 {
739 struct e1000_phy_info *phy = &hw->phy;
740 s32 ret_val = E1000_SUCCESS;
741 u16 data;
742
743 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
744
745 if (!(hw->phy.ops.read_reg))
746 goto out;
747
748 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
749 if (ret_val)
750 goto out;
751
752 if (active) {
753 data |= IGP02E1000_PM_D0_LPLU;
754 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
755 data);
756 if (ret_val)
757 goto out;
758
759 /* When LPLU is enabled, we should disable SmartSpeed */
760 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
761 &data);
762 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
763 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
764 data);
765 if (ret_val)
766 goto out;
767 } else {
768 data &= ~IGP02E1000_PM_D0_LPLU;
769 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
770 data);
771 /*
772 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
773 * during Dx states where the power conservation is most
774 * important. During driver activity we should enable
775 * SmartSpeed, so performance is maintained.
776 */
777 if (phy->smart_speed == e1000_smart_speed_on) {
778 ret_val = phy->ops.read_reg(hw,
779 IGP01E1000_PHY_PORT_CONFIG,
780 &data);
781 if (ret_val)
782 goto out;
783
784 data |= IGP01E1000_PSCFR_SMART_SPEED;
785 ret_val = phy->ops.write_reg(hw,
786 IGP01E1000_PHY_PORT_CONFIG,
787 data);
788 if (ret_val)
789 goto out;
790 } else if (phy->smart_speed == e1000_smart_speed_off) {
791 ret_val = phy->ops.read_reg(hw,
792 IGP01E1000_PHY_PORT_CONFIG,
793 &data);
794 if (ret_val)
795 goto out;
796
797 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
798 ret_val = phy->ops.write_reg(hw,
799 IGP01E1000_PHY_PORT_CONFIG,
800 data);
801 if (ret_val)
802 goto out;
803 }
804 }
805
806 out:
807 return ret_val;
808 }
809
810 /**
811 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
812 * @hw: pointer to the HW structure
813 * @active: true to enable LPLU, false to disable
814 *
815 * Sets the LPLU D0 state according to the active flag. When
816 * activating LPLU this function also disables smart speed
817 * and vice versa. LPLU will not be activated unless the
818 * device autonegotiation advertisement meets standards of
819 * either 10 or 10/100 or 10/100/1000 at all duplexes.
820 * This is a function pointer entry point only called by
821 * PHY setup routines.
822 **/
e1000_set_d0_lplu_state_82580(struct e1000_hw * hw,bool active)823 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
824 {
825 struct e1000_phy_info *phy = &hw->phy;
826 u32 data;
827
828 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
829
830 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
831
832 if (active) {
833 data |= E1000_82580_PM_D0_LPLU;
834
835 /* When LPLU is enabled, we should disable SmartSpeed */
836 data &= ~E1000_82580_PM_SPD;
837 } else {
838 data &= ~E1000_82580_PM_D0_LPLU;
839
840 /*
841 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
842 * during Dx states where the power conservation is most
843 * important. During driver activity we should enable
844 * SmartSpeed, so performance is maintained.
845 */
846 if (phy->smart_speed == e1000_smart_speed_on)
847 data |= E1000_82580_PM_SPD;
848 else if (phy->smart_speed == e1000_smart_speed_off)
849 data &= ~E1000_82580_PM_SPD;
850 }
851
852 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
853 return E1000_SUCCESS;
854 }
855
856 /**
857 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
858 * @hw: pointer to the HW structure
859 * @active: boolean used to enable/disable lplu
860 *
861 * Success returns 0, Failure returns 1
862 *
863 * The low power link up (lplu) state is set to the power management level D3
864 * and SmartSpeed is disabled when active is true, else clear lplu for D3
865 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
866 * is used during Dx states where the power conservation is most important.
867 * During driver activity, SmartSpeed should be enabled so performance is
868 * maintained.
869 **/
e1000_set_d3_lplu_state_82580(struct e1000_hw * hw,bool active)870 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
871 {
872 struct e1000_phy_info *phy = &hw->phy;
873 u32 data;
874
875 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
876
877 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
878
879 if (!active) {
880 data &= ~E1000_82580_PM_D3_LPLU;
881 /*
882 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
883 * during Dx states where the power conservation is most
884 * important. During driver activity we should enable
885 * SmartSpeed, so performance is maintained.
886 */
887 if (phy->smart_speed == e1000_smart_speed_on)
888 data |= E1000_82580_PM_SPD;
889 else if (phy->smart_speed == e1000_smart_speed_off)
890 data &= ~E1000_82580_PM_SPD;
891 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
892 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
893 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
894 data |= E1000_82580_PM_D3_LPLU;
895 /* When LPLU is enabled, we should disable SmartSpeed */
896 data &= ~E1000_82580_PM_SPD;
897 }
898
899 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
900 return E1000_SUCCESS;
901 }
902
903 /**
904 * e1000_acquire_nvm_82575 - Request for access to EEPROM
905 * @hw: pointer to the HW structure
906 *
907 * Acquire the necessary semaphores for exclusive access to the EEPROM.
908 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
909 * Return successful if access grant bit set, else clear the request for
910 * EEPROM access and return -E1000_ERR_NVM (-1).
911 **/
e1000_acquire_nvm_82575(struct e1000_hw * hw)912 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
913 {
914 s32 ret_val = E1000_SUCCESS;
915
916 DEBUGFUNC("e1000_acquire_nvm_82575");
917
918 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
919 if (ret_val)
920 goto out;
921
922 /*
923 * Check if there is some access
924 * error this access may hook on
925 */
926 if (hw->mac.type == e1000_i350) {
927 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
928 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
929 E1000_EECD_TIMEOUT)) {
930 /* Clear all access error flags */
931 E1000_WRITE_REG(hw, E1000_EECD, eecd |
932 E1000_EECD_ERROR_CLR);
933 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
934 }
935 }
936
937 if (hw->mac.type == e1000_82580) {
938 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
939 if (eecd & E1000_EECD_BLOCKED) {
940 /* Clear access error flag */
941 E1000_WRITE_REG(hw, E1000_EECD, eecd |
942 E1000_EECD_BLOCKED);
943 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
944 }
945 }
946
947 ret_val = e1000_acquire_nvm_generic(hw);
948 if (ret_val)
949 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
950
951 out:
952 return ret_val;
953 }
954
955 /**
956 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
957 * @hw: pointer to the HW structure
958 *
959 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
960 * then release the semaphores acquired.
961 **/
e1000_release_nvm_82575(struct e1000_hw * hw)962 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
963 {
964 DEBUGFUNC("e1000_release_nvm_82575");
965
966 e1000_release_nvm_generic(hw);
967
968 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
969 }
970
971 /**
972 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
973 * @hw: pointer to the HW structure
974 * @mask: specifies which semaphore to acquire
975 *
976 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
977 * will also specify which port we're acquiring the lock for.
978 **/
e1000_acquire_swfw_sync_82575(struct e1000_hw * hw,u16 mask)979 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
980 {
981 u32 swfw_sync;
982 u32 swmask = mask;
983 u32 fwmask = mask << 16;
984 s32 ret_val = E1000_SUCCESS;
985 s32 i = 0, timeout = 200;
986
987 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
988
989 while (i < timeout) {
990 if (e1000_get_hw_semaphore_generic(hw)) {
991 ret_val = -E1000_ERR_SWFW_SYNC;
992 goto out;
993 }
994
995 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
996 if (!(swfw_sync & (fwmask | swmask)))
997 break;
998
999 /*
1000 * Firmware currently using resource (fwmask)
1001 * or other software thread using resource (swmask)
1002 */
1003 e1000_put_hw_semaphore_generic(hw);
1004 msec_delay_irq(5);
1005 i++;
1006 }
1007
1008 if (i == timeout) {
1009 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1010 ret_val = -E1000_ERR_SWFW_SYNC;
1011 goto out;
1012 }
1013
1014 swfw_sync |= swmask;
1015 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1016
1017 e1000_put_hw_semaphore_generic(hw);
1018
1019 out:
1020 return ret_val;
1021 }
1022
1023 /**
1024 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1025 * @hw: pointer to the HW structure
1026 * @mask: specifies which semaphore to acquire
1027 *
1028 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1029 * will also specify which port we're releasing the lock for.
1030 **/
e1000_release_swfw_sync_82575(struct e1000_hw * hw,u16 mask)1031 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1032 {
1033 u32 swfw_sync;
1034
1035 DEBUGFUNC("e1000_release_swfw_sync_82575");
1036
1037 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1038 ; /* Empty */
1039
1040 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1041 swfw_sync &= (u32)~mask;
1042 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1043
1044 e1000_put_hw_semaphore_generic(hw);
1045 }
1046
1047 /**
1048 * e1000_get_cfg_done_82575 - Read config done bit
1049 * @hw: pointer to the HW structure
1050 *
1051 * Read the management control register for the config done bit for
1052 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1053 * to read the config done bit, so an error is *ONLY* logged and returns
1054 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1055 * would not be able to be reset or change link.
1056 **/
e1000_get_cfg_done_82575(struct e1000_hw * hw)1057 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1058 {
1059 s32 timeout = PHY_CFG_TIMEOUT;
1060 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1061
1062 DEBUGFUNC("e1000_get_cfg_done_82575");
1063
1064 if (hw->bus.func == E1000_FUNC_1)
1065 mask = E1000_NVM_CFG_DONE_PORT_1;
1066 else if (hw->bus.func == E1000_FUNC_2)
1067 mask = E1000_NVM_CFG_DONE_PORT_2;
1068 else if (hw->bus.func == E1000_FUNC_3)
1069 mask = E1000_NVM_CFG_DONE_PORT_3;
1070 while (timeout) {
1071 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1072 break;
1073 msec_delay(1);
1074 timeout--;
1075 }
1076 if (!timeout)
1077 DEBUGOUT("MNG configuration cycle has not completed.\n");
1078
1079 /* If EEPROM is not marked present, init the PHY manually */
1080 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1081 (hw->phy.type == e1000_phy_igp_3))
1082 e1000_phy_init_script_igp3(hw);
1083
1084 return E1000_SUCCESS;
1085 }
1086
1087 /**
1088 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1089 * @hw: pointer to the HW structure
1090 * @speed: stores the current speed
1091 * @duplex: stores the current duplex
1092 *
1093 * This is a wrapper function, if using the serial gigabit media independent
1094 * interface, use PCS to retrieve the link speed and duplex information.
1095 * Otherwise, use the generic function to get the link speed and duplex info.
1096 **/
e1000_get_link_up_info_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1097 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1098 u16 *duplex)
1099 {
1100 s32 ret_val;
1101
1102 DEBUGFUNC("e1000_get_link_up_info_82575");
1103
1104 if (hw->phy.media_type != e1000_media_type_copper)
1105 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1106 duplex);
1107 else
1108 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1109 duplex);
1110
1111 return ret_val;
1112 }
1113
1114 /**
1115 * e1000_check_for_link_82575 - Check for link
1116 * @hw: pointer to the HW structure
1117 *
1118 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1119 * use the generic interface for determining link.
1120 **/
e1000_check_for_link_82575(struct e1000_hw * hw)1121 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1122 {
1123 s32 ret_val;
1124 u16 speed, duplex;
1125
1126 DEBUGFUNC("e1000_check_for_link_82575");
1127
1128 if (hw->phy.media_type != e1000_media_type_copper) {
1129 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1130 &duplex);
1131 /*
1132 * Use this flag to determine if link needs to be checked or
1133 * not. If we have link clear the flag so that we do not
1134 * continue to check for link.
1135 */
1136 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1137
1138 /*
1139 * Configure Flow Control now that Auto-Neg has completed.
1140 * First, we need to restore the desired flow control
1141 * settings because we may have had to re-autoneg with a
1142 * different link partner.
1143 */
1144 ret_val = e1000_config_fc_after_link_up_generic(hw);
1145 if (ret_val)
1146 DEBUGOUT("Error configuring flow control\n");
1147 } else {
1148 ret_val = e1000_check_for_copper_link_generic(hw);
1149 }
1150
1151 return ret_val;
1152 }
1153
1154 /**
1155 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1156 * @hw: pointer to the HW structure
1157 *
1158 * Poll the M88E1112 interfaces to see which interface achieved link.
1159 */
e1000_check_for_link_media_swap(struct e1000_hw * hw)1160 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1161 {
1162 struct e1000_phy_info *phy = &hw->phy;
1163 s32 ret_val;
1164 u16 data;
1165 u8 port = 0;
1166
1167 DEBUGFUNC("e1000_check_for_link_media_swap");
1168
1169 /* Check for copper. */
1170 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1171 if (ret_val)
1172 return ret_val;
1173
1174 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1175 if (ret_val)
1176 return ret_val;
1177
1178 if (data & E1000_M88E1112_STATUS_LINK)
1179 port = E1000_MEDIA_PORT_COPPER;
1180
1181 /* Check for other. */
1182 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1183 if (ret_val)
1184 return ret_val;
1185
1186 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1187 if (ret_val)
1188 return ret_val;
1189
1190 if (data & E1000_M88E1112_STATUS_LINK)
1191 port = E1000_MEDIA_PORT_OTHER;
1192
1193 /* Determine if a swap needs to happen. */
1194 if (port && (hw->dev_spec._82575.media_port != port)) {
1195 hw->dev_spec._82575.media_port = port;
1196 hw->dev_spec._82575.media_changed = true;
1197 }
1198
1199 if (port == E1000_MEDIA_PORT_COPPER) {
1200 /* reset page to 0 */
1201 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1202 if (ret_val)
1203 return ret_val;
1204 e1000_check_for_link_82575(hw);
1205 } else {
1206 e1000_check_for_link_82575(hw);
1207 /* reset page to 0 */
1208 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1209 if (ret_val)
1210 return ret_val;
1211 }
1212
1213 return E1000_SUCCESS;
1214 }
1215
1216 /**
1217 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1218 * @hw: pointer to the HW structure
1219 **/
e1000_power_up_serdes_link_82575(struct e1000_hw * hw)1220 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1221 {
1222 u32 reg;
1223
1224 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1225
1226 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1227 !e1000_sgmii_active_82575(hw))
1228 return;
1229
1230 /* Enable PCS to turn on link */
1231 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1232 reg |= E1000_PCS_CFG_PCS_EN;
1233 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1234
1235 /* Power up the laser */
1236 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1237 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1238 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1239
1240 /* flush the write to verify completion */
1241 E1000_WRITE_FLUSH(hw);
1242 msec_delay(1);
1243 }
1244
1245 /**
1246 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1247 * @hw: pointer to the HW structure
1248 * @speed: stores the current speed
1249 * @duplex: stores the current duplex
1250 *
1251 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1252 * duplex, then store the values in the pointers provided.
1253 **/
e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1254 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1255 u16 *speed, u16 *duplex)
1256 {
1257 struct e1000_mac_info *mac = &hw->mac;
1258 u32 pcs;
1259 u32 status;
1260
1261 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1262
1263 /*
1264 * Read the PCS Status register for link state. For non-copper mode,
1265 * the status register is not accurate. The PCS status register is
1266 * used instead.
1267 */
1268 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1269
1270 /*
1271 * The link up bit determines when link is up on autoneg.
1272 */
1273 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1274 mac->serdes_has_link = true;
1275
1276 /* Detect and store PCS speed */
1277 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1278 *speed = SPEED_1000;
1279 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1280 *speed = SPEED_100;
1281 else
1282 *speed = SPEED_10;
1283
1284 /* Detect and store PCS duplex */
1285 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1286 *duplex = FULL_DUPLEX;
1287 else
1288 *duplex = HALF_DUPLEX;
1289
1290 /* Check if it is an I354 2.5Gb backplane connection. */
1291 if (mac->type == e1000_i354) {
1292 status = E1000_READ_REG(hw, E1000_STATUS);
1293 if ((status & E1000_STATUS_2P5_SKU) &&
1294 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1295 *speed = SPEED_2500;
1296 *duplex = FULL_DUPLEX;
1297 DEBUGOUT("2500 Mbs, ");
1298 DEBUGOUT("Full Duplex\n");
1299 }
1300 }
1301
1302 } else {
1303 mac->serdes_has_link = false;
1304 *speed = 0;
1305 *duplex = 0;
1306 }
1307
1308 return E1000_SUCCESS;
1309 }
1310
1311 /**
1312 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1313 * @hw: pointer to the HW structure
1314 *
1315 * In the case of serdes shut down sfp and PCS on driver unload
1316 * when management pass thru is not enabled.
1317 **/
e1000_shutdown_serdes_link_82575(struct e1000_hw * hw)1318 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1319 {
1320 u32 reg;
1321
1322 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1323
1324 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1325 !e1000_sgmii_active_82575(hw))
1326 return;
1327
1328 if (!e1000_enable_mng_pass_thru(hw)) {
1329 /* Disable PCS to turn off link */
1330 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1331 reg &= ~E1000_PCS_CFG_PCS_EN;
1332 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1333
1334 /* shutdown the laser */
1335 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1336 reg |= E1000_CTRL_EXT_SDP3_DATA;
1337 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1338
1339 /* flush the write to verify completion */
1340 E1000_WRITE_FLUSH(hw);
1341 msec_delay(1);
1342 }
1343
1344 return;
1345 }
1346
1347 /**
1348 * e1000_reset_hw_82575 - Reset hardware
1349 * @hw: pointer to the HW structure
1350 *
1351 * This resets the hardware into a known state.
1352 **/
e1000_reset_hw_82575(struct e1000_hw * hw)1353 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1354 {
1355 u32 ctrl;
1356 s32 ret_val;
1357
1358 DEBUGFUNC("e1000_reset_hw_82575");
1359
1360 /*
1361 * Prevent the PCI-E bus from sticking if there is no TLP connection
1362 * on the last TLP read/write transaction when MAC is reset.
1363 */
1364 ret_val = e1000_disable_pcie_master_generic(hw);
1365 if (ret_val)
1366 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1367
1368 /* set the completion timeout for interface */
1369 ret_val = e1000_set_pcie_completion_timeout(hw);
1370 if (ret_val)
1371 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1372
1373 DEBUGOUT("Masking off all interrupts\n");
1374 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1375
1376 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1377 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1378 E1000_WRITE_FLUSH(hw);
1379
1380 msec_delay(10);
1381
1382 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1383
1384 DEBUGOUT("Issuing a global reset to MAC\n");
1385 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1386
1387 ret_val = e1000_get_auto_rd_done_generic(hw);
1388 if (ret_val) {
1389 /*
1390 * When auto config read does not complete, do not
1391 * return with an error. This can happen in situations
1392 * where there is no eeprom and prevents getting link.
1393 */
1394 DEBUGOUT("Auto Read Done did not complete\n");
1395 }
1396
1397 /* If EEPROM is not present, run manual init scripts */
1398 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1399 e1000_reset_init_script_82575(hw);
1400
1401 /* Clear any pending interrupt events. */
1402 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1403 E1000_READ_REG(hw, E1000_ICR);
1404
1405 /* Install any alternate MAC address into RAR0 */
1406 ret_val = e1000_check_alt_mac_addr_generic(hw);
1407
1408 return ret_val;
1409 }
1410
1411 /**
1412 * e1000_init_hw_82575 - Initialize hardware
1413 * @hw: pointer to the HW structure
1414 *
1415 * This inits the hardware readying it for operation.
1416 **/
e1000_init_hw_82575(struct e1000_hw * hw)1417 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1418 {
1419 struct e1000_mac_info *mac = &hw->mac;
1420 s32 ret_val;
1421
1422 DEBUGFUNC("e1000_init_hw_82575");
1423
1424 /* Initialize identification LED */
1425 ret_val = mac->ops.id_led_init(hw);
1426 if (ret_val) {
1427 DEBUGOUT("Error initializing identification LED\n");
1428 /* This is not fatal and we should not stop init due to this */
1429 }
1430
1431 /* Disabling VLAN filtering */
1432 DEBUGOUT("Initializing the IEEE VLAN\n");
1433 mac->ops.clear_vfta(hw);
1434
1435 ret_val = e1000_init_hw_base(hw);
1436
1437 /* Set the default MTU size */
1438 hw->dev_spec._82575.mtu = 1500;
1439
1440 /* Clear all of the statistics registers (clear on read). It is
1441 * important that we do this after we have tried to establish link
1442 * because the symbol error count will increment wildly if there
1443 * is no link.
1444 */
1445 e1000_clear_hw_cntrs_82575(hw);
1446
1447 return ret_val;
1448 }
1449 /**
1450 * e1000_setup_copper_link_82575 - Configure copper link settings
1451 * @hw: pointer to the HW structure
1452 *
1453 * Configures the link for auto-neg or forced speed and duplex. Then we check
1454 * for link, once link is established calls to configure collision distance
1455 * and flow control are called.
1456 **/
e1000_setup_copper_link_82575(struct e1000_hw * hw)1457 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1458 {
1459 u32 phpm_reg;
1460 s32 ret_val;
1461 u32 ctrl;
1462
1463 DEBUGFUNC("e1000_setup_copper_link_82575");
1464
1465 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1466 ctrl |= E1000_CTRL_SLU;
1467 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1468 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1469
1470 /* Clear Go Link Disconnect bit on supported devices */
1471 switch (hw->mac.type) {
1472 case e1000_82580:
1473 case e1000_i350:
1474 case e1000_i210:
1475 case e1000_i211:
1476 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1477 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1478 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1479 break;
1480 default:
1481 break;
1482 }
1483
1484 ret_val = e1000_setup_serdes_link_82575(hw);
1485 if (ret_val)
1486 goto out;
1487
1488 if (e1000_sgmii_active_82575(hw)) {
1489 /* allow time for SFP cage time to power up phy */
1490 msec_delay(300);
1491
1492 ret_val = hw->phy.ops.reset(hw);
1493 if (ret_val) {
1494 DEBUGOUT("Error resetting the PHY.\n");
1495 goto out;
1496 }
1497 }
1498 switch (hw->phy.type) {
1499 case e1000_phy_i210:
1500 /* Fall through */
1501 case e1000_phy_m88:
1502 switch (hw->phy.id) {
1503 case I347AT4_E_PHY_ID:
1504 /* Fall through */
1505 case M88E1112_E_PHY_ID:
1506 /* Fall through */
1507 case M88E1340M_E_PHY_ID:
1508 /* Fall through */
1509 case M88E1543_E_PHY_ID:
1510 /* Fall through */
1511 case M88E1512_E_PHY_ID:
1512 /* Fall through */
1513 case I210_I_PHY_ID:
1514 /* Fall through */
1515 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1516 break;
1517 default:
1518 ret_val = e1000_copper_link_setup_m88(hw);
1519 break;
1520 }
1521 break;
1522 case e1000_phy_igp_3:
1523 ret_val = e1000_copper_link_setup_igp(hw);
1524 break;
1525 case e1000_phy_82580:
1526 ret_val = e1000_copper_link_setup_82577(hw);
1527 break;
1528 default:
1529 ret_val = -E1000_ERR_PHY;
1530 break;
1531 }
1532
1533 if (ret_val)
1534 goto out;
1535
1536 ret_val = e1000_setup_copper_link_generic(hw);
1537 out:
1538 return ret_val;
1539 }
1540
1541 /**
1542 * e1000_setup_serdes_link_82575 - Setup link for serdes
1543 * @hw: pointer to the HW structure
1544 *
1545 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1546 * used on copper connections where the serialized gigabit media independent
1547 * interface (sgmii), or serdes fiber is being used. Configures the link
1548 * for auto-negotiation or forces speed/duplex.
1549 **/
e1000_setup_serdes_link_82575(struct e1000_hw * hw)1550 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1551 {
1552 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1553 bool pcs_autoneg;
1554 s32 ret_val = E1000_SUCCESS;
1555 u16 data;
1556
1557 DEBUGFUNC("e1000_setup_serdes_link_82575");
1558
1559 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1560 !e1000_sgmii_active_82575(hw))
1561 return ret_val;
1562
1563 /*
1564 * On the 82575, SerDes loopback mode persists until it is
1565 * explicitly turned off or a power cycle is performed. A read to
1566 * the register does not indicate its status. Therefore, we ensure
1567 * loopback mode is disabled during initialization.
1568 */
1569 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1570
1571 /* power on the sfp cage if present */
1572 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1573 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1574 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1575
1576 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1577 ctrl_reg |= E1000_CTRL_SLU;
1578
1579 /* set both sw defined pins on 82575/82576*/
1580 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1581 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1582
1583 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1584
1585 /* default pcs_autoneg to the same setting as mac autoneg */
1586 pcs_autoneg = hw->mac.autoneg;
1587
1588 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1589 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1590 /* sgmii mode lets the phy handle forcing speed/duplex */
1591 pcs_autoneg = true;
1592 /* autoneg time out should be disabled for SGMII mode */
1593 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1594 break;
1595 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1596 /* disable PCS autoneg and support parallel detect only */
1597 pcs_autoneg = false;
1598 /* Fall through */
1599 default:
1600 if (hw->mac.type == e1000_82575 ||
1601 hw->mac.type == e1000_82576) {
1602 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1603 if (ret_val) {
1604 DEBUGOUT("NVM Read Error\n");
1605 return ret_val;
1606 }
1607
1608 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1609 pcs_autoneg = false;
1610 }
1611
1612 /*
1613 * non-SGMII modes only supports a speed of 1000/Full for the
1614 * link so it is best to just force the MAC and let the pcs
1615 * link either autoneg or be forced to 1000/Full
1616 */
1617 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1618 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1619
1620 /* set speed of 1000/Full if speed/duplex is forced */
1621 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1622 break;
1623 }
1624
1625 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1626
1627 /*
1628 * New SerDes mode allows for forcing speed or autonegotiating speed
1629 * at 1gb. Autoneg should be default set by most drivers. This is the
1630 * mode that will be compatible with older link partners and switches.
1631 * However, both are supported by the hardware and some drivers/tools.
1632 */
1633 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1634 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1635
1636 if (pcs_autoneg) {
1637 /* Set PCS register for autoneg */
1638 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1639 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1640
1641 /* Disable force flow control for autoneg */
1642 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1643
1644 /* Configure flow control advertisement for autoneg */
1645 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1646 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1647
1648 switch (hw->fc.requested_mode) {
1649 case e1000_fc_full:
1650 case e1000_fc_rx_pause:
1651 anadv_reg |= E1000_TXCW_ASM_DIR;
1652 anadv_reg |= E1000_TXCW_PAUSE;
1653 break;
1654 case e1000_fc_tx_pause:
1655 anadv_reg |= E1000_TXCW_ASM_DIR;
1656 break;
1657 default:
1658 break;
1659 }
1660
1661 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1662
1663 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1664 } else {
1665 /* Set PCS register for forced link */
1666 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1667
1668 /* Force flow control for forced link */
1669 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1670
1671 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1672 }
1673
1674 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1675
1676 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1677 e1000_force_mac_fc_generic(hw);
1678
1679 return ret_val;
1680 }
1681
1682 /**
1683 * e1000_get_media_type_82575 - derives current media type.
1684 * @hw: pointer to the HW structure
1685 *
1686 * The media type is chosen reflecting few settings.
1687 * The following are taken into account:
1688 * - link mode set in the current port Init Control Word #3
1689 * - current link mode settings in CSR register
1690 * - MDIO vs. I2C PHY control interface chosen
1691 * - SFP module media type
1692 **/
e1000_get_media_type_82575(struct e1000_hw * hw)1693 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1694 {
1695 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1696 s32 ret_val = E1000_SUCCESS;
1697 u32 ctrl_ext = 0;
1698 u32 link_mode = 0;
1699
1700 /* Set internal phy as default */
1701 dev_spec->sgmii_active = false;
1702 dev_spec->module_plugged = false;
1703
1704 /* Get CSR setting */
1705 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1706
1707 /* extract link mode setting */
1708 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1709
1710 switch (link_mode) {
1711 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1712 hw->phy.media_type = e1000_media_type_internal_serdes;
1713 break;
1714 case E1000_CTRL_EXT_LINK_MODE_GMII:
1715 hw->phy.media_type = e1000_media_type_copper;
1716 break;
1717 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1718 /* Get phy control interface type set (MDIO vs. I2C)*/
1719 if (e1000_sgmii_uses_mdio_82575(hw)) {
1720 hw->phy.media_type = e1000_media_type_copper;
1721 dev_spec->sgmii_active = true;
1722 break;
1723 }
1724 /* Fall through for I2C based SGMII */
1725 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1726 /* read media type from SFP EEPROM */
1727 ret_val = e1000_set_sfp_media_type_82575(hw);
1728 if ((ret_val != E1000_SUCCESS) ||
1729 (hw->phy.media_type == e1000_media_type_unknown)) {
1730 /*
1731 * If media type was not identified then return media
1732 * type defined by the CTRL_EXT settings.
1733 */
1734 hw->phy.media_type = e1000_media_type_internal_serdes;
1735
1736 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1737 hw->phy.media_type = e1000_media_type_copper;
1738 dev_spec->sgmii_active = true;
1739 }
1740
1741 break;
1742 }
1743
1744 /* do not change link mode for 100BaseFX */
1745 if (dev_spec->eth_flags.e100_base_fx)
1746 break;
1747
1748 /* change current link mode setting */
1749 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1750
1751 if (hw->phy.media_type == e1000_media_type_copper)
1752 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1753 else
1754 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1755
1756 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1757
1758 break;
1759 }
1760
1761 return ret_val;
1762 }
1763
1764 /**
1765 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1766 * @hw: pointer to the HW structure
1767 *
1768 * The media type is chosen based on SFP module.
1769 * compatibility flags retrieved from SFP ID EEPROM.
1770 **/
e1000_set_sfp_media_type_82575(struct e1000_hw * hw)1771 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1772 {
1773 s32 ret_val = E1000_ERR_CONFIG;
1774 u32 ctrl_ext = 0;
1775 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1776 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1777 u8 tranceiver_type = 0;
1778 s32 timeout = 3;
1779
1780 /* Turn I2C interface ON and power on sfp cage */
1781 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1782 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1783 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1784
1785 E1000_WRITE_FLUSH(hw);
1786
1787 /* Read SFP module data */
1788 while (timeout) {
1789 ret_val = e1000_read_sfp_data_byte(hw,
1790 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1791 &tranceiver_type);
1792 if (ret_val == E1000_SUCCESS)
1793 break;
1794 msec_delay(100);
1795 timeout--;
1796 }
1797 if (ret_val != E1000_SUCCESS)
1798 goto out;
1799
1800 ret_val = e1000_read_sfp_data_byte(hw,
1801 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1802 (u8 *)eth_flags);
1803 if (ret_val != E1000_SUCCESS)
1804 goto out;
1805
1806 /* Check if there is some SFP module plugged and powered */
1807 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1808 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1809 dev_spec->module_plugged = true;
1810 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1811 hw->phy.media_type = e1000_media_type_internal_serdes;
1812 } else if (eth_flags->e100_base_fx) {
1813 dev_spec->sgmii_active = true;
1814 hw->phy.media_type = e1000_media_type_internal_serdes;
1815 } else if (eth_flags->e1000_base_t) {
1816 dev_spec->sgmii_active = true;
1817 hw->phy.media_type = e1000_media_type_copper;
1818 } else {
1819 hw->phy.media_type = e1000_media_type_unknown;
1820 DEBUGOUT("PHY module has not been recognized\n");
1821 goto out;
1822 }
1823 } else {
1824 hw->phy.media_type = e1000_media_type_unknown;
1825 }
1826 ret_val = E1000_SUCCESS;
1827 out:
1828 /* Restore I2C interface setting */
1829 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1830 return ret_val;
1831 }
1832
1833 /**
1834 * e1000_valid_led_default_82575 - Verify a valid default LED config
1835 * @hw: pointer to the HW structure
1836 * @data: pointer to the NVM (EEPROM)
1837 *
1838 * Read the EEPROM for the current default LED configuration. If the
1839 * LED configuration is not valid, set to a valid LED configuration.
1840 **/
e1000_valid_led_default_82575(struct e1000_hw * hw,u16 * data)1841 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1842 {
1843 s32 ret_val;
1844
1845 DEBUGFUNC("e1000_valid_led_default_82575");
1846
1847 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1848 if (ret_val) {
1849 DEBUGOUT("NVM Read Error\n");
1850 goto out;
1851 }
1852
1853 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1854 switch (hw->phy.media_type) {
1855 case e1000_media_type_internal_serdes:
1856 *data = ID_LED_DEFAULT_82575_SERDES;
1857 break;
1858 case e1000_media_type_copper:
1859 default:
1860 *data = ID_LED_DEFAULT;
1861 break;
1862 }
1863 }
1864 out:
1865 return ret_val;
1866 }
1867
1868 /**
1869 * e1000_sgmii_active_82575 - Return sgmii state
1870 * @hw: pointer to the HW structure
1871 *
1872 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1873 * which can be enabled for use in the embedded applications. Simply
1874 * return the current state of the sgmii interface.
1875 **/
e1000_sgmii_active_82575(struct e1000_hw * hw)1876 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1877 {
1878 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1879 return dev_spec->sgmii_active;
1880 }
1881
1882 /**
1883 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1884 * @hw: pointer to the HW structure
1885 *
1886 * Inits recommended HW defaults after a reset when there is no EEPROM
1887 * detected. This is only for the 82575.
1888 **/
e1000_reset_init_script_82575(struct e1000_hw * hw)1889 s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1890 {
1891 DEBUGFUNC("e1000_reset_init_script_82575");
1892
1893 if (hw->mac.type == e1000_82575) {
1894 DEBUGOUT("Running reset init script for 82575\n");
1895 /* SerDes configuration via SERDESCTRL */
1896 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1897 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1898 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1899 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1900
1901 /* CCM configuration via CCMCTL register */
1902 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1903 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1904
1905 /* PCIe lanes configuration */
1906 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1907 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1908 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1909 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1910
1911 /* PCIe PLL Configuration */
1912 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1913 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1914 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1915 }
1916
1917 return E1000_SUCCESS;
1918 }
1919
1920 /**
1921 * e1000_read_mac_addr_82575 - Read device MAC address
1922 * @hw: pointer to the HW structure
1923 **/
e1000_read_mac_addr_82575(struct e1000_hw * hw)1924 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1925 {
1926 s32 ret_val;
1927
1928 DEBUGFUNC("e1000_read_mac_addr_82575");
1929
1930 /*
1931 * If there's an alternate MAC address place it in RAR0
1932 * so that it will override the Si installed default perm
1933 * address.
1934 */
1935 ret_val = e1000_check_alt_mac_addr_generic(hw);
1936 if (ret_val)
1937 goto out;
1938
1939 ret_val = e1000_read_mac_addr_generic(hw);
1940
1941 out:
1942 return ret_val;
1943 }
1944
1945 /**
1946 * e1000_config_collision_dist_82575 - Configure collision distance
1947 * @hw: pointer to the HW structure
1948 *
1949 * Configures the collision distance to the default value and is used
1950 * during link setup.
1951 **/
e1000_config_collision_dist_82575(struct e1000_hw * hw)1952 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1953 {
1954 u32 tctl_ext;
1955
1956 DEBUGFUNC("e1000_config_collision_dist_82575");
1957
1958 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1959
1960 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1961 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1962
1963 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1964 E1000_WRITE_FLUSH(hw);
1965 }
1966
1967 /**
1968 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1969 * @hw: pointer to the HW structure
1970 *
1971 * Clears the hardware counters by reading the counter registers.
1972 **/
e1000_clear_hw_cntrs_82575(struct e1000_hw * hw)1973 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1974 {
1975 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1976
1977 e1000_clear_hw_cntrs_base_generic(hw);
1978
1979 E1000_READ_REG(hw, E1000_PRC64);
1980 E1000_READ_REG(hw, E1000_PRC127);
1981 E1000_READ_REG(hw, E1000_PRC255);
1982 E1000_READ_REG(hw, E1000_PRC511);
1983 E1000_READ_REG(hw, E1000_PRC1023);
1984 E1000_READ_REG(hw, E1000_PRC1522);
1985 E1000_READ_REG(hw, E1000_PTC64);
1986 E1000_READ_REG(hw, E1000_PTC127);
1987 E1000_READ_REG(hw, E1000_PTC255);
1988 E1000_READ_REG(hw, E1000_PTC511);
1989 E1000_READ_REG(hw, E1000_PTC1023);
1990 E1000_READ_REG(hw, E1000_PTC1522);
1991
1992 E1000_READ_REG(hw, E1000_ALGNERRC);
1993 E1000_READ_REG(hw, E1000_RXERRC);
1994 E1000_READ_REG(hw, E1000_TNCRS);
1995 E1000_READ_REG(hw, E1000_CEXTERR);
1996 E1000_READ_REG(hw, E1000_TSCTC);
1997 E1000_READ_REG(hw, E1000_TSCTFC);
1998
1999 E1000_READ_REG(hw, E1000_MGTPRC);
2000 E1000_READ_REG(hw, E1000_MGTPDC);
2001 E1000_READ_REG(hw, E1000_MGTPTC);
2002
2003 E1000_READ_REG(hw, E1000_IAC);
2004 E1000_READ_REG(hw, E1000_ICRXOC);
2005
2006 E1000_READ_REG(hw, E1000_ICRXPTC);
2007 E1000_READ_REG(hw, E1000_ICRXATC);
2008 E1000_READ_REG(hw, E1000_ICTXPTC);
2009 E1000_READ_REG(hw, E1000_ICTXATC);
2010 E1000_READ_REG(hw, E1000_ICTXQEC);
2011 E1000_READ_REG(hw, E1000_ICTXQMTC);
2012 E1000_READ_REG(hw, E1000_ICRXDMTC);
2013
2014 E1000_READ_REG(hw, E1000_CBTMPC);
2015 E1000_READ_REG(hw, E1000_HTDPMC);
2016 E1000_READ_REG(hw, E1000_CBRMPC);
2017 E1000_READ_REG(hw, E1000_RPTHC);
2018 E1000_READ_REG(hw, E1000_HGPTC);
2019 E1000_READ_REG(hw, E1000_HTCBDPC);
2020 E1000_READ_REG(hw, E1000_HGORCL);
2021 E1000_READ_REG(hw, E1000_HGORCH);
2022 E1000_READ_REG(hw, E1000_HGOTCL);
2023 E1000_READ_REG(hw, E1000_HGOTCH);
2024 E1000_READ_REG(hw, E1000_LENERRS);
2025
2026 /* This register should not be read in copper configurations */
2027 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2028 e1000_sgmii_active_82575(hw))
2029 E1000_READ_REG(hw, E1000_SCVPC);
2030 }
2031
2032 /**
2033 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2034 * @hw: pointer to the HW structure
2035 *
2036 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2037 * however the hardware default for these parts is 500us to 1ms which is less
2038 * than the 10ms recommended by the pci-e spec. To address this we need to
2039 * increase the value to either 10ms to 200ms for capability version 1 config,
2040 * or 16ms to 55ms for version 2.
2041 **/
e1000_set_pcie_completion_timeout(struct e1000_hw * hw)2042 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2043 {
2044 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2045 s32 ret_val = E1000_SUCCESS;
2046 u16 pcie_devctl2;
2047
2048 /* only take action if timeout value is defaulted to 0 */
2049 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2050 goto out;
2051
2052 /*
2053 * if capababilities version is type 1 we can write the
2054 * timeout of 10ms to 200ms through the GCR register
2055 */
2056 if (!(gcr & E1000_GCR_CAP_VER2)) {
2057 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2058 goto out;
2059 }
2060
2061 /*
2062 * for version 2 capabilities we need to write the config space
2063 * directly in order to set the completion timeout value for
2064 * 16ms to 55ms
2065 */
2066 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2067 &pcie_devctl2);
2068 if (ret_val)
2069 goto out;
2070
2071 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2072
2073 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2074 &pcie_devctl2);
2075 out:
2076 /* disable completion timeout resend */
2077 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2078
2079 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2080 return ret_val;
2081 }
2082
2083 /**
2084 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2085 * @hw: pointer to the hardware struct
2086 * @enable: state to enter, either enabled or disabled
2087 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2088 *
2089 * enables/disables L2 switch anti-spoofing functionality.
2090 **/
e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw * hw,bool enable,int pf)2091 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2092 {
2093 u32 reg_val, reg_offset;
2094
2095 switch (hw->mac.type) {
2096 case e1000_82576:
2097 reg_offset = E1000_DTXSWC;
2098 break;
2099 case e1000_i350:
2100 case e1000_i354:
2101 reg_offset = E1000_TXSWC;
2102 break;
2103 default:
2104 return;
2105 }
2106
2107 reg_val = E1000_READ_REG(hw, reg_offset);
2108 if (enable) {
2109 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2110 E1000_DTXSWC_VLAN_SPOOF_MASK);
2111 /* The PF can spoof - it has to in order to
2112 * support emulation mode NICs
2113 */
2114 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2115 } else {
2116 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2117 E1000_DTXSWC_VLAN_SPOOF_MASK);
2118 }
2119 E1000_WRITE_REG(hw, reg_offset, reg_val);
2120 }
2121
2122 /**
2123 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2124 * @hw: pointer to the hardware struct
2125 * @enable: state to enter, either enabled or disabled
2126 *
2127 * enables/disables L2 switch loopback functionality.
2128 **/
e1000_vmdq_set_loopback_pf(struct e1000_hw * hw,bool enable)2129 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2130 {
2131 u32 dtxswc;
2132
2133 switch (hw->mac.type) {
2134 case e1000_82576:
2135 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2136 if (enable)
2137 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2138 else
2139 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2140 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2141 break;
2142 case e1000_i350:
2143 case e1000_i354:
2144 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2145 if (enable)
2146 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2147 else
2148 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2149 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2150 break;
2151 default:
2152 /* Currently no other hardware supports loopback */
2153 break;
2154 }
2155
2156
2157 }
2158
2159 /**
2160 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2161 * @hw: pointer to the hardware struct
2162 * @enable: state to enter, either enabled or disabled
2163 *
2164 * enables/disables replication of packets across multiple pools.
2165 **/
e1000_vmdq_set_replication_pf(struct e1000_hw * hw,bool enable)2166 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2167 {
2168 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2169
2170 if (enable)
2171 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2172 else
2173 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2174
2175 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2176 }
2177
2178 /**
2179 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2180 * @hw: pointer to the HW structure
2181 * @offset: register offset to be read
2182 * @data: pointer to the read data
2183 *
2184 * Reads the MDI control register in the PHY at offset and stores the
2185 * information read to data.
2186 **/
e1000_read_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 * data)2187 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2188 {
2189 s32 ret_val;
2190
2191 DEBUGFUNC("e1000_read_phy_reg_82580");
2192
2193 ret_val = hw->phy.ops.acquire(hw);
2194 if (ret_val)
2195 goto out;
2196
2197 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2198
2199 hw->phy.ops.release(hw);
2200
2201 out:
2202 return ret_val;
2203 }
2204
2205 /**
2206 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2207 * @hw: pointer to the HW structure
2208 * @offset: register offset to write to
2209 * @data: data to write to register at offset
2210 *
2211 * Writes data to MDI control register in the PHY at offset.
2212 **/
e1000_write_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 data)2213 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2214 {
2215 s32 ret_val;
2216
2217 DEBUGFUNC("e1000_write_phy_reg_82580");
2218
2219 ret_val = hw->phy.ops.acquire(hw);
2220 if (ret_val)
2221 goto out;
2222
2223 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2224
2225 hw->phy.ops.release(hw);
2226
2227 out:
2228 return ret_val;
2229 }
2230
2231 /**
2232 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2233 * @hw: pointer to the HW structure
2234 *
2235 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2236 * the values found in the EEPROM. This addresses an issue in which these
2237 * bits are not restored from EEPROM after reset.
2238 **/
e1000_reset_mdicnfg_82580(struct e1000_hw * hw)2239 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2240 {
2241 s32 ret_val = E1000_SUCCESS;
2242 u32 mdicnfg;
2243 u16 nvm_data = 0;
2244
2245 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2246
2247 if (hw->mac.type != e1000_82580)
2248 goto out;
2249 if (!e1000_sgmii_active_82575(hw))
2250 goto out;
2251
2252 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2253 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2254 &nvm_data);
2255 if (ret_val) {
2256 DEBUGOUT("NVM Read Error\n");
2257 goto out;
2258 }
2259
2260 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2261 if (nvm_data & NVM_WORD24_EXT_MDIO)
2262 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2263 if (nvm_data & NVM_WORD24_COM_MDIO)
2264 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2265 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2266 out:
2267 return ret_val;
2268 }
2269
2270 /**
2271 * e1000_reset_hw_82580 - Reset hardware
2272 * @hw: pointer to the HW structure
2273 *
2274 * This resets function or entire device (all ports, etc.)
2275 * to a known state.
2276 **/
e1000_reset_hw_82580(struct e1000_hw * hw)2277 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2278 {
2279 s32 ret_val = E1000_SUCCESS;
2280 /* BH SW mailbox bit in SW_FW_SYNC */
2281 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2282 u32 ctrl;
2283 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2284
2285 DEBUGFUNC("e1000_reset_hw_82580");
2286
2287 hw->dev_spec._82575.global_device_reset = false;
2288
2289 /* 82580 does not reliably do global_device_reset due to hw errata */
2290 if (hw->mac.type == e1000_82580)
2291 global_device_reset = false;
2292
2293 /* Get current control state. */
2294 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2295
2296 /*
2297 * Prevent the PCI-E bus from sticking if there is no TLP connection
2298 * on the last TLP read/write transaction when MAC is reset.
2299 */
2300 ret_val = e1000_disable_pcie_master_generic(hw);
2301 if (ret_val)
2302 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2303
2304 DEBUGOUT("Masking off all interrupts\n");
2305 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2306 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2307 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2308 E1000_WRITE_FLUSH(hw);
2309
2310 msec_delay(10);
2311
2312 /* Determine whether or not a global dev reset is requested */
2313 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2314 swmbsw_mask))
2315 global_device_reset = false;
2316
2317 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2318 E1000_STAT_DEV_RST_SET))
2319 ctrl |= E1000_CTRL_DEV_RST;
2320 else
2321 ctrl |= E1000_CTRL_RST;
2322
2323 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2324
2325 switch (hw->device_id) {
2326 case E1000_DEV_ID_DH89XXCC_SGMII:
2327 break;
2328 default:
2329 E1000_WRITE_FLUSH(hw);
2330 break;
2331 }
2332
2333 /* Add delay to insure DEV_RST or RST has time to complete */
2334 msec_delay(5);
2335
2336 ret_val = e1000_get_auto_rd_done_generic(hw);
2337 if (ret_val) {
2338 /*
2339 * When auto config read does not complete, do not
2340 * return with an error. This can happen in situations
2341 * where there is no eeprom and prevents getting link.
2342 */
2343 DEBUGOUT("Auto Read Done did not complete\n");
2344 }
2345
2346 /* clear global device reset status bit */
2347 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2348
2349 /* Clear any pending interrupt events. */
2350 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2351 E1000_READ_REG(hw, E1000_ICR);
2352
2353 ret_val = e1000_reset_mdicnfg_82580(hw);
2354 if (ret_val)
2355 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2356
2357 /* Install any alternate MAC address into RAR0 */
2358 ret_val = e1000_check_alt_mac_addr_generic(hw);
2359
2360 /* Release semaphore */
2361 if (global_device_reset)
2362 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2363
2364 return ret_val;
2365 }
2366
2367 /**
2368 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2369 * @data: data received by reading RXPBS register
2370 *
2371 * The 82580 uses a table based approach for packet buffer allocation sizes.
2372 * This function converts the retrieved value into the correct table value
2373 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2374 * 0x0 36 72 144 1 2 4 8 16
2375 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2376 */
e1000_rxpbs_adjust_82580(u32 data)2377 u16 e1000_rxpbs_adjust_82580(u32 data)
2378 {
2379 u16 ret_val = 0;
2380
2381 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2382 ret_val = e1000_82580_rxpbs_table[data];
2383
2384 return ret_val;
2385 }
2386
2387 /**
2388 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2389 * checksum
2390 * @hw: pointer to the HW structure
2391 * @offset: offset in words of the checksum protected region
2392 *
2393 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2394 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2395 **/
e1000_validate_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2396 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2397 {
2398 s32 ret_val = E1000_SUCCESS;
2399 u16 checksum = 0;
2400 u16 i, nvm_data;
2401
2402 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2403
2404 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2405 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2406 if (ret_val) {
2407 DEBUGOUT("NVM Read Error\n");
2408 goto out;
2409 }
2410 checksum += nvm_data;
2411 }
2412
2413 if (checksum != (u16) NVM_SUM) {
2414 DEBUGOUT("NVM Checksum Invalid\n");
2415 ret_val = -E1000_ERR_NVM;
2416 goto out;
2417 }
2418
2419 out:
2420 return ret_val;
2421 }
2422
2423 /**
2424 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2425 * checksum
2426 * @hw: pointer to the HW structure
2427 * @offset: offset in words of the checksum protected region
2428 *
2429 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2430 * up to the checksum. Then calculates the EEPROM checksum and writes the
2431 * value to the EEPROM.
2432 **/
e1000_update_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2433 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2434 {
2435 s32 ret_val;
2436 u16 checksum = 0;
2437 u16 i, nvm_data;
2438
2439 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2440
2441 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2442 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2443 if (ret_val) {
2444 DEBUGOUT("NVM Read Error while updating checksum.\n");
2445 goto out;
2446 }
2447 checksum += nvm_data;
2448 }
2449 checksum = (u16) NVM_SUM - checksum;
2450 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2451 &checksum);
2452 if (ret_val)
2453 DEBUGOUT("NVM Write Error while updating checksum.\n");
2454
2455 out:
2456 return ret_val;
2457 }
2458
2459 /**
2460 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2461 * @hw: pointer to the HW structure
2462 *
2463 * Calculates the EEPROM section checksum by reading/adding each word of
2464 * the EEPROM and then verifies that the sum of the EEPROM is
2465 * equal to 0xBABA.
2466 **/
e1000_validate_nvm_checksum_82580(struct e1000_hw * hw)2467 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2468 {
2469 s32 ret_val;
2470 u16 eeprom_regions_count = 1;
2471 u16 j, nvm_data;
2472 u16 nvm_offset;
2473
2474 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2475
2476 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2477 if (ret_val) {
2478 DEBUGOUT("NVM Read Error\n");
2479 goto out;
2480 }
2481
2482 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2483 /* if chekcsums compatibility bit is set validate checksums
2484 * for all 4 ports. */
2485 eeprom_regions_count = 4;
2486 }
2487
2488 for (j = 0; j < eeprom_regions_count; j++) {
2489 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2490 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2491 nvm_offset);
2492 if (ret_val != E1000_SUCCESS)
2493 goto out;
2494 }
2495
2496 out:
2497 return ret_val;
2498 }
2499
2500 /**
2501 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2502 * @hw: pointer to the HW structure
2503 *
2504 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2505 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2506 * checksum and writes the value to the EEPROM.
2507 **/
e1000_update_nvm_checksum_82580(struct e1000_hw * hw)2508 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2509 {
2510 s32 ret_val;
2511 u16 j, nvm_data;
2512 u16 nvm_offset;
2513
2514 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2515
2516 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2517 if (ret_val) {
2518 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2519 goto out;
2520 }
2521
2522 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2523 /* set compatibility bit to validate checksums appropriately */
2524 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2525 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2526 &nvm_data);
2527 if (ret_val) {
2528 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2529 goto out;
2530 }
2531 }
2532
2533 for (j = 0; j < 4; j++) {
2534 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2535 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2536 if (ret_val)
2537 goto out;
2538 }
2539
2540 out:
2541 return ret_val;
2542 }
2543
2544 /**
2545 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2546 * @hw: pointer to the HW structure
2547 *
2548 * Calculates the EEPROM section checksum by reading/adding each word of
2549 * the EEPROM and then verifies that the sum of the EEPROM is
2550 * equal to 0xBABA.
2551 **/
e1000_validate_nvm_checksum_i350(struct e1000_hw * hw)2552 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2553 {
2554 s32 ret_val = E1000_SUCCESS;
2555 u16 j;
2556 u16 nvm_offset;
2557
2558 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2559
2560 for (j = 0; j < 4; j++) {
2561 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2562 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2563 nvm_offset);
2564 if (ret_val != E1000_SUCCESS)
2565 goto out;
2566 }
2567
2568 out:
2569 return ret_val;
2570 }
2571
2572 /**
2573 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2574 * @hw: pointer to the HW structure
2575 *
2576 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2577 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2578 * checksum and writes the value to the EEPROM.
2579 **/
e1000_update_nvm_checksum_i350(struct e1000_hw * hw)2580 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2581 {
2582 s32 ret_val = E1000_SUCCESS;
2583 u16 j;
2584 u16 nvm_offset;
2585
2586 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2587
2588 for (j = 0; j < 4; j++) {
2589 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2590 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2591 if (ret_val != E1000_SUCCESS)
2592 goto out;
2593 }
2594
2595 out:
2596 return ret_val;
2597 }
2598
2599 /**
2600 * __e1000_access_emi_reg - Read/write EMI register
2601 * @hw: pointer to the HW structure
2602 * @address: EMI address to program
2603 * @data: pointer to value to read/write from/to the EMI address
2604 * @read: boolean flag to indicate read or write
2605 **/
__e1000_access_emi_reg(struct e1000_hw * hw,u16 address,u16 * data,bool read)2606 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2607 u16 *data, bool read)
2608 {
2609 s32 ret_val;
2610
2611 DEBUGFUNC("__e1000_access_emi_reg");
2612
2613 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2614 if (ret_val)
2615 return ret_val;
2616
2617 if (read)
2618 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2619 else
2620 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2621
2622 return ret_val;
2623 }
2624
2625 /**
2626 * e1000_read_emi_reg - Read Extended Management Interface register
2627 * @hw: pointer to the HW structure
2628 * @addr: EMI address to program
2629 * @data: value to be read from the EMI address
2630 **/
e1000_read_emi_reg(struct e1000_hw * hw,u16 addr,u16 * data)2631 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2632 {
2633 DEBUGFUNC("e1000_read_emi_reg");
2634
2635 return __e1000_access_emi_reg(hw, addr, data, true);
2636 }
2637
2638 /**
2639 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2640 * @hw: pointer to the HW structure
2641 *
2642 * Initialize Marvell 1512 to work correctly with Avoton.
2643 **/
e1000_initialize_M88E1512_phy(struct e1000_hw * hw)2644 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2645 {
2646 struct e1000_phy_info *phy = &hw->phy;
2647 s32 ret_val = E1000_SUCCESS;
2648
2649 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2650
2651 /* Check if this is correct PHY. */
2652 if (phy->id != M88E1512_E_PHY_ID)
2653 goto out;
2654
2655 /* Switch to PHY page 0xFF. */
2656 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2657 if (ret_val)
2658 goto out;
2659
2660 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2661 if (ret_val)
2662 goto out;
2663
2664 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2665 if (ret_val)
2666 goto out;
2667
2668 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2669 if (ret_val)
2670 goto out;
2671
2672 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2673 if (ret_val)
2674 goto out;
2675
2676 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2677 if (ret_val)
2678 goto out;
2679
2680 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2681 if (ret_val)
2682 goto out;
2683
2684 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2685 if (ret_val)
2686 goto out;
2687
2688 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2689 if (ret_val)
2690 goto out;
2691
2692 /* Switch to PHY page 0xFB. */
2693 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2694 if (ret_val)
2695 goto out;
2696
2697 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2698 if (ret_val)
2699 goto out;
2700
2701 /* Switch to PHY page 0x12. */
2702 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2703 if (ret_val)
2704 goto out;
2705
2706 /* Change mode to SGMII-to-Copper */
2707 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2708 if (ret_val)
2709 goto out;
2710
2711 /* Return the PHY to page 0. */
2712 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2713 if (ret_val)
2714 goto out;
2715
2716 ret_val = phy->ops.commit(hw);
2717 if (ret_val) {
2718 DEBUGOUT("Error committing the PHY changes\n");
2719 return ret_val;
2720 }
2721
2722 msec_delay(1000);
2723 out:
2724 return ret_val;
2725 }
2726
2727 /**
2728 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2729 * @hw: pointer to the HW structure
2730 *
2731 * Initialize Marvell 1543 to work correctly with Avoton.
2732 **/
e1000_initialize_M88E1543_phy(struct e1000_hw * hw)2733 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2734 {
2735 struct e1000_phy_info *phy = &hw->phy;
2736 s32 ret_val = E1000_SUCCESS;
2737
2738 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2739
2740 /* Check if this is correct PHY. */
2741 if (phy->id != M88E1543_E_PHY_ID)
2742 goto out;
2743
2744 /* Switch to PHY page 0xFF. */
2745 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2746 if (ret_val)
2747 goto out;
2748
2749 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2750 if (ret_val)
2751 goto out;
2752
2753 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2754 if (ret_val)
2755 goto out;
2756
2757 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2758 if (ret_val)
2759 goto out;
2760
2761 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2762 if (ret_val)
2763 goto out;
2764
2765 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2766 if (ret_val)
2767 goto out;
2768
2769 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2770 if (ret_val)
2771 goto out;
2772
2773 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2774 if (ret_val)
2775 goto out;
2776
2777 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2778 if (ret_val)
2779 goto out;
2780
2781 /* Switch to PHY page 0xFB. */
2782 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2783 if (ret_val)
2784 goto out;
2785
2786 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2787 if (ret_val)
2788 goto out;
2789
2790 /* Switch to PHY page 0x12. */
2791 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2792 if (ret_val)
2793 goto out;
2794
2795 /* Change mode to SGMII-to-Copper */
2796 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2797 if (ret_val)
2798 goto out;
2799
2800 /* Switch to PHY page 1. */
2801 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2802 if (ret_val)
2803 goto out;
2804
2805 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2806 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2807 if (ret_val)
2808 goto out;
2809
2810 /* Return the PHY to page 0. */
2811 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2812 if (ret_val)
2813 goto out;
2814
2815 ret_val = phy->ops.commit(hw);
2816 if (ret_val) {
2817 DEBUGOUT("Error committing the PHY changes\n");
2818 return ret_val;
2819 }
2820
2821 msec_delay(1000);
2822 out:
2823 return ret_val;
2824 }
2825
2826 /**
2827 * e1000_set_eee_i350 - Enable/disable EEE support
2828 * @hw: pointer to the HW structure
2829 * @adv1G: boolean flag enabling 1G EEE advertisement
2830 * @adv100M: boolean flag enabling 100M EEE advertisement
2831 *
2832 * Enable/disable EEE based on setting in dev_spec structure.
2833 *
2834 **/
e1000_set_eee_i350(struct e1000_hw * hw,bool adv1G,bool adv100M)2835 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2836 {
2837 u32 ipcnfg, eeer;
2838
2839 DEBUGFUNC("e1000_set_eee_i350");
2840
2841 if ((hw->mac.type < e1000_i350) ||
2842 (hw->phy.media_type != e1000_media_type_copper))
2843 goto out;
2844 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2845 eeer = E1000_READ_REG(hw, E1000_EEER);
2846
2847 /* enable or disable per user setting */
2848 if (!(hw->dev_spec._82575.eee_disable)) {
2849 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2850
2851 if (adv100M)
2852 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2853 else
2854 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2855
2856 if (adv1G)
2857 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2858 else
2859 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2860
2861 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2862 E1000_EEER_LPI_FC);
2863
2864 /* This bit should not be set in normal operation. */
2865 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2866 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2867 } else {
2868 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2869 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2870 E1000_EEER_LPI_FC);
2871 }
2872 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2873 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2874 E1000_READ_REG(hw, E1000_IPCNFG);
2875 E1000_READ_REG(hw, E1000_EEER);
2876 out:
2877
2878 return E1000_SUCCESS;
2879 }
2880
2881 /**
2882 * e1000_set_eee_i354 - Enable/disable EEE support
2883 * @hw: pointer to the HW structure
2884 * @adv1G: boolean flag enabling 1G EEE advertisement
2885 * @adv100M: boolean flag enabling 100M EEE advertisement
2886 *
2887 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2888 *
2889 **/
e1000_set_eee_i354(struct e1000_hw * hw,bool adv1G,bool adv100M)2890 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2891 {
2892 struct e1000_phy_info *phy = &hw->phy;
2893 s32 ret_val = E1000_SUCCESS;
2894 u16 phy_data;
2895
2896 DEBUGFUNC("e1000_set_eee_i354");
2897
2898 if ((hw->phy.media_type != e1000_media_type_copper) ||
2899 ((phy->id != M88E1543_E_PHY_ID) &&
2900 (phy->id != M88E1512_E_PHY_ID)))
2901 goto out;
2902
2903 if (!hw->dev_spec._82575.eee_disable) {
2904 /* Switch to PHY page 18. */
2905 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2906 if (ret_val)
2907 goto out;
2908
2909 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2910 &phy_data);
2911 if (ret_val)
2912 goto out;
2913
2914 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2915 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2916 phy_data);
2917 if (ret_val)
2918 goto out;
2919
2920 /* Return the PHY to page 0. */
2921 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2922 if (ret_val)
2923 goto out;
2924
2925 /* Turn on EEE advertisement. */
2926 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2927 E1000_EEE_ADV_DEV_I354,
2928 &phy_data);
2929 if (ret_val)
2930 goto out;
2931
2932 if (adv100M)
2933 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2934 else
2935 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2936
2937 if (adv1G)
2938 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2939 else
2940 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2941
2942 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2943 E1000_EEE_ADV_DEV_I354,
2944 phy_data);
2945 } else {
2946 /* Turn off EEE advertisement. */
2947 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2948 E1000_EEE_ADV_DEV_I354,
2949 &phy_data);
2950 if (ret_val)
2951 goto out;
2952
2953 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2954 E1000_EEE_ADV_1000_SUPPORTED);
2955 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2956 E1000_EEE_ADV_DEV_I354,
2957 phy_data);
2958 }
2959
2960 out:
2961 return ret_val;
2962 }
2963
2964 /**
2965 * e1000_get_eee_status_i354 - Get EEE status
2966 * @hw: pointer to the HW structure
2967 * @status: EEE status
2968 *
2969 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2970 * been received.
2971 **/
e1000_get_eee_status_i354(struct e1000_hw * hw,bool * status)2972 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2973 {
2974 struct e1000_phy_info *phy = &hw->phy;
2975 s32 ret_val = E1000_SUCCESS;
2976 u16 phy_data;
2977
2978 DEBUGFUNC("e1000_get_eee_status_i354");
2979
2980 /* Check if EEE is supported on this device. */
2981 if ((hw->phy.media_type != e1000_media_type_copper) ||
2982 ((phy->id != M88E1543_E_PHY_ID) &&
2983 (phy->id != M88E1512_E_PHY_ID)))
2984 goto out;
2985
2986 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2987 E1000_PCS_STATUS_DEV_I354,
2988 &phy_data);
2989 if (ret_val)
2990 goto out;
2991
2992 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2993 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2994
2995 out:
2996 return ret_val;
2997 }
2998
2999 /* Due to a hw errata, if the host tries to configure the VFTA register
3000 * while performing queries from the BMC or DMA, then the VFTA in some
3001 * cases won't be written.
3002 */
3003
3004 /**
3005 * e1000_clear_vfta_i350 - Clear VLAN filter table
3006 * @hw: pointer to the HW structure
3007 *
3008 * Clears the register array which contains the VLAN filter table by
3009 * setting all the values to 0.
3010 **/
e1000_clear_vfta_i350(struct e1000_hw * hw)3011 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3012 {
3013 u32 offset;
3014 int i;
3015
3016 DEBUGFUNC("e1000_clear_vfta_350");
3017
3018 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3019 for (i = 0; i < 10; i++)
3020 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3021
3022 E1000_WRITE_FLUSH(hw);
3023 }
3024 }
3025
3026 /**
3027 * e1000_write_vfta_i350 - Write value to VLAN filter table
3028 * @hw: pointer to the HW structure
3029 * @offset: register offset in VLAN filter table
3030 * @value: register value written to VLAN filter table
3031 *
3032 * Writes value at the given offset in the register array which stores
3033 * the VLAN filter table.
3034 **/
e1000_write_vfta_i350(struct e1000_hw * hw,u32 offset,u32 value)3035 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3036 {
3037 int i;
3038
3039 DEBUGFUNC("e1000_write_vfta_350");
3040
3041 for (i = 0; i < 10; i++)
3042 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3043
3044 E1000_WRITE_FLUSH(hw);
3045 }
3046
3047
3048 /**
3049 * e1000_set_i2c_bb - Enable I2C bit-bang
3050 * @hw: pointer to the HW structure
3051 *
3052 * Enable I2C bit-bang interface
3053 *
3054 **/
e1000_set_i2c_bb(struct e1000_hw * hw)3055 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3056 {
3057 s32 ret_val = E1000_SUCCESS;
3058 u32 ctrl_ext, i2cparams;
3059
3060 DEBUGFUNC("e1000_set_i2c_bb");
3061
3062 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3063 ctrl_ext |= E1000_CTRL_I2C_ENA;
3064 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3065 E1000_WRITE_FLUSH(hw);
3066
3067 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3068 i2cparams |= E1000_I2CBB_EN;
3069 i2cparams |= E1000_I2C_DATA_OE_N;
3070 i2cparams |= E1000_I2C_CLK_OE_N;
3071 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3072 E1000_WRITE_FLUSH(hw);
3073
3074 return ret_val;
3075 }
3076
3077 /**
3078 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3079 * @hw: pointer to hardware structure
3080 * @byte_offset: byte offset to read
3081 * @dev_addr: device address
3082 * @data: value read
3083 *
3084 * Performs byte read operation over I2C interface at
3085 * a specified device address.
3086 **/
e1000_read_i2c_byte_generic(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)3087 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3088 u8 dev_addr, u8 *data)
3089 {
3090 s32 status = E1000_SUCCESS;
3091 u32 max_retry = 10;
3092 u32 retry = 1;
3093 u16 swfw_mask = 0;
3094
3095 bool nack = true;
3096
3097 DEBUGFUNC("e1000_read_i2c_byte_generic");
3098
3099 swfw_mask = E1000_SWFW_PHY0_SM;
3100
3101 do {
3102 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3103 != E1000_SUCCESS) {
3104 status = E1000_ERR_SWFW_SYNC;
3105 goto read_byte_out;
3106 }
3107
3108 e1000_i2c_start(hw);
3109
3110 /* Device Address and write indication */
3111 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3112 if (status != E1000_SUCCESS)
3113 goto fail;
3114
3115 status = e1000_get_i2c_ack(hw);
3116 if (status != E1000_SUCCESS)
3117 goto fail;
3118
3119 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3120 if (status != E1000_SUCCESS)
3121 goto fail;
3122
3123 status = e1000_get_i2c_ack(hw);
3124 if (status != E1000_SUCCESS)
3125 goto fail;
3126
3127 e1000_i2c_start(hw);
3128
3129 /* Device Address and read indication */
3130 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3131 if (status != E1000_SUCCESS)
3132 goto fail;
3133
3134 status = e1000_get_i2c_ack(hw);
3135 if (status != E1000_SUCCESS)
3136 goto fail;
3137
3138 e1000_clock_in_i2c_byte(hw, data);
3139
3140 status = e1000_clock_out_i2c_bit(hw, nack);
3141 if (status != E1000_SUCCESS)
3142 goto fail;
3143
3144 e1000_i2c_stop(hw);
3145 break;
3146
3147 fail:
3148 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3149 msec_delay(100);
3150 e1000_i2c_bus_clear(hw);
3151 retry++;
3152 if (retry < max_retry)
3153 DEBUGOUT("I2C byte read error - Retrying.\n");
3154 else
3155 DEBUGOUT("I2C byte read error.\n");
3156
3157 } while (retry < max_retry);
3158
3159 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3160
3161 read_byte_out:
3162
3163 return status;
3164 }
3165
3166 /**
3167 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3168 * @hw: pointer to hardware structure
3169 * @byte_offset: byte offset to write
3170 * @dev_addr: device address
3171 * @data: value to write
3172 *
3173 * Performs byte write operation over I2C interface at
3174 * a specified device address.
3175 **/
e1000_write_i2c_byte_generic(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)3176 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3177 u8 dev_addr, u8 data)
3178 {
3179 s32 status = E1000_SUCCESS;
3180 u32 max_retry = 1;
3181 u32 retry = 0;
3182 u16 swfw_mask = 0;
3183
3184 DEBUGFUNC("e1000_write_i2c_byte_generic");
3185
3186 swfw_mask = E1000_SWFW_PHY0_SM;
3187
3188 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3189 status = E1000_ERR_SWFW_SYNC;
3190 goto write_byte_out;
3191 }
3192
3193 do {
3194 e1000_i2c_start(hw);
3195
3196 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3197 if (status != E1000_SUCCESS)
3198 goto fail;
3199
3200 status = e1000_get_i2c_ack(hw);
3201 if (status != E1000_SUCCESS)
3202 goto fail;
3203
3204 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3205 if (status != E1000_SUCCESS)
3206 goto fail;
3207
3208 status = e1000_get_i2c_ack(hw);
3209 if (status != E1000_SUCCESS)
3210 goto fail;
3211
3212 status = e1000_clock_out_i2c_byte(hw, data);
3213 if (status != E1000_SUCCESS)
3214 goto fail;
3215
3216 status = e1000_get_i2c_ack(hw);
3217 if (status != E1000_SUCCESS)
3218 goto fail;
3219
3220 e1000_i2c_stop(hw);
3221 break;
3222
3223 fail:
3224 e1000_i2c_bus_clear(hw);
3225 retry++;
3226 if (retry < max_retry)
3227 DEBUGOUT("I2C byte write error - Retrying.\n");
3228 else
3229 DEBUGOUT("I2C byte write error.\n");
3230 } while (retry < max_retry);
3231
3232 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3233
3234 write_byte_out:
3235
3236 return status;
3237 }
3238
3239 /**
3240 * e1000_i2c_start - Sets I2C start condition
3241 * @hw: pointer to hardware structure
3242 *
3243 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3244 **/
e1000_i2c_start(struct e1000_hw * hw)3245 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3246 {
3247 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3248
3249 DEBUGFUNC("e1000_i2c_start");
3250
3251 /* Start condition must begin with data and clock high */
3252 e1000_set_i2c_data(hw, &i2cctl, 1);
3253 e1000_raise_i2c_clk(hw, &i2cctl);
3254
3255 /* Setup time for start condition (4.7us) */
3256 usec_delay(E1000_I2C_T_SU_STA);
3257
3258 e1000_set_i2c_data(hw, &i2cctl, 0);
3259
3260 /* Hold time for start condition (4us) */
3261 usec_delay(E1000_I2C_T_HD_STA);
3262
3263 e1000_lower_i2c_clk(hw, &i2cctl);
3264
3265 /* Minimum low period of clock is 4.7 us */
3266 usec_delay(E1000_I2C_T_LOW);
3267
3268 }
3269
3270 /**
3271 * e1000_i2c_stop - Sets I2C stop condition
3272 * @hw: pointer to hardware structure
3273 *
3274 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3275 **/
e1000_i2c_stop(struct e1000_hw * hw)3276 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3277 {
3278 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3279
3280 DEBUGFUNC("e1000_i2c_stop");
3281
3282 /* Stop condition must begin with data low and clock high */
3283 e1000_set_i2c_data(hw, &i2cctl, 0);
3284 e1000_raise_i2c_clk(hw, &i2cctl);
3285
3286 /* Setup time for stop condition (4us) */
3287 usec_delay(E1000_I2C_T_SU_STO);
3288
3289 e1000_set_i2c_data(hw, &i2cctl, 1);
3290
3291 /* bus free time between stop and start (4.7us)*/
3292 usec_delay(E1000_I2C_T_BUF);
3293 }
3294
3295 /**
3296 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3297 * @hw: pointer to hardware structure
3298 * @data: data byte to clock in
3299 *
3300 * Clocks in one byte data via I2C data/clock
3301 **/
e1000_clock_in_i2c_byte(struct e1000_hw * hw,u8 * data)3302 STATIC void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3303 {
3304 s32 i;
3305 bool bit = 0;
3306
3307 DEBUGFUNC("e1000_clock_in_i2c_byte");
3308
3309 *data = 0;
3310 for (i = 7; i >= 0; i--) {
3311 e1000_clock_in_i2c_bit(hw, &bit);
3312 *data |= bit << i;
3313 }
3314 }
3315
3316 /**
3317 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3318 * @hw: pointer to hardware structure
3319 * @data: data byte clocked out
3320 *
3321 * Clocks out one byte data via I2C data/clock
3322 **/
e1000_clock_out_i2c_byte(struct e1000_hw * hw,u8 data)3323 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3324 {
3325 s32 status = E1000_SUCCESS;
3326 s32 i;
3327 u32 i2cctl;
3328 bool bit = 0;
3329
3330 DEBUGFUNC("e1000_clock_out_i2c_byte");
3331
3332 for (i = 7; i >= 0; i--) {
3333 bit = (data >> i) & 0x1;
3334 status = e1000_clock_out_i2c_bit(hw, bit);
3335
3336 if (status != E1000_SUCCESS)
3337 break;
3338 }
3339
3340 /* Release SDA line (set high) */
3341 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3342
3343 i2cctl |= E1000_I2C_DATA_OE_N;
3344 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3345 E1000_WRITE_FLUSH(hw);
3346
3347 return status;
3348 }
3349
3350 /**
3351 * e1000_get_i2c_ack - Polls for I2C ACK
3352 * @hw: pointer to hardware structure
3353 *
3354 * Clocks in/out one bit via I2C data/clock
3355 **/
e1000_get_i2c_ack(struct e1000_hw * hw)3356 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3357 {
3358 s32 status = E1000_SUCCESS;
3359 u32 i = 0;
3360 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3361 u32 timeout = 10;
3362 bool ack = true;
3363
3364 DEBUGFUNC("e1000_get_i2c_ack");
3365
3366 e1000_raise_i2c_clk(hw, &i2cctl);
3367
3368 /* Minimum high period of clock is 4us */
3369 usec_delay(E1000_I2C_T_HIGH);
3370
3371 /* Wait until SCL returns high */
3372 for (i = 0; i < timeout; i++) {
3373 usec_delay(1);
3374 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3375 if (i2cctl & E1000_I2C_CLK_IN)
3376 break;
3377 }
3378 if (!(i2cctl & E1000_I2C_CLK_IN))
3379 return E1000_ERR_I2C;
3380
3381 ack = e1000_get_i2c_data(&i2cctl);
3382 if (ack) {
3383 DEBUGOUT("I2C ack was not received.\n");
3384 status = E1000_ERR_I2C;
3385 }
3386
3387 e1000_lower_i2c_clk(hw, &i2cctl);
3388
3389 /* Minimum low period of clock is 4.7 us */
3390 usec_delay(E1000_I2C_T_LOW);
3391
3392 return status;
3393 }
3394
3395 /**
3396 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3397 * @hw: pointer to hardware structure
3398 * @data: read data value
3399 *
3400 * Clocks in one bit via I2C data/clock
3401 **/
e1000_clock_in_i2c_bit(struct e1000_hw * hw,bool * data)3402 STATIC void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3403 {
3404 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3405
3406 DEBUGFUNC("e1000_clock_in_i2c_bit");
3407
3408 e1000_raise_i2c_clk(hw, &i2cctl);
3409
3410 /* Minimum high period of clock is 4us */
3411 usec_delay(E1000_I2C_T_HIGH);
3412
3413 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3414 *data = e1000_get_i2c_data(&i2cctl);
3415
3416 e1000_lower_i2c_clk(hw, &i2cctl);
3417
3418 /* Minimum low period of clock is 4.7 us */
3419 usec_delay(E1000_I2C_T_LOW);
3420 }
3421
3422 /**
3423 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3424 * @hw: pointer to hardware structure
3425 * @data: data value to write
3426 *
3427 * Clocks out one bit via I2C data/clock
3428 **/
e1000_clock_out_i2c_bit(struct e1000_hw * hw,bool data)3429 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3430 {
3431 s32 status;
3432 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3433
3434 DEBUGFUNC("e1000_clock_out_i2c_bit");
3435
3436 status = e1000_set_i2c_data(hw, &i2cctl, data);
3437 if (status == E1000_SUCCESS) {
3438 e1000_raise_i2c_clk(hw, &i2cctl);
3439
3440 /* Minimum high period of clock is 4us */
3441 usec_delay(E1000_I2C_T_HIGH);
3442
3443 e1000_lower_i2c_clk(hw, &i2cctl);
3444
3445 /* Minimum low period of clock is 4.7 us.
3446 * This also takes care of the data hold time.
3447 */
3448 usec_delay(E1000_I2C_T_LOW);
3449 } else {
3450 status = E1000_ERR_I2C;
3451 DEBUGOUT1("I2C data was not set to %X\n", data);
3452 }
3453
3454 return status;
3455 }
3456 /**
3457 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3458 * @hw: pointer to hardware structure
3459 * @i2cctl: Current value of I2CCTL register
3460 *
3461 * Raises the I2C clock line '0'->'1'
3462 **/
e1000_raise_i2c_clk(struct e1000_hw * hw,u32 * i2cctl)3463 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3464 {
3465 DEBUGFUNC("e1000_raise_i2c_clk");
3466
3467 *i2cctl |= E1000_I2C_CLK_OUT;
3468 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3469 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3470 E1000_WRITE_FLUSH(hw);
3471
3472 /* SCL rise time (1000ns) */
3473 usec_delay(E1000_I2C_T_RISE);
3474 }
3475
3476 /**
3477 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3478 * @hw: pointer to hardware structure
3479 * @i2cctl: Current value of I2CCTL register
3480 *
3481 * Lowers the I2C clock line '1'->'0'
3482 **/
e1000_lower_i2c_clk(struct e1000_hw * hw,u32 * i2cctl)3483 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3484 {
3485
3486 DEBUGFUNC("e1000_lower_i2c_clk");
3487
3488 *i2cctl &= ~E1000_I2C_CLK_OUT;
3489 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3490 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3491 E1000_WRITE_FLUSH(hw);
3492
3493 /* SCL fall time (300ns) */
3494 usec_delay(E1000_I2C_T_FALL);
3495 }
3496
3497 /**
3498 * e1000_set_i2c_data - Sets the I2C data bit
3499 * @hw: pointer to hardware structure
3500 * @i2cctl: Current value of I2CCTL register
3501 * @data: I2C data value (0 or 1) to set
3502 *
3503 * Sets the I2C data bit
3504 **/
e1000_set_i2c_data(struct e1000_hw * hw,u32 * i2cctl,bool data)3505 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3506 {
3507 s32 status = E1000_SUCCESS;
3508
3509 DEBUGFUNC("e1000_set_i2c_data");
3510
3511 if (data)
3512 *i2cctl |= E1000_I2C_DATA_OUT;
3513 else
3514 *i2cctl &= ~E1000_I2C_DATA_OUT;
3515
3516 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3517 *i2cctl |= E1000_I2C_CLK_OE_N;
3518 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3519 E1000_WRITE_FLUSH(hw);
3520
3521 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3522 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3523
3524 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3525 if (data != e1000_get_i2c_data(i2cctl)) {
3526 status = E1000_ERR_I2C;
3527 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3528 }
3529
3530 return status;
3531 }
3532
3533 /**
3534 * e1000_get_i2c_data - Reads the I2C SDA data bit
3535 * @i2cctl: Current value of I2CCTL register
3536 *
3537 * Returns the I2C data bit value
3538 **/
e1000_get_i2c_data(u32 * i2cctl)3539 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3540 {
3541 bool data;
3542
3543 DEBUGFUNC("e1000_get_i2c_data");
3544
3545 if (*i2cctl & E1000_I2C_DATA_IN)
3546 data = 1;
3547 else
3548 data = 0;
3549
3550 return data;
3551 }
3552
3553 /**
3554 * e1000_i2c_bus_clear - Clears the I2C bus
3555 * @hw: pointer to hardware structure
3556 *
3557 * Clears the I2C bus by sending nine clock pulses.
3558 * Used when data line is stuck low.
3559 **/
e1000_i2c_bus_clear(struct e1000_hw * hw)3560 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3561 {
3562 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3563 u32 i;
3564
3565 DEBUGFUNC("e1000_i2c_bus_clear");
3566
3567 e1000_i2c_start(hw);
3568
3569 e1000_set_i2c_data(hw, &i2cctl, 1);
3570
3571 for (i = 0; i < 9; i++) {
3572 e1000_raise_i2c_clk(hw, &i2cctl);
3573
3574 /* Min high period of clock is 4us */
3575 usec_delay(E1000_I2C_T_HIGH);
3576
3577 e1000_lower_i2c_clk(hw, &i2cctl);
3578
3579 /* Min low period of clock is 4.7us*/
3580 usec_delay(E1000_I2C_T_LOW);
3581 }
3582
3583 e1000_i2c_start(hw);
3584
3585 /* Put the i2c bus back to default state */
3586 e1000_i2c_stop(hw);
3587 }
3588
3589