1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 /*
6 * 82543GC Gigabit Ethernet Controller (Fiber)
7 * 82543GC Gigabit Ethernet Controller (Copper)
8 * 82544EI Gigabit Ethernet Controller (Copper)
9 * 82544EI Gigabit Ethernet Controller (Fiber)
10 * 82544GC Gigabit Ethernet Controller (Copper)
11 * 82544GC Gigabit Ethernet Controller (LOM)
12 */
13
14 #include "e1000_api.h"
15
16 STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
17 STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
18 STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
19 STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
20 u16 *data);
21 STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
22 u16 data);
23 STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
24 STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
25 STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw);
26 STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw);
27 STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw);
28 STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
29 STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
30 STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
31 STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
32 STATIC s32 e1000_led_on_82543(struct e1000_hw *hw);
33 STATIC s32 e1000_led_off_82543(struct e1000_hw *hw);
34 STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
35 u32 value);
36 STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
37 STATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
38 STATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
39 STATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
40 STATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
41 STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
42 STATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
43 STATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
44 u16 count);
45 STATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
46 STATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
47
48 /**
49 * e1000_init_phy_params_82543 - Init PHY func ptrs.
50 * @hw: pointer to the HW structure
51 **/
e1000_init_phy_params_82543(struct e1000_hw * hw)52 STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
53 {
54 struct e1000_phy_info *phy = &hw->phy;
55 s32 ret_val = E1000_SUCCESS;
56
57 DEBUGFUNC("e1000_init_phy_params_82543");
58
59 if (hw->phy.media_type != e1000_media_type_copper) {
60 phy->type = e1000_phy_none;
61 goto out;
62 } else {
63 phy->ops.power_up = e1000_power_up_phy_copper;
64 phy->ops.power_down = e1000_power_down_phy_copper;
65 }
66
67 phy->addr = 1;
68 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
69 phy->reset_delay_us = 10000;
70 phy->type = e1000_phy_m88;
71
72 /* Function Pointers */
73 phy->ops.check_polarity = e1000_check_polarity_m88;
74 phy->ops.commit = e1000_phy_sw_reset_generic;
75 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
76 phy->ops.get_cable_length = e1000_get_cable_length_m88;
77 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
78 phy->ops.read_reg = (hw->mac.type == e1000_82543)
79 ? e1000_read_phy_reg_82543
80 : e1000_read_phy_reg_m88;
81 phy->ops.reset = (hw->mac.type == e1000_82543)
82 ? e1000_phy_hw_reset_82543
83 : e1000_phy_hw_reset_generic;
84 phy->ops.write_reg = (hw->mac.type == e1000_82543)
85 ? e1000_write_phy_reg_82543
86 : e1000_write_phy_reg_m88;
87 phy->ops.get_info = e1000_get_phy_info_m88;
88
89 /*
90 * The external PHY of the 82543 can be in a funky state.
91 * Resetting helps us read the PHY registers for acquiring
92 * the PHY ID.
93 */
94 if (!e1000_init_phy_disabled_82543(hw)) {
95 ret_val = phy->ops.reset(hw);
96 if (ret_val) {
97 DEBUGOUT("Resetting PHY during init failed.\n");
98 goto out;
99 }
100 msec_delay(20);
101 }
102
103 ret_val = e1000_get_phy_id(hw);
104 if (ret_val)
105 goto out;
106
107 /* Verify phy id */
108 switch (hw->mac.type) {
109 case e1000_82543:
110 if (phy->id != M88E1000_E_PHY_ID) {
111 ret_val = -E1000_ERR_PHY;
112 goto out;
113 }
114 break;
115 case e1000_82544:
116 if (phy->id != M88E1000_I_PHY_ID) {
117 ret_val = -E1000_ERR_PHY;
118 goto out;
119 }
120 break;
121 default:
122 ret_val = -E1000_ERR_PHY;
123 goto out;
124 break;
125 }
126
127 out:
128 return ret_val;
129 }
130
131 /**
132 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
133 * @hw: pointer to the HW structure
134 **/
e1000_init_nvm_params_82543(struct e1000_hw * hw)135 STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
136 {
137 struct e1000_nvm_info *nvm = &hw->nvm;
138
139 DEBUGFUNC("e1000_init_nvm_params_82543");
140
141 nvm->type = e1000_nvm_eeprom_microwire;
142 nvm->word_size = 64;
143 nvm->delay_usec = 50;
144 nvm->address_bits = 6;
145 nvm->opcode_bits = 3;
146
147 /* Function Pointers */
148 nvm->ops.read = e1000_read_nvm_microwire;
149 nvm->ops.update = e1000_update_nvm_checksum_generic;
150 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
151 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
152 nvm->ops.write = e1000_write_nvm_microwire;
153
154 return E1000_SUCCESS;
155 }
156
157 /**
158 * e1000_init_mac_params_82543 - Init MAC func ptrs.
159 * @hw: pointer to the HW structure
160 **/
e1000_init_mac_params_82543(struct e1000_hw * hw)161 STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
162 {
163 struct e1000_mac_info *mac = &hw->mac;
164
165 DEBUGFUNC("e1000_init_mac_params_82543");
166
167 /* Set media type */
168 switch (hw->device_id) {
169 case E1000_DEV_ID_82543GC_FIBER:
170 case E1000_DEV_ID_82544EI_FIBER:
171 hw->phy.media_type = e1000_media_type_fiber;
172 break;
173 default:
174 hw->phy.media_type = e1000_media_type_copper;
175 break;
176 }
177
178 /* Set mta register count */
179 mac->mta_reg_count = 128;
180 /* Set rar entry count */
181 mac->rar_entry_count = E1000_RAR_ENTRIES;
182
183 /* Function pointers */
184
185 /* bus type/speed/width */
186 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
187 /* function id */
188 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
189 /* reset */
190 mac->ops.reset_hw = e1000_reset_hw_82543;
191 /* hw initialization */
192 mac->ops.init_hw = e1000_init_hw_82543;
193 /* link setup */
194 mac->ops.setup_link = e1000_setup_link_82543;
195 /* physical interface setup */
196 mac->ops.setup_physical_interface =
197 (hw->phy.media_type == e1000_media_type_copper)
198 ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543;
199 /* check for link */
200 mac->ops.check_for_link =
201 (hw->phy.media_type == e1000_media_type_copper)
202 ? e1000_check_for_copper_link_82543
203 : e1000_check_for_fiber_link_82543;
204 /* link info */
205 mac->ops.get_link_up_info =
206 (hw->phy.media_type == e1000_media_type_copper)
207 ? e1000_get_speed_and_duplex_copper_generic
208 : e1000_get_speed_and_duplex_fiber_serdes_generic;
209 /* multicast address update */
210 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
211 /* writing VFTA */
212 mac->ops.write_vfta = e1000_write_vfta_82543;
213 /* clearing VFTA */
214 mac->ops.clear_vfta = e1000_clear_vfta_generic;
215 /* turn on/off LED */
216 mac->ops.led_on = e1000_led_on_82543;
217 mac->ops.led_off = e1000_led_off_82543;
218 /* clear hardware counters */
219 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
220
221 /* Set tbi compatibility */
222 if ((hw->mac.type != e1000_82543) ||
223 (hw->phy.media_type == e1000_media_type_fiber))
224 e1000_set_tbi_compatibility_82543(hw, false);
225
226 return E1000_SUCCESS;
227 }
228
229 /**
230 * e1000_init_function_pointers_82543 - Init func ptrs.
231 * @hw: pointer to the HW structure
232 *
233 * Called to initialize all function pointers and parameters.
234 **/
e1000_init_function_pointers_82543(struct e1000_hw * hw)235 void e1000_init_function_pointers_82543(struct e1000_hw *hw)
236 {
237 DEBUGFUNC("e1000_init_function_pointers_82543");
238
239 hw->mac.ops.init_params = e1000_init_mac_params_82543;
240 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
241 hw->phy.ops.init_params = e1000_init_phy_params_82543;
242 }
243
244 /**
245 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
246 * @hw: pointer to the HW structure
247 *
248 * Returns the current status of 10-bit Interface (TBI) compatibility
249 * (enabled/disabled).
250 **/
e1000_tbi_compatibility_enabled_82543(struct e1000_hw * hw)251 STATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
252 {
253 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
254 bool state = false;
255
256 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
257
258 if (hw->mac.type != e1000_82543) {
259 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
260 goto out;
261 }
262
263 state = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED);
264
265 out:
266 return state;
267 }
268
269 /**
270 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
271 * @hw: pointer to the HW structure
272 * @state: enable/disable TBI compatibility
273 *
274 * Enables or disabled 10-bit Interface (TBI) compatibility.
275 **/
e1000_set_tbi_compatibility_82543(struct e1000_hw * hw,bool state)276 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
277 {
278 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
279
280 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
281
282 if (hw->mac.type != e1000_82543) {
283 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
284 goto out;
285 }
286
287 if (state)
288 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
289 else
290 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
291
292 out:
293 return;
294 }
295
296 /**
297 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
298 * @hw: pointer to the HW structure
299 *
300 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
301 * (enabled/disabled).
302 **/
e1000_tbi_sbp_enabled_82543(struct e1000_hw * hw)303 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
304 {
305 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
306 bool state = false;
307
308 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
309
310 if (hw->mac.type != e1000_82543) {
311 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
312 goto out;
313 }
314
315 state = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED);
316
317 out:
318 return state;
319 }
320
321 /**
322 * e1000_set_tbi_sbp_82543 - Set TBI SBP
323 * @hw: pointer to the HW structure
324 * @state: enable/disable TBI store bad packet
325 *
326 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
327 **/
e1000_set_tbi_sbp_82543(struct e1000_hw * hw,bool state)328 STATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
329 {
330 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
331
332 DEBUGFUNC("e1000_set_tbi_sbp_82543");
333
334 if (state && e1000_tbi_compatibility_enabled_82543(hw))
335 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
336 else
337 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
338
339 return;
340 }
341
342 /**
343 * e1000_init_phy_disabled_82543 - Returns init PHY status
344 * @hw: pointer to the HW structure
345 *
346 * Returns the current status of whether PHY initialization is disabled.
347 * True if PHY initialization is disabled else false.
348 **/
e1000_init_phy_disabled_82543(struct e1000_hw * hw)349 STATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
350 {
351 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
352 bool ret_val;
353
354 DEBUGFUNC("e1000_init_phy_disabled_82543");
355
356 if (hw->mac.type != e1000_82543) {
357 ret_val = false;
358 goto out;
359 }
360
361 ret_val = dev_spec->init_phy_disabled;
362
363 out:
364 return ret_val;
365 }
366
367 /**
368 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
369 * @hw: pointer to the HW structure
370 * @stats: Struct containing statistic register values
371 * @frame_len: The length of the frame in question
372 * @mac_addr: The Ethernet destination address of the frame in question
373 * @max_frame_size: The maximum frame size
374 *
375 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
376 **/
e1000_tbi_adjust_stats_82543(struct e1000_hw * hw,struct e1000_hw_stats * stats,u32 frame_len,u8 * mac_addr,u32 max_frame_size)377 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
378 struct e1000_hw_stats *stats, u32 frame_len,
379 u8 *mac_addr, u32 max_frame_size)
380 {
381 if (!(e1000_tbi_sbp_enabled_82543(hw)))
382 goto out;
383
384 /* First adjust the frame length. */
385 frame_len--;
386 /*
387 * We need to adjust the statistics counters, since the hardware
388 * counters overcount this packet as a CRC error and undercount
389 * the packet as a good packet
390 */
391 /* This packet should not be counted as a CRC error. */
392 stats->crcerrs--;
393 /* This packet does count as a Good Packet Received. */
394 stats->gprc++;
395
396 /* Adjust the Good Octets received counters */
397 stats->gorc += frame_len;
398
399 /*
400 * Is this a broadcast or multicast? Check broadcast first,
401 * since the test for a multicast frame will test positive on
402 * a broadcast frame.
403 */
404 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
405 /* Broadcast packet */
406 stats->bprc++;
407 else if (*mac_addr & 0x01)
408 /* Multicast packet */
409 stats->mprc++;
410
411 /*
412 * In this case, the hardware has over counted the number of
413 * oversize frames.
414 */
415 if ((frame_len == max_frame_size) && (stats->roc > 0))
416 stats->roc--;
417
418 /*
419 * Adjust the bin counters when the extra byte put the frame in the
420 * wrong bin. Remember that the frame_len was adjusted above.
421 */
422 if (frame_len == 64) {
423 stats->prc64++;
424 stats->prc127--;
425 } else if (frame_len == 127) {
426 stats->prc127++;
427 stats->prc255--;
428 } else if (frame_len == 255) {
429 stats->prc255++;
430 stats->prc511--;
431 } else if (frame_len == 511) {
432 stats->prc511++;
433 stats->prc1023--;
434 } else if (frame_len == 1023) {
435 stats->prc1023++;
436 stats->prc1522--;
437 } else if (frame_len == 1522) {
438 stats->prc1522++;
439 }
440
441 out:
442 return;
443 }
444
445 /**
446 * e1000_read_phy_reg_82543 - Read PHY register
447 * @hw: pointer to the HW structure
448 * @offset: register offset to be read
449 * @data: pointer to the read data
450 *
451 * Reads the PHY at offset and stores the information read to data.
452 **/
e1000_read_phy_reg_82543(struct e1000_hw * hw,u32 offset,u16 * data)453 STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
454 {
455 u32 mdic;
456 s32 ret_val = E1000_SUCCESS;
457
458 DEBUGFUNC("e1000_read_phy_reg_82543");
459
460 if (offset > MAX_PHY_REG_ADDRESS) {
461 DEBUGOUT1("PHY Address %d is out of range\n", offset);
462 ret_val = -E1000_ERR_PARAM;
463 goto out;
464 }
465
466 /*
467 * We must first send a preamble through the MDIO pin to signal the
468 * beginning of an MII instruction. This is done by sending 32
469 * consecutive "1" bits.
470 */
471 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
472
473 /*
474 * Now combine the next few fields that are required for a read
475 * operation. We use this method instead of calling the
476 * e1000_shift_out_mdi_bits routine five different times. The format
477 * of an MII read instruction consists of a shift out of 14 bits and
478 * is defined as follows:
479 * <Preamble><SOF><Op Code><Phy Addr><Offset>
480 * followed by a shift in of 18 bits. This first two bits shifted in
481 * are TurnAround bits used to avoid contention on the MDIO pin when a
482 * READ operation is performed. These two bits are thrown away
483 * followed by a shift in of 16 bits which contains the desired data.
484 */
485 mdic = (offset | (hw->phy.addr << 5) |
486 (PHY_OP_READ << 10) | (PHY_SOF << 12));
487
488 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
489
490 /*
491 * Now that we've shifted out the read command to the MII, we need to
492 * "shift in" the 16-bit value (18 total bits) of the requested PHY
493 * register address.
494 */
495 *data = e1000_shift_in_mdi_bits_82543(hw);
496
497 out:
498 return ret_val;
499 }
500
501 /**
502 * e1000_write_phy_reg_82543 - Write PHY register
503 * @hw: pointer to the HW structure
504 * @offset: register offset to be written
505 * @data: pointer to the data to be written at offset
506 *
507 * Writes data to the PHY at offset.
508 **/
e1000_write_phy_reg_82543(struct e1000_hw * hw,u32 offset,u16 data)509 STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
510 {
511 u32 mdic;
512 s32 ret_val = E1000_SUCCESS;
513
514 DEBUGFUNC("e1000_write_phy_reg_82543");
515
516 if (offset > MAX_PHY_REG_ADDRESS) {
517 DEBUGOUT1("PHY Address %d is out of range\n", offset);
518 ret_val = -E1000_ERR_PARAM;
519 goto out;
520 }
521
522 /*
523 * We'll need to use the SW defined pins to shift the write command
524 * out to the PHY. We first send a preamble to the PHY to signal the
525 * beginning of the MII instruction. This is done by sending 32
526 * consecutive "1" bits.
527 */
528 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
529
530 /*
531 * Now combine the remaining required fields that will indicate a
532 * write operation. We use this method instead of calling the
533 * e1000_shift_out_mdi_bits routine for each field in the command. The
534 * format of a MII write instruction is as follows:
535 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
536 */
537 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
538 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
539 mdic <<= 16;
540 mdic |= (u32)data;
541
542 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
543
544 out:
545 return ret_val;
546 }
547
548 /**
549 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
550 * @hw: pointer to the HW structure
551 * @ctrl: pointer to the control register
552 *
553 * Raise the management data input clock by setting the MDC bit in the control
554 * register.
555 **/
e1000_raise_mdi_clk_82543(struct e1000_hw * hw,u32 * ctrl)556 STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
557 {
558 /*
559 * Raise the clock input to the Management Data Clock (by setting the
560 * MDC bit), and then delay a sufficient amount of time.
561 */
562 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
563 E1000_WRITE_FLUSH(hw);
564 usec_delay(10);
565 }
566
567 /**
568 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
569 * @hw: pointer to the HW structure
570 * @ctrl: pointer to the control register
571 *
572 * Lower the management data input clock by clearing the MDC bit in the
573 * control register.
574 **/
e1000_lower_mdi_clk_82543(struct e1000_hw * hw,u32 * ctrl)575 STATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
576 {
577 /*
578 * Lower the clock input to the Management Data Clock (by clearing the
579 * MDC bit), and then delay a sufficient amount of time.
580 */
581 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
582 E1000_WRITE_FLUSH(hw);
583 usec_delay(10);
584 }
585
586 /**
587 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
588 * @hw: pointer to the HW structure
589 * @data: data to send to the PHY
590 * @count: number of bits to shift out
591 *
592 * We need to shift 'count' bits out to the PHY. So, the value in the
593 * "data" parameter will be shifted out to the PHY one bit at a time.
594 * In order to do this, "data" must be broken down into bits.
595 **/
e1000_shift_out_mdi_bits_82543(struct e1000_hw * hw,u32 data,u16 count)596 STATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
597 u16 count)
598 {
599 u32 ctrl, mask;
600
601 /*
602 * We need to shift "count" number of bits out to the PHY. So, the
603 * value in the "data" parameter will be shifted out to the PHY one
604 * bit at a time. In order to do this, "data" must be broken down
605 * into bits.
606 */
607 mask = 0x01;
608 mask <<= (count - 1);
609
610 ctrl = E1000_READ_REG(hw, E1000_CTRL);
611
612 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
613 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
614
615 while (mask) {
616 /*
617 * A "1" is shifted out to the PHY by setting the MDIO bit to
618 * "1" and then raising and lowering the Management Data Clock.
619 * A "0" is shifted out to the PHY by setting the MDIO bit to
620 * "0" and then raising and lowering the clock.
621 */
622 if (data & mask)
623 ctrl |= E1000_CTRL_MDIO;
624 else
625 ctrl &= ~E1000_CTRL_MDIO;
626
627 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
628 E1000_WRITE_FLUSH(hw);
629
630 usec_delay(10);
631
632 e1000_raise_mdi_clk_82543(hw, &ctrl);
633 e1000_lower_mdi_clk_82543(hw, &ctrl);
634
635 mask >>= 1;
636 }
637 }
638
639 /**
640 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
641 * @hw: pointer to the HW structure
642 *
643 * In order to read a register from the PHY, we need to shift 18 bits
644 * in from the PHY. Bits are "shifted in" by raising the clock input to
645 * the PHY (setting the MDC bit), and then reading the value of the data out
646 * MDIO bit.
647 **/
e1000_shift_in_mdi_bits_82543(struct e1000_hw * hw)648 STATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
649 {
650 u32 ctrl;
651 u16 data = 0;
652 u8 i;
653
654 /*
655 * In order to read a register from the PHY, we need to shift in a
656 * total of 18 bits from the PHY. The first two bit (turnaround)
657 * times are used to avoid contention on the MDIO pin when a read
658 * operation is performed. These two bits are ignored by us and
659 * thrown away. Bits are "shifted in" by raising the input to the
660 * Management Data Clock (setting the MDC bit) and then reading the
661 * value of the MDIO bit.
662 */
663 ctrl = E1000_READ_REG(hw, E1000_CTRL);
664
665 /*
666 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
667 * input.
668 */
669 ctrl &= ~E1000_CTRL_MDIO_DIR;
670 ctrl &= ~E1000_CTRL_MDIO;
671
672 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
673 E1000_WRITE_FLUSH(hw);
674
675 /*
676 * Raise and lower the clock before reading in the data. This accounts
677 * for the turnaround bits. The first clock occurred when we clocked
678 * out the last bit of the Register Address.
679 */
680 e1000_raise_mdi_clk_82543(hw, &ctrl);
681 e1000_lower_mdi_clk_82543(hw, &ctrl);
682
683 for (data = 0, i = 0; i < 16; i++) {
684 data <<= 1;
685 e1000_raise_mdi_clk_82543(hw, &ctrl);
686 ctrl = E1000_READ_REG(hw, E1000_CTRL);
687 /* Check to see if we shifted in a "1". */
688 if (ctrl & E1000_CTRL_MDIO)
689 data |= 1;
690 e1000_lower_mdi_clk_82543(hw, &ctrl);
691 }
692
693 e1000_raise_mdi_clk_82543(hw, &ctrl);
694 e1000_lower_mdi_clk_82543(hw, &ctrl);
695
696 return data;
697 }
698
699 /**
700 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
701 * @hw: pointer to the HW structure
702 *
703 * Calls the function to force speed and duplex for the m88 PHY, and
704 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
705 * then call the function for polarity reversal workaround.
706 **/
e1000_phy_force_speed_duplex_82543(struct e1000_hw * hw)707 STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
708 {
709 s32 ret_val;
710
711 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
712
713 ret_val = e1000_phy_force_speed_duplex_m88(hw);
714 if (ret_val)
715 goto out;
716
717 if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex &
718 E1000_ALL_10_SPEED))
719 ret_val = e1000_polarity_reversal_workaround_82543(hw);
720
721 out:
722 return ret_val;
723 }
724
725 /**
726 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
727 * @hw: pointer to the HW structure
728 *
729 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
730 * inadvertently. To workaround the issue, we disable the transmitter on
731 * the PHY until we have established the link partner's link parameters.
732 **/
e1000_polarity_reversal_workaround_82543(struct e1000_hw * hw)733 STATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
734 {
735 s32 ret_val = E1000_SUCCESS;
736 u16 mii_status_reg;
737 u16 i;
738 bool link;
739
740 if (!(hw->phy.ops.write_reg))
741 goto out;
742
743 /* Polarity reversal workaround for forced 10F/10H links. */
744
745 /* Disable the transmitter on the PHY */
746
747 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
748 if (ret_val)
749 goto out;
750 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
751 if (ret_val)
752 goto out;
753
754 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
755 if (ret_val)
756 goto out;
757
758 /*
759 * This loop will early-out if the NO link condition has been met.
760 * In other words, DO NOT use e1000_phy_has_link_generic() here.
761 */
762 for (i = PHY_FORCE_TIME; i > 0; i--) {
763 /*
764 * Read the MII Status Register and wait for Link Status bit
765 * to be clear.
766 */
767
768 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
769 if (ret_val)
770 goto out;
771
772 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
773 if (ret_val)
774 goto out;
775
776 if (!(mii_status_reg & ~MII_SR_LINK_STATUS))
777 break;
778 msec_delay_irq(100);
779 }
780
781 /* Recommended delay time after link has been lost */
782 msec_delay_irq(1000);
783
784 /* Now we will re-enable the transmitter on the PHY */
785
786 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
787 if (ret_val)
788 goto out;
789 msec_delay_irq(50);
790 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
791 if (ret_val)
792 goto out;
793 msec_delay_irq(50);
794 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
795 if (ret_val)
796 goto out;
797 msec_delay_irq(50);
798 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
799 if (ret_val)
800 goto out;
801
802 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
803 if (ret_val)
804 goto out;
805
806 /*
807 * Read the MII Status Register and wait for Link Status bit
808 * to be set.
809 */
810 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
811 if (ret_val)
812 goto out;
813
814 out:
815 return ret_val;
816 }
817
818 /**
819 * e1000_phy_hw_reset_82543 - PHY hardware reset
820 * @hw: pointer to the HW structure
821 *
822 * Sets the PHY_RESET_DIR bit in the extended device control register
823 * to put the PHY into a reset and waits for completion. Once the reset
824 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
825 * of reset.
826 **/
e1000_phy_hw_reset_82543(struct e1000_hw * hw)827 STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
828 {
829 u32 ctrl_ext;
830 s32 ret_val;
831
832 DEBUGFUNC("e1000_phy_hw_reset_82543");
833
834 /*
835 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
836 * bit to put the PHY into reset...
837 */
838 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
839 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
840 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
841 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
842 E1000_WRITE_FLUSH(hw);
843
844 msec_delay(10);
845
846 /* ...then take it out of reset. */
847 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
848 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
849 E1000_WRITE_FLUSH(hw);
850
851 usec_delay(150);
852
853 if (!(hw->phy.ops.get_cfg_done))
854 return E1000_SUCCESS;
855
856 ret_val = hw->phy.ops.get_cfg_done(hw);
857
858 return ret_val;
859 }
860
861 /**
862 * e1000_reset_hw_82543 - Reset hardware
863 * @hw: pointer to the HW structure
864 *
865 * This resets the hardware into a known state.
866 **/
e1000_reset_hw_82543(struct e1000_hw * hw)867 STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw)
868 {
869 u32 ctrl;
870 s32 ret_val = E1000_SUCCESS;
871
872 DEBUGFUNC("e1000_reset_hw_82543");
873
874 DEBUGOUT("Masking off all interrupts\n");
875 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
876
877 E1000_WRITE_REG(hw, E1000_RCTL, 0);
878 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
879 E1000_WRITE_FLUSH(hw);
880
881 e1000_set_tbi_sbp_82543(hw, false);
882
883 /*
884 * Delay to allow any outstanding PCI transactions to complete before
885 * resetting the device
886 */
887 msec_delay(10);
888
889 ctrl = E1000_READ_REG(hw, E1000_CTRL);
890
891 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
892 if (hw->mac.type == e1000_82543) {
893 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
894 } else {
895 /*
896 * The 82544 can't ACK the 64-bit write when issuing the
897 * reset, so use IO-mapping as a workaround.
898 */
899 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
900 }
901
902 /*
903 * After MAC reset, force reload of NVM to restore power-on
904 * settings to device.
905 */
906 hw->nvm.ops.reload(hw);
907 msec_delay(2);
908
909 /* Masking off and clearing any pending interrupts */
910 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
911 E1000_READ_REG(hw, E1000_ICR);
912
913 return ret_val;
914 }
915
916 /**
917 * e1000_init_hw_82543 - Initialize hardware
918 * @hw: pointer to the HW structure
919 *
920 * This inits the hardware readying it for operation.
921 **/
e1000_init_hw_82543(struct e1000_hw * hw)922 STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw)
923 {
924 struct e1000_mac_info *mac = &hw->mac;
925 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
926 u32 ctrl;
927 s32 ret_val;
928 u16 i;
929
930 DEBUGFUNC("e1000_init_hw_82543");
931
932 /* Disabling VLAN filtering */
933 E1000_WRITE_REG(hw, E1000_VET, 0);
934 mac->ops.clear_vfta(hw);
935
936 /* Setup the receive address. */
937 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
938
939 /* Zero out the Multicast HASH table */
940 DEBUGOUT("Zeroing the MTA\n");
941 for (i = 0; i < mac->mta_reg_count; i++) {
942 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
943 E1000_WRITE_FLUSH(hw);
944 }
945
946 /*
947 * Set the PCI priority bit correctly in the CTRL register. This
948 * determines if the adapter gives priority to receives, or if it
949 * gives equal priority to transmits and receives.
950 */
951 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
952 ctrl = E1000_READ_REG(hw, E1000_CTRL);
953 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
954 }
955
956 e1000_pcix_mmrbc_workaround_generic(hw);
957
958 /* Setup link and flow control */
959 ret_val = mac->ops.setup_link(hw);
960
961 /*
962 * Clear all of the statistics registers (clear on read). It is
963 * important that we do this after we have tried to establish link
964 * because the symbol error count will increment wildly if there
965 * is no link.
966 */
967 e1000_clear_hw_cntrs_82543(hw);
968
969 return ret_val;
970 }
971
972 /**
973 * e1000_setup_link_82543 - Setup flow control and link settings
974 * @hw: pointer to the HW structure
975 *
976 * Read the EEPROM to determine the initial polarity value and write the
977 * extended device control register with the information before calling
978 * the generic setup link function, which does the following:
979 * Determines which flow control settings to use, then configures flow
980 * control. Calls the appropriate media-specific link configuration
981 * function. Assuming the adapter has a valid link partner, a valid link
982 * should be established. Assumes the hardware has previously been reset
983 * and the transmitter and receiver are not enabled.
984 **/
e1000_setup_link_82543(struct e1000_hw * hw)985 STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw)
986 {
987 u32 ctrl_ext;
988 s32 ret_val;
989 u16 data;
990
991 DEBUGFUNC("e1000_setup_link_82543");
992
993 /*
994 * Take the 4 bits from NVM word 0xF that determine the initial
995 * polarity value for the SW controlled pins, and setup the
996 * Extended Device Control reg with that info.
997 * This is needed because one of the SW controlled pins is used for
998 * signal detection. So this should be done before phy setup.
999 */
1000 if (hw->mac.type == e1000_82543) {
1001 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1002 if (ret_val) {
1003 DEBUGOUT("NVM Read Error\n");
1004 ret_val = -E1000_ERR_NVM;
1005 goto out;
1006 }
1007 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1008 NVM_SWDPIO_EXT_SHIFT);
1009 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1010 }
1011
1012 ret_val = e1000_setup_link_generic(hw);
1013
1014 out:
1015 return ret_val;
1016 }
1017
1018 /**
1019 * e1000_setup_copper_link_82543 - Configure copper link settings
1020 * @hw: pointer to the HW structure
1021 *
1022 * Configures the link for auto-neg or forced speed and duplex. Then we check
1023 * for link, once link is established calls to configure collision distance
1024 * and flow control are called.
1025 **/
e1000_setup_copper_link_82543(struct e1000_hw * hw)1026 STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1027 {
1028 u32 ctrl;
1029 s32 ret_val;
1030 bool link = true;
1031
1032 DEBUGFUNC("e1000_setup_copper_link_82543");
1033
1034 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1035 /*
1036 * With 82543, we need to force speed and duplex on the MAC
1037 * equal to what the PHY speed and duplex configuration is.
1038 * In addition, we need to perform a hardware reset on the
1039 * PHY to take it out of reset.
1040 */
1041 if (hw->mac.type == e1000_82543) {
1042 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1043 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1044 ret_val = hw->phy.ops.reset(hw);
1045 if (ret_val)
1046 goto out;
1047 } else {
1048 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1049 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1050 }
1051
1052 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1053 ret_val = e1000_copper_link_setup_m88(hw);
1054 if (ret_val)
1055 goto out;
1056
1057 if (hw->mac.autoneg) {
1058 /*
1059 * Setup autoneg and flow control advertisement and perform
1060 * autonegotiation.
1061 */
1062 ret_val = e1000_copper_link_autoneg(hw);
1063 if (ret_val)
1064 goto out;
1065 } else {
1066 /*
1067 * PHY will be set to 10H, 10F, 100H or 100F
1068 * depending on user settings.
1069 */
1070 DEBUGOUT("Forcing Speed and Duplex\n");
1071 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1072 if (ret_val) {
1073 DEBUGOUT("Error Forcing Speed and Duplex\n");
1074 goto out;
1075 }
1076 }
1077
1078 /*
1079 * Check link status. Wait up to 100 microseconds for link to become
1080 * valid.
1081 */
1082 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1083 &link);
1084 if (ret_val)
1085 goto out;
1086
1087
1088 if (link) {
1089 DEBUGOUT("Valid link established!!!\n");
1090 /* Config the MAC and PHY after link is up */
1091 if (hw->mac.type == e1000_82544) {
1092 hw->mac.ops.config_collision_dist(hw);
1093 } else {
1094 ret_val = e1000_config_mac_to_phy_82543(hw);
1095 if (ret_val)
1096 goto out;
1097 }
1098 ret_val = e1000_config_fc_after_link_up_generic(hw);
1099 } else {
1100 DEBUGOUT("Unable to establish link!!!\n");
1101 }
1102
1103 out:
1104 return ret_val;
1105 }
1106
1107 /**
1108 * e1000_setup_fiber_link_82543 - Setup link for fiber
1109 * @hw: pointer to the HW structure
1110 *
1111 * Configures collision distance and flow control for fiber links. Upon
1112 * successful setup, poll for link.
1113 **/
e1000_setup_fiber_link_82543(struct e1000_hw * hw)1114 STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1115 {
1116 u32 ctrl;
1117 s32 ret_val;
1118
1119 DEBUGFUNC("e1000_setup_fiber_link_82543");
1120
1121 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1122
1123 /* Take the link out of reset */
1124 ctrl &= ~E1000_CTRL_LRST;
1125
1126 hw->mac.ops.config_collision_dist(hw);
1127
1128 ret_val = e1000_commit_fc_settings_generic(hw);
1129 if (ret_val)
1130 goto out;
1131
1132 DEBUGOUT("Auto-negotiation enabled\n");
1133
1134 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1135 E1000_WRITE_FLUSH(hw);
1136 msec_delay(1);
1137
1138 /*
1139 * For these adapters, the SW definable pin 1 is cleared when the
1140 * optics detect a signal. If we have a signal, then poll for a
1141 * "Link-Up" indication.
1142 */
1143 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1))
1144 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1145 else
1146 DEBUGOUT("No signal detected\n");
1147
1148 out:
1149 return ret_val;
1150 }
1151
1152 /**
1153 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1154 * @hw: pointer to the HW structure
1155 *
1156 * Checks the phy for link, if link exists, do the following:
1157 * - check for downshift
1158 * - do polarity workaround (if necessary)
1159 * - configure collision distance
1160 * - configure flow control after link up
1161 * - configure tbi compatibility
1162 **/
e1000_check_for_copper_link_82543(struct e1000_hw * hw)1163 STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1164 {
1165 struct e1000_mac_info *mac = &hw->mac;
1166 u32 icr, rctl;
1167 s32 ret_val;
1168 u16 speed, duplex;
1169 bool link;
1170
1171 DEBUGFUNC("e1000_check_for_copper_link_82543");
1172
1173 if (!mac->get_link_status) {
1174 ret_val = E1000_SUCCESS;
1175 goto out;
1176 }
1177
1178 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1179 if (ret_val)
1180 goto out;
1181
1182 if (!link)
1183 goto out; /* No link detected */
1184
1185 mac->get_link_status = false;
1186
1187 e1000_check_downshift_generic(hw);
1188
1189 /*
1190 * If we are forcing speed/duplex, then we can return since
1191 * we have already determined whether we have link or not.
1192 */
1193 if (!mac->autoneg) {
1194 /*
1195 * If speed and duplex are forced to 10H or 10F, then we will
1196 * implement the polarity reversal workaround. We disable
1197 * interrupts first, and upon returning, place the devices
1198 * interrupt state to its previous value except for the link
1199 * status change interrupt which will happened due to the
1200 * execution of this workaround.
1201 */
1202 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1203 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1204 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1205 icr = E1000_READ_REG(hw, E1000_ICR);
1206 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1207 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1208 }
1209
1210 ret_val = -E1000_ERR_CONFIG;
1211 goto out;
1212 }
1213
1214 /*
1215 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1216 * have Si on board that is 82544 or newer, Auto
1217 * Speed Detection takes care of MAC speed/duplex
1218 * configuration. So we only need to configure Collision
1219 * Distance in the MAC. Otherwise, we need to force
1220 * speed/duplex on the MAC to the current PHY speed/duplex
1221 * settings.
1222 */
1223 if (mac->type == e1000_82544)
1224 hw->mac.ops.config_collision_dist(hw);
1225 else {
1226 ret_val = e1000_config_mac_to_phy_82543(hw);
1227 if (ret_val) {
1228 DEBUGOUT("Error configuring MAC to PHY settings\n");
1229 goto out;
1230 }
1231 }
1232
1233 /*
1234 * Configure Flow Control now that Auto-Neg has completed.
1235 * First, we need to restore the desired flow control
1236 * settings because we may have had to re-autoneg with a
1237 * different link partner.
1238 */
1239 ret_val = e1000_config_fc_after_link_up_generic(hw);
1240 if (ret_val)
1241 DEBUGOUT("Error configuring flow control\n");
1242
1243 /*
1244 * At this point we know that we are on copper and we have
1245 * auto-negotiated link. These are conditions for checking the link
1246 * partner capability register. We use the link speed to determine if
1247 * TBI compatibility needs to be turned on or off. If the link is not
1248 * at gigabit speed, then TBI compatibility is not needed. If we are
1249 * at gigabit speed, we turn on TBI compatibility.
1250 */
1251 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1252 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1253 if (ret_val) {
1254 DEBUGOUT("Error getting link speed and duplex\n");
1255 return ret_val;
1256 }
1257 if (speed != SPEED_1000) {
1258 /*
1259 * If link speed is not set to gigabit speed,
1260 * we do not need to enable TBI compatibility.
1261 */
1262 if (e1000_tbi_sbp_enabled_82543(hw)) {
1263 /*
1264 * If we previously were in the mode,
1265 * turn it off.
1266 */
1267 e1000_set_tbi_sbp_82543(hw, false);
1268 rctl = E1000_READ_REG(hw, E1000_RCTL);
1269 rctl &= ~E1000_RCTL_SBP;
1270 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1271 }
1272 } else {
1273 /*
1274 * If TBI compatibility is was previously off,
1275 * turn it on. For compatibility with a TBI link
1276 * partner, we will store bad packets. Some
1277 * frames have an additional byte on the end and
1278 * will look like CRC errors to to the hardware.
1279 */
1280 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1281 e1000_set_tbi_sbp_82543(hw, true);
1282 rctl = E1000_READ_REG(hw, E1000_RCTL);
1283 rctl |= E1000_RCTL_SBP;
1284 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1285 }
1286 }
1287 }
1288 out:
1289 return ret_val;
1290 }
1291
1292 /**
1293 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1294 * @hw: pointer to the HW structure
1295 *
1296 * Checks for link up on the hardware. If link is not up and we have
1297 * a signal, then we need to force link up.
1298 **/
e1000_check_for_fiber_link_82543(struct e1000_hw * hw)1299 STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1300 {
1301 struct e1000_mac_info *mac = &hw->mac;
1302 u32 rxcw, ctrl, status;
1303 s32 ret_val = E1000_SUCCESS;
1304
1305 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1306
1307 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1308 status = E1000_READ_REG(hw, E1000_STATUS);
1309 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1310
1311 /*
1312 * If we don't have link (auto-negotiation failed or link partner
1313 * cannot auto-negotiate), the cable is plugged in (we have signal),
1314 * and our link partner is not trying to auto-negotiate with us (we
1315 * are receiving idles or data), we need to force link up. We also
1316 * need to give auto-negotiation time to complete, in case the cable
1317 * was just plugged in. The autoneg_failed flag does this.
1318 */
1319 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1320 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1321 (!(status & E1000_STATUS_LU)) &&
1322 (!(rxcw & E1000_RXCW_C))) {
1323 if (!mac->autoneg_failed) {
1324 mac->autoneg_failed = true;
1325 ret_val = 0;
1326 goto out;
1327 }
1328 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1329
1330 /* Disable auto-negotiation in the TXCW register */
1331 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1332
1333 /* Force link-up and also force full-duplex. */
1334 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1335 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1336 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1337
1338 /* Configure Flow Control after forcing link up. */
1339 ret_val = e1000_config_fc_after_link_up_generic(hw);
1340 if (ret_val) {
1341 DEBUGOUT("Error configuring flow control\n");
1342 goto out;
1343 }
1344 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1345 /*
1346 * If we are forcing link and we are receiving /C/ ordered
1347 * sets, re-enable auto-negotiation in the TXCW register
1348 * and disable forced link in the Device Control register
1349 * in an attempt to auto-negotiate with our link partner.
1350 */
1351 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1352 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1353 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1354
1355 mac->serdes_has_link = true;
1356 }
1357
1358 out:
1359 return ret_val;
1360 }
1361
1362 /**
1363 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1364 * @hw: pointer to the HW structure
1365 *
1366 * For the 82543 silicon, we need to set the MAC to match the settings
1367 * of the PHY, even if the PHY is auto-negotiating.
1368 **/
e1000_config_mac_to_phy_82543(struct e1000_hw * hw)1369 STATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1370 {
1371 u32 ctrl;
1372 s32 ret_val = E1000_SUCCESS;
1373 u16 phy_data;
1374
1375 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1376
1377 if (!(hw->phy.ops.read_reg))
1378 goto out;
1379
1380 /* Set the bits to force speed and duplex */
1381 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1382 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1383 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1384
1385 /*
1386 * Set up duplex in the Device Control and Transmit Control
1387 * registers depending on negotiated values.
1388 */
1389 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1390 if (ret_val)
1391 goto out;
1392
1393 ctrl &= ~E1000_CTRL_FD;
1394 if (phy_data & M88E1000_PSSR_DPLX)
1395 ctrl |= E1000_CTRL_FD;
1396
1397 hw->mac.ops.config_collision_dist(hw);
1398
1399 /*
1400 * Set up speed in the Device Control register depending on
1401 * negotiated values.
1402 */
1403 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1404 ctrl |= E1000_CTRL_SPD_1000;
1405 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1406 ctrl |= E1000_CTRL_SPD_100;
1407
1408 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1409
1410 out:
1411 return ret_val;
1412 }
1413
1414 /**
1415 * e1000_write_vfta_82543 - Write value to VLAN filter table
1416 * @hw: pointer to the HW structure
1417 * @offset: the 32-bit offset in which to write the value to.
1418 * @value: the 32-bit value to write at location offset.
1419 *
1420 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1421 * table.
1422 **/
e1000_write_vfta_82543(struct e1000_hw * hw,u32 offset,u32 value)1423 STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1424 {
1425 u32 temp;
1426
1427 DEBUGFUNC("e1000_write_vfta_82543");
1428
1429 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1430 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1431 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1432 E1000_WRITE_FLUSH(hw);
1433 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1434 E1000_WRITE_FLUSH(hw);
1435 } else {
1436 e1000_write_vfta_generic(hw, offset, value);
1437 }
1438 }
1439
1440 /**
1441 * e1000_led_on_82543 - Turn on SW controllable LED
1442 * @hw: pointer to the HW structure
1443 *
1444 * Turns the SW defined LED on.
1445 **/
e1000_led_on_82543(struct e1000_hw * hw)1446 STATIC s32 e1000_led_on_82543(struct e1000_hw *hw)
1447 {
1448 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1449
1450 DEBUGFUNC("e1000_led_on_82543");
1451
1452 if (hw->mac.type == e1000_82544 &&
1453 hw->phy.media_type == e1000_media_type_copper) {
1454 /* Clear SW-definable Pin 0 to turn on the LED */
1455 ctrl &= ~E1000_CTRL_SWDPIN0;
1456 ctrl |= E1000_CTRL_SWDPIO0;
1457 } else {
1458 /* Fiber 82544 and all 82543 use this method */
1459 ctrl |= E1000_CTRL_SWDPIN0;
1460 ctrl |= E1000_CTRL_SWDPIO0;
1461 }
1462 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1463
1464 return E1000_SUCCESS;
1465 }
1466
1467 /**
1468 * e1000_led_off_82543 - Turn off SW controllable LED
1469 * @hw: pointer to the HW structure
1470 *
1471 * Turns the SW defined LED off.
1472 **/
e1000_led_off_82543(struct e1000_hw * hw)1473 STATIC s32 e1000_led_off_82543(struct e1000_hw *hw)
1474 {
1475 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1476
1477 DEBUGFUNC("e1000_led_off_82543");
1478
1479 if (hw->mac.type == e1000_82544 &&
1480 hw->phy.media_type == e1000_media_type_copper) {
1481 /* Set SW-definable Pin 0 to turn off the LED */
1482 ctrl |= E1000_CTRL_SWDPIN0;
1483 ctrl |= E1000_CTRL_SWDPIO0;
1484 } else {
1485 ctrl &= ~E1000_CTRL_SWDPIN0;
1486 ctrl |= E1000_CTRL_SWDPIO0;
1487 }
1488 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1489
1490 return E1000_SUCCESS;
1491 }
1492
1493 /**
1494 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1495 * @hw: pointer to the HW structure
1496 *
1497 * Clears the hardware counters by reading the counter registers.
1498 **/
e1000_clear_hw_cntrs_82543(struct e1000_hw * hw)1499 STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1500 {
1501 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1502
1503 e1000_clear_hw_cntrs_base_generic(hw);
1504
1505 E1000_READ_REG(hw, E1000_PRC64);
1506 E1000_READ_REG(hw, E1000_PRC127);
1507 E1000_READ_REG(hw, E1000_PRC255);
1508 E1000_READ_REG(hw, E1000_PRC511);
1509 E1000_READ_REG(hw, E1000_PRC1023);
1510 E1000_READ_REG(hw, E1000_PRC1522);
1511 E1000_READ_REG(hw, E1000_PTC64);
1512 E1000_READ_REG(hw, E1000_PTC127);
1513 E1000_READ_REG(hw, E1000_PTC255);
1514 E1000_READ_REG(hw, E1000_PTC511);
1515 E1000_READ_REG(hw, E1000_PTC1023);
1516 E1000_READ_REG(hw, E1000_PTC1522);
1517
1518 E1000_READ_REG(hw, E1000_ALGNERRC);
1519 E1000_READ_REG(hw, E1000_RXERRC);
1520 E1000_READ_REG(hw, E1000_TNCRS);
1521 E1000_READ_REG(hw, E1000_CEXTERR);
1522 E1000_READ_REG(hw, E1000_TSCTC);
1523 E1000_READ_REG(hw, E1000_TSCTFC);
1524 }
1525