1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
6 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
7 */
8
9 #include "e1000_api.h"
10
11 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
12 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
13 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
14 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
15 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
16 u32 offset,
17 u16 *data);
18 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
19 u32 offset,
20 u16 data);
21 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
22 u16 words, u16 *data);
23 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
24 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
25 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
26 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
27 u16 *duplex);
28 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
29 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
30 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
31 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
32 STATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
33 STATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
34 STATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
35 STATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
36 STATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
37 u16 *data);
38 STATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
39 u16 data);
40 STATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
41 STATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
42 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
43 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
44
45 /* A table for the GG82563 cable length where the range is defined
46 * with a lower bound at "index" and the upper bound at
47 * "index + 5".
48 */
49 STATIC const u16 e1000_gg82563_cable_length_table[] = {
50 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
51 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
52 (sizeof(e1000_gg82563_cable_length_table) / \
53 sizeof(e1000_gg82563_cable_length_table[0]))
54
55 /**
56 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
57 * @hw: pointer to the HW structure
58 **/
e1000_init_phy_params_80003es2lan(struct e1000_hw * hw)59 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
60 {
61 struct e1000_phy_info *phy = &hw->phy;
62 s32 ret_val;
63
64 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
65
66 if (hw->phy.media_type != e1000_media_type_copper) {
67 phy->type = e1000_phy_none;
68 return E1000_SUCCESS;
69 } else {
70 phy->ops.power_up = e1000_power_up_phy_copper;
71 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
72 }
73
74 phy->addr = 1;
75 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
76 phy->reset_delay_us = 100;
77 phy->type = e1000_phy_gg82563;
78
79 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
80 phy->ops.check_polarity = e1000_check_polarity_m88;
81 phy->ops.check_reset_block = e1000_check_reset_block_generic;
82 phy->ops.commit = e1000_phy_sw_reset_generic;
83 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
84 phy->ops.get_info = e1000_get_phy_info_m88;
85 phy->ops.release = e1000_release_phy_80003es2lan;
86 phy->ops.reset = e1000_phy_hw_reset_generic;
87 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
88
89 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
90 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
91 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
92 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
93
94 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
95
96 /* This can only be done after all function pointers are setup. */
97 ret_val = e1000_get_phy_id(hw);
98
99 /* Verify phy id */
100 if (phy->id != GG82563_E_PHY_ID)
101 return -E1000_ERR_PHY;
102
103 return ret_val;
104 }
105
106 /**
107 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
108 * @hw: pointer to the HW structure
109 **/
e1000_init_nvm_params_80003es2lan(struct e1000_hw * hw)110 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
111 {
112 struct e1000_nvm_info *nvm = &hw->nvm;
113 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
114 u16 size;
115
116 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
117
118 nvm->opcode_bits = 8;
119 nvm->delay_usec = 1;
120 switch (nvm->override) {
121 case e1000_nvm_override_spi_large:
122 nvm->page_size = 32;
123 nvm->address_bits = 16;
124 break;
125 case e1000_nvm_override_spi_small:
126 nvm->page_size = 8;
127 nvm->address_bits = 8;
128 break;
129 default:
130 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
131 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
132 break;
133 }
134
135 nvm->type = e1000_nvm_eeprom_spi;
136
137 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
138 E1000_EECD_SIZE_EX_SHIFT);
139
140 /* Added to a constant, "size" becomes the left-shift value
141 * for setting word_size.
142 */
143 size += NVM_WORD_SIZE_BASE_SHIFT;
144
145 /* EEPROM access above 16k is unsupported */
146 if (size > 14)
147 size = 14;
148 nvm->word_size = 1 << size;
149
150 /* Function Pointers */
151 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
152 nvm->ops.read = e1000_read_nvm_eerd;
153 nvm->ops.release = e1000_release_nvm_80003es2lan;
154 nvm->ops.update = e1000_update_nvm_checksum_generic;
155 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
156 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
157 nvm->ops.write = e1000_write_nvm_80003es2lan;
158
159 return E1000_SUCCESS;
160 }
161
162 /**
163 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
164 * @hw: pointer to the HW structure
165 **/
e1000_init_mac_params_80003es2lan(struct e1000_hw * hw)166 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
167 {
168 struct e1000_mac_info *mac = &hw->mac;
169
170 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
171
172 /* Set media type and media-dependent function pointers */
173 switch (hw->device_id) {
174 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
175 hw->phy.media_type = e1000_media_type_internal_serdes;
176 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
177 mac->ops.setup_physical_interface =
178 e1000_setup_fiber_serdes_link_generic;
179 break;
180 default:
181 hw->phy.media_type = e1000_media_type_copper;
182 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
183 mac->ops.setup_physical_interface =
184 e1000_setup_copper_link_80003es2lan;
185 break;
186 }
187
188 /* Set mta register count */
189 mac->mta_reg_count = 128;
190 /* Set rar entry count */
191 mac->rar_entry_count = E1000_RAR_ENTRIES;
192 /* Set if part includes ASF firmware */
193 mac->asf_firmware_present = true;
194 /* FWSM register */
195 mac->has_fwsm = true;
196 /* ARC supported; valid only if manageability features are enabled. */
197 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
198 E1000_FWSM_MODE_MASK);
199 /* Adaptive IFS not supported */
200 mac->adaptive_ifs = false;
201
202 /* Function pointers */
203
204 /* bus type/speed/width */
205 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
206 /* reset */
207 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
208 /* hw initialization */
209 mac->ops.init_hw = e1000_init_hw_80003es2lan;
210 /* link setup */
211 mac->ops.setup_link = e1000_setup_link_generic;
212 /* check management mode */
213 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
214 /* multicast address update */
215 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
216 /* writing VFTA */
217 mac->ops.write_vfta = e1000_write_vfta_generic;
218 /* clearing VFTA */
219 mac->ops.clear_vfta = e1000_clear_vfta_generic;
220 /* read mac address */
221 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
222 /* ID LED init */
223 mac->ops.id_led_init = e1000_id_led_init_generic;
224 /* blink LED */
225 mac->ops.blink_led = e1000_blink_led_generic;
226 /* setup LED */
227 mac->ops.setup_led = e1000_setup_led_generic;
228 /* cleanup LED */
229 mac->ops.cleanup_led = e1000_cleanup_led_generic;
230 /* turn on/off LED */
231 mac->ops.led_on = e1000_led_on_generic;
232 mac->ops.led_off = e1000_led_off_generic;
233 /* clear hardware counters */
234 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
235 /* link info */
236 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
237
238 /* set lan id for port to determine which phy lock to use */
239 hw->mac.ops.set_lan_id(hw);
240
241 return E1000_SUCCESS;
242 }
243
244 /**
245 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
246 * @hw: pointer to the HW structure
247 *
248 * Called to initialize all function pointers and parameters.
249 **/
e1000_init_function_pointers_80003es2lan(struct e1000_hw * hw)250 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
251 {
252 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
253
254 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
255 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
256 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
257 }
258
259 /**
260 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
261 * @hw: pointer to the HW structure
262 *
263 * A wrapper to acquire access rights to the correct PHY.
264 **/
e1000_acquire_phy_80003es2lan(struct e1000_hw * hw)265 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
266 {
267 u16 mask;
268
269 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
270
271 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
272 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
273 }
274
275 /**
276 * e1000_release_phy_80003es2lan - Release rights to access PHY
277 * @hw: pointer to the HW structure
278 *
279 * A wrapper to release access rights to the correct PHY.
280 **/
e1000_release_phy_80003es2lan(struct e1000_hw * hw)281 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
282 {
283 u16 mask;
284
285 DEBUGFUNC("e1000_release_phy_80003es2lan");
286
287 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
288 e1000_release_swfw_sync_80003es2lan(hw, mask);
289 }
290
291 /**
292 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
293 * @hw: pointer to the HW structure
294 *
295 * Acquire the semaphore to access the Kumeran interface.
296 *
297 **/
e1000_acquire_mac_csr_80003es2lan(struct e1000_hw * hw)298 STATIC s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
299 {
300 u16 mask;
301
302 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
303
304 mask = E1000_SWFW_CSR_SM;
305
306 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
307 }
308
309 /**
310 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
311 * @hw: pointer to the HW structure
312 *
313 * Release the semaphore used to access the Kumeran interface
314 **/
e1000_release_mac_csr_80003es2lan(struct e1000_hw * hw)315 STATIC void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
316 {
317 u16 mask;
318
319 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
320
321 mask = E1000_SWFW_CSR_SM;
322
323 e1000_release_swfw_sync_80003es2lan(hw, mask);
324 }
325
326 /**
327 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
328 * @hw: pointer to the HW structure
329 *
330 * Acquire the semaphore to access the EEPROM.
331 **/
e1000_acquire_nvm_80003es2lan(struct e1000_hw * hw)332 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
333 {
334 s32 ret_val;
335
336 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
337
338 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
339 if (ret_val)
340 return ret_val;
341
342 ret_val = e1000_acquire_nvm_generic(hw);
343
344 if (ret_val)
345 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
346
347 return ret_val;
348 }
349
350 /**
351 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
352 * @hw: pointer to the HW structure
353 *
354 * Release the semaphore used to access the EEPROM.
355 **/
e1000_release_nvm_80003es2lan(struct e1000_hw * hw)356 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
357 {
358 DEBUGFUNC("e1000_release_nvm_80003es2lan");
359
360 e1000_release_nvm_generic(hw);
361 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
362 }
363
364 /**
365 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
366 * @hw: pointer to the HW structure
367 * @mask: specifies which semaphore to acquire
368 *
369 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
370 * will also specify which port we're acquiring the lock for.
371 **/
e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw * hw,u16 mask)372 STATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
373 {
374 u32 swfw_sync;
375 u32 swmask = mask;
376 u32 fwmask = mask << 16;
377 s32 i = 0;
378 s32 timeout = 50;
379
380 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
381
382 while (i < timeout) {
383 if (e1000_get_hw_semaphore_generic(hw))
384 return -E1000_ERR_SWFW_SYNC;
385
386 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
387 if (!(swfw_sync & (fwmask | swmask)))
388 break;
389
390 /* Firmware currently using resource (fwmask)
391 * or other software thread using resource (swmask)
392 */
393 e1000_put_hw_semaphore_generic(hw);
394 msec_delay_irq(5);
395 i++;
396 }
397
398 if (i == timeout) {
399 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
400 return -E1000_ERR_SWFW_SYNC;
401 }
402
403 swfw_sync |= swmask;
404 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
405
406 e1000_put_hw_semaphore_generic(hw);
407
408 return E1000_SUCCESS;
409 }
410
411 /**
412 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
413 * @hw: pointer to the HW structure
414 * @mask: specifies which semaphore to acquire
415 *
416 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
417 * will also specify which port we're releasing the lock for.
418 **/
e1000_release_swfw_sync_80003es2lan(struct e1000_hw * hw,u16 mask)419 STATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
420 {
421 u32 swfw_sync;
422
423 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
424
425 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
426 ; /* Empty */
427
428 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
429 swfw_sync &= ~mask;
430 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
431
432 e1000_put_hw_semaphore_generic(hw);
433 }
434
435 /**
436 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
437 * @hw: pointer to the HW structure
438 * @offset: offset of the register to read
439 * @data: pointer to the data returned from the operation
440 *
441 * Read the GG82563 PHY register.
442 **/
e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)443 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
444 u32 offset, u16 *data)
445 {
446 s32 ret_val;
447 u32 page_select;
448 u16 temp;
449
450 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
451
452 ret_val = e1000_acquire_phy_80003es2lan(hw);
453 if (ret_val)
454 return ret_val;
455
456 /* Select Configuration Page */
457 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
458 page_select = GG82563_PHY_PAGE_SELECT;
459 } else {
460 /* Use Alternative Page Select register to access
461 * registers 30 and 31
462 */
463 page_select = GG82563_PHY_PAGE_SELECT_ALT;
464 }
465
466 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
467 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
468 if (ret_val) {
469 e1000_release_phy_80003es2lan(hw);
470 return ret_val;
471 }
472
473 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
474 /* The "ready" bit in the MDIC register may be incorrectly set
475 * before the device has completed the "Page Select" MDI
476 * transaction. So we wait 200us after each MDI command...
477 */
478 usec_delay(200);
479
480 /* ...and verify the command was successful. */
481 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
482
483 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
484 e1000_release_phy_80003es2lan(hw);
485 return -E1000_ERR_PHY;
486 }
487
488 usec_delay(200);
489
490 ret_val = e1000_read_phy_reg_mdic(hw,
491 MAX_PHY_REG_ADDRESS & offset,
492 data);
493
494 usec_delay(200);
495 } else {
496 ret_val = e1000_read_phy_reg_mdic(hw,
497 MAX_PHY_REG_ADDRESS & offset,
498 data);
499 }
500
501 e1000_release_phy_80003es2lan(hw);
502
503 return ret_val;
504 }
505
506 /**
507 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
508 * @hw: pointer to the HW structure
509 * @offset: offset of the register to read
510 * @data: value to write to the register
511 *
512 * Write to the GG82563 PHY register.
513 **/
e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)514 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
515 u32 offset, u16 data)
516 {
517 s32 ret_val;
518 u32 page_select;
519 u16 temp;
520
521 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
522
523 ret_val = e1000_acquire_phy_80003es2lan(hw);
524 if (ret_val)
525 return ret_val;
526
527 /* Select Configuration Page */
528 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
529 page_select = GG82563_PHY_PAGE_SELECT;
530 } else {
531 /* Use Alternative Page Select register to access
532 * registers 30 and 31
533 */
534 page_select = GG82563_PHY_PAGE_SELECT_ALT;
535 }
536
537 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
538 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
539 if (ret_val) {
540 e1000_release_phy_80003es2lan(hw);
541 return ret_val;
542 }
543
544 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
545 /* The "ready" bit in the MDIC register may be incorrectly set
546 * before the device has completed the "Page Select" MDI
547 * transaction. So we wait 200us after each MDI command...
548 */
549 usec_delay(200);
550
551 /* ...and verify the command was successful. */
552 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
553
554 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
555 e1000_release_phy_80003es2lan(hw);
556 return -E1000_ERR_PHY;
557 }
558
559 usec_delay(200);
560
561 ret_val = e1000_write_phy_reg_mdic(hw,
562 MAX_PHY_REG_ADDRESS & offset,
563 data);
564
565 usec_delay(200);
566 } else {
567 ret_val = e1000_write_phy_reg_mdic(hw,
568 MAX_PHY_REG_ADDRESS & offset,
569 data);
570 }
571
572 e1000_release_phy_80003es2lan(hw);
573
574 return ret_val;
575 }
576
577 /**
578 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
579 * @hw: pointer to the HW structure
580 * @offset: offset of the register to read
581 * @words: number of words to write
582 * @data: buffer of data to write to the NVM
583 *
584 * Write "words" of data to the ESB2 NVM.
585 **/
e1000_write_nvm_80003es2lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)586 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
587 u16 words, u16 *data)
588 {
589 DEBUGFUNC("e1000_write_nvm_80003es2lan");
590
591 return e1000_write_nvm_spi(hw, offset, words, data);
592 }
593
594 /**
595 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
596 * @hw: pointer to the HW structure
597 *
598 * Wait a specific amount of time for manageability processes to complete.
599 * This is a function pointer entry point called by the phy module.
600 **/
e1000_get_cfg_done_80003es2lan(struct e1000_hw * hw)601 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
602 {
603 s32 timeout = PHY_CFG_TIMEOUT;
604 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
605
606 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
607
608 if (hw->bus.func == 1)
609 mask = E1000_NVM_CFG_DONE_PORT_1;
610
611 while (timeout) {
612 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
613 break;
614 msec_delay(1);
615 timeout--;
616 }
617 if (!timeout) {
618 DEBUGOUT("MNG configuration cycle has not completed.\n");
619 return -E1000_ERR_RESET;
620 }
621
622 return E1000_SUCCESS;
623 }
624
625 /**
626 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
627 * @hw: pointer to the HW structure
628 *
629 * Force the speed and duplex settings onto the PHY. This is a
630 * function pointer entry point called by the phy module.
631 **/
e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw * hw)632 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
633 {
634 s32 ret_val;
635 u16 phy_data;
636 bool link;
637
638 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
639
640 if (!(hw->phy.ops.read_reg))
641 return E1000_SUCCESS;
642
643 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
644 * forced whenever speed and duplex are forced.
645 */
646 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
647 if (ret_val)
648 return ret_val;
649
650 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
651 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
652 if (ret_val)
653 return ret_val;
654
655 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
656
657 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
658 if (ret_val)
659 return ret_val;
660
661 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
662
663 /* Reset the phy to commit changes. */
664 phy_data |= MII_CR_RESET;
665
666 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
667 if (ret_val)
668 return ret_val;
669
670 usec_delay(1);
671
672 if (hw->phy.autoneg_wait_to_complete) {
673 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
674
675 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
676 100000, &link);
677 if (ret_val)
678 return ret_val;
679
680 if (!link) {
681 /* We didn't get link.
682 * Reset the DSP and cross our fingers.
683 */
684 ret_val = e1000_phy_reset_dsp_generic(hw);
685 if (ret_val)
686 return ret_val;
687 }
688
689 /* Try once more */
690 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
691 100000, &link);
692 if (ret_val)
693 return ret_val;
694 }
695
696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
697 &phy_data);
698 if (ret_val)
699 return ret_val;
700
701 /* Resetting the phy means we need to verify the TX_CLK corresponds
702 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
703 */
704 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
705 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
706 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
707 else
708 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
709
710 /* In addition, we must re-enable CRS on Tx for both half and full
711 * duplex.
712 */
713 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
714 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
715 phy_data);
716
717 return ret_val;
718 }
719
720 /**
721 * e1000_get_cable_length_80003es2lan - Set approximate cable length
722 * @hw: pointer to the HW structure
723 *
724 * Find the approximate cable length as measured by the GG82563 PHY.
725 * This is a function pointer entry point called by the phy module.
726 **/
e1000_get_cable_length_80003es2lan(struct e1000_hw * hw)727 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
728 {
729 struct e1000_phy_info *phy = &hw->phy;
730 s32 ret_val;
731 u16 phy_data, index;
732
733 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
734
735 if (!(hw->phy.ops.read_reg))
736 return E1000_SUCCESS;
737
738 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
739 if (ret_val)
740 return ret_val;
741
742 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
743
744 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
745 return -E1000_ERR_PHY;
746
747 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
748 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
749
750 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
751
752 return E1000_SUCCESS;
753 }
754
755 /**
756 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
757 * @hw: pointer to the HW structure
758 * @speed: pointer to speed buffer
759 * @duplex: pointer to duplex buffer
760 *
761 * Retrieve the current speed and duplex configuration.
762 **/
e1000_get_link_up_info_80003es2lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)763 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
764 u16 *duplex)
765 {
766 s32 ret_val;
767
768 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
769
770 if (hw->phy.media_type == e1000_media_type_copper) {
771 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
772 duplex);
773 hw->phy.ops.cfg_on_link_up(hw);
774 } else {
775 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
776 speed,
777 duplex);
778 }
779
780 return ret_val;
781 }
782
783 /**
784 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
785 * @hw: pointer to the HW structure
786 *
787 * Perform a global reset to the ESB2 controller.
788 **/
e1000_reset_hw_80003es2lan(struct e1000_hw * hw)789 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
790 {
791 u32 ctrl;
792 s32 ret_val;
793 u16 kum_reg_data;
794
795 DEBUGFUNC("e1000_reset_hw_80003es2lan");
796
797 /* Prevent the PCI-E bus from sticking if there is no TLP connection
798 * on the last TLP read/write transaction when MAC is reset.
799 */
800 ret_val = e1000_disable_pcie_master_generic(hw);
801 if (ret_val)
802 DEBUGOUT("PCI-E Master disable polling has failed.\n");
803
804 DEBUGOUT("Masking off all interrupts\n");
805 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
806
807 E1000_WRITE_REG(hw, E1000_RCTL, 0);
808 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
809 E1000_WRITE_FLUSH(hw);
810
811 msec_delay(10);
812
813 ctrl = E1000_READ_REG(hw, E1000_CTRL);
814
815 ret_val = e1000_acquire_phy_80003es2lan(hw);
816 if (ret_val)
817 return ret_val;
818
819 DEBUGOUT("Issuing a global reset to MAC\n");
820 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
821 e1000_release_phy_80003es2lan(hw);
822
823 /* Disable IBIST slave mode (far-end loopback) */
824 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
825 E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data);
826 if (!ret_val) {
827 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
828 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
829 E1000_KMRNCTRLSTA_INBAND_PARAM,
830 kum_reg_data);
831 if (ret_val)
832 DEBUGOUT("Error disabling far-end loopback\n");
833 } else
834 DEBUGOUT("Error disabling far-end loopback\n");
835
836 ret_val = e1000_get_auto_rd_done_generic(hw);
837 if (ret_val)
838 /* We don't want to continue accessing MAC registers. */
839 return ret_val;
840
841 /* Clear any pending interrupt events. */
842 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
843 E1000_READ_REG(hw, E1000_ICR);
844
845 return e1000_check_alt_mac_addr_generic(hw);
846 }
847
848 /**
849 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
850 * @hw: pointer to the HW structure
851 *
852 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
853 **/
e1000_init_hw_80003es2lan(struct e1000_hw * hw)854 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
855 {
856 struct e1000_mac_info *mac = &hw->mac;
857 u32 reg_data;
858 s32 ret_val;
859 u16 kum_reg_data;
860 u16 i;
861
862 DEBUGFUNC("e1000_init_hw_80003es2lan");
863
864 e1000_initialize_hw_bits_80003es2lan(hw);
865
866 /* Initialize identification LED */
867 ret_val = mac->ops.id_led_init(hw);
868 /* An error is not fatal and we should not stop init due to this */
869 if (ret_val)
870 DEBUGOUT("Error initializing identification LED\n");
871
872 /* Disabling VLAN filtering */
873 DEBUGOUT("Initializing the IEEE VLAN\n");
874 mac->ops.clear_vfta(hw);
875
876 /* Setup the receive address. */
877 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
878
879 /* Zero out the Multicast HASH table */
880 DEBUGOUT("Zeroing the MTA\n");
881 for (i = 0; i < mac->mta_reg_count; i++)
882 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
883
884 /* Setup link and flow control */
885 ret_val = mac->ops.setup_link(hw);
886 if (ret_val)
887 return ret_val;
888
889 /* Disable IBIST slave mode (far-end loopback) */
890 ret_val =
891 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
892 &kum_reg_data);
893 if (!ret_val) {
894 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
895 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
896 E1000_KMRNCTRLSTA_INBAND_PARAM,
897 kum_reg_data);
898 if (ret_val)
899 DEBUGOUT("Error disabling far-end loopback\n");
900 } else
901 DEBUGOUT("Error disabling far-end loopback\n");
902
903 /* Set the transmit descriptor write-back policy */
904 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
905 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
906 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
907 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
908
909 /* ...for both queues. */
910 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
911 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
912 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
913 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
914
915 /* Enable retransmit on late collisions */
916 reg_data = E1000_READ_REG(hw, E1000_TCTL);
917 reg_data |= E1000_TCTL_RTLC;
918 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
919
920 /* Configure Gigabit Carry Extend Padding */
921 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
922 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
923 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
924 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
925
926 /* Configure Transmit Inter-Packet Gap */
927 reg_data = E1000_READ_REG(hw, E1000_TIPG);
928 reg_data &= ~E1000_TIPG_IPGT_MASK;
929 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
930 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
931
932 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
933 reg_data &= ~0x00100000;
934 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
935
936 /* default to true to enable the MDIC W/A */
937 hw->dev_spec._80003es2lan.mdic_wa_enable = true;
938
939 ret_val =
940 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
941 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
942 if (!ret_val) {
943 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
944 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
945 hw->dev_spec._80003es2lan.mdic_wa_enable = false;
946 }
947
948 /* Clear all of the statistics registers (clear on read). It is
949 * important that we do this after we have tried to establish link
950 * because the symbol error count will increment wildly if there
951 * is no link.
952 */
953 e1000_clear_hw_cntrs_80003es2lan(hw);
954
955 return ret_val;
956 }
957
958 /**
959 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
960 * @hw: pointer to the HW structure
961 *
962 * Initializes required hardware-dependent bits needed for normal operation.
963 **/
e1000_initialize_hw_bits_80003es2lan(struct e1000_hw * hw)964 STATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
965 {
966 u32 reg;
967
968 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
969
970 /* Transmit Descriptor Control 0 */
971 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
972 reg |= (1 << 22);
973 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
974
975 /* Transmit Descriptor Control 1 */
976 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
977 reg |= (1 << 22);
978 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
979
980 /* Transmit Arbitration Control 0 */
981 reg = E1000_READ_REG(hw, E1000_TARC(0));
982 reg &= ~(0xF << 27); /* 30:27 */
983 if (hw->phy.media_type != e1000_media_type_copper)
984 reg &= ~(1 << 20);
985 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
986
987 /* Transmit Arbitration Control 1 */
988 reg = E1000_READ_REG(hw, E1000_TARC(1));
989 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
990 reg &= ~(1 << 28);
991 else
992 reg |= (1 << 28);
993 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
994
995 /* Disable IPv6 extension header parsing because some malformed
996 * IPv6 headers can hang the Rx.
997 */
998 reg = E1000_READ_REG(hw, E1000_RFCTL);
999 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1000 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1001
1002 return;
1003 }
1004
1005 /**
1006 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1007 * @hw: pointer to the HW structure
1008 *
1009 * Setup some GG82563 PHY registers for obtaining link
1010 **/
e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw * hw)1011 STATIC s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1012 {
1013 struct e1000_phy_info *phy = &hw->phy;
1014 s32 ret_val;
1015 u32 reg;
1016 u16 data;
1017
1018 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1019
1020 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1021 if (ret_val)
1022 return ret_val;
1023
1024 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1025 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1026 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1027
1028 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1029 if (ret_val)
1030 return ret_val;
1031
1032 /* Options:
1033 * MDI/MDI-X = 0 (default)
1034 * 0 - Auto for all speeds
1035 * 1 - MDI mode
1036 * 2 - MDI-X mode
1037 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1038 */
1039 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1040 if (ret_val)
1041 return ret_val;
1042
1043 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1044
1045 switch (phy->mdix) {
1046 case 1:
1047 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1048 break;
1049 case 2:
1050 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1051 break;
1052 case 0:
1053 default:
1054 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1055 break;
1056 }
1057
1058 /* Options:
1059 * disable_polarity_correction = 0 (default)
1060 * Automatic Correction for Reversed Cable Polarity
1061 * 0 - Disabled
1062 * 1 - Enabled
1063 */
1064 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1065 if (phy->disable_polarity_correction)
1066 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1067
1068 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1069 if (ret_val)
1070 return ret_val;
1071
1072 /* SW Reset the PHY so all changes take effect */
1073 ret_val = hw->phy.ops.commit(hw);
1074 if (ret_val) {
1075 DEBUGOUT("Error Resetting the PHY\n");
1076 return ret_val;
1077 }
1078
1079 /* Bypass Rx and Tx FIFO's */
1080 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
1081 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1082 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1083 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1084 if (ret_val)
1085 return ret_val;
1086
1087 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
1088 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1089 if (ret_val)
1090 return ret_val;
1091 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1092 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1093 if (ret_val)
1094 return ret_val;
1095
1096 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1097 if (ret_val)
1098 return ret_val;
1099
1100 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1101 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1102 if (ret_val)
1103 return ret_val;
1104
1105 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1106 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1107 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1108
1109 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1110 if (ret_val)
1111 return ret_val;
1112
1113 /* Do not init these registers when the HW is in IAMT mode, since the
1114 * firmware will have already initialized them. We only initialize
1115 * them if the HW is not in IAMT mode.
1116 */
1117 if (!hw->mac.ops.check_mng_mode(hw)) {
1118 /* Enable Electrical Idle on the PHY */
1119 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1120 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1121 data);
1122 if (ret_val)
1123 return ret_val;
1124
1125 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1126 &data);
1127 if (ret_val)
1128 return ret_val;
1129
1130 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1132 data);
1133 if (ret_val)
1134 return ret_val;
1135 }
1136
1137 /* Workaround: Disable padding in Kumeran interface in the MAC
1138 * and in the PHY to avoid CRC errors.
1139 */
1140 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1141 if (ret_val)
1142 return ret_val;
1143
1144 data |= GG82563_ICR_DIS_PADDING;
1145 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1146 if (ret_val)
1147 return ret_val;
1148
1149 return E1000_SUCCESS;
1150 }
1151
1152 /**
1153 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1154 * @hw: pointer to the HW structure
1155 *
1156 * Essentially a wrapper for setting up all things "copper" related.
1157 * This is a function pointer entry point called by the mac module.
1158 **/
e1000_setup_copper_link_80003es2lan(struct e1000_hw * hw)1159 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1160 {
1161 u32 ctrl;
1162 s32 ret_val;
1163 u16 reg_data;
1164
1165 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1166
1167 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1168 ctrl |= E1000_CTRL_SLU;
1169 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1170 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1171
1172 /* Set the mac to wait the maximum time between each
1173 * iteration and increase the max iterations when
1174 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1175 */
1176 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1177 0xFFFF);
1178 if (ret_val)
1179 return ret_val;
1180 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1181 ®_data);
1182 if (ret_val)
1183 return ret_val;
1184 reg_data |= 0x3F;
1185 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1186 reg_data);
1187 if (ret_val)
1188 return ret_val;
1189 ret_val =
1190 e1000_read_kmrn_reg_80003es2lan(hw,
1191 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1192 ®_data);
1193 if (ret_val)
1194 return ret_val;
1195 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1196 ret_val =
1197 e1000_write_kmrn_reg_80003es2lan(hw,
1198 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1199 reg_data);
1200 if (ret_val)
1201 return ret_val;
1202
1203 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1204 if (ret_val)
1205 return ret_val;
1206
1207 return e1000_setup_copper_link_generic(hw);
1208 }
1209
1210 /**
1211 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1212 * @hw: pointer to the HW structure
1213 *
1214 * Configure the KMRN interface by applying last minute quirks for
1215 * 10/100 operation.
1216 **/
e1000_cfg_on_link_up_80003es2lan(struct e1000_hw * hw)1217 STATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1218 {
1219 s32 ret_val = E1000_SUCCESS;
1220 u16 speed;
1221 u16 duplex;
1222
1223 DEBUGFUNC("e1000_configure_on_link_up");
1224
1225 if (hw->phy.media_type == e1000_media_type_copper) {
1226 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1227 &duplex);
1228 if (ret_val)
1229 return ret_val;
1230
1231 if (speed == SPEED_1000)
1232 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1233 else
1234 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1235 }
1236
1237 return ret_val;
1238 }
1239
1240 /**
1241 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1242 * @hw: pointer to the HW structure
1243 * @duplex: current duplex setting
1244 *
1245 * Configure the KMRN interface by applying last minute quirks for
1246 * 10/100 operation.
1247 **/
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw * hw,u16 duplex)1248 STATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1249 {
1250 s32 ret_val;
1251 u32 tipg;
1252 u32 i = 0;
1253 u16 reg_data, reg_data2;
1254
1255 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1256
1257 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1258 ret_val =
1259 e1000_write_kmrn_reg_80003es2lan(hw,
1260 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1261 reg_data);
1262 if (ret_val)
1263 return ret_val;
1264
1265 /* Configure Transmit Inter-Packet Gap */
1266 tipg = E1000_READ_REG(hw, E1000_TIPG);
1267 tipg &= ~E1000_TIPG_IPGT_MASK;
1268 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1269 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1270
1271 do {
1272 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1273 ®_data);
1274 if (ret_val)
1275 return ret_val;
1276
1277 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1278 ®_data2);
1279 if (ret_val)
1280 return ret_val;
1281 i++;
1282 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1283
1284 if (duplex == HALF_DUPLEX)
1285 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1286 else
1287 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1288
1289 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1290 }
1291
1292 /**
1293 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1294 * @hw: pointer to the HW structure
1295 *
1296 * Configure the KMRN interface by applying last minute quirks for
1297 * gigabit operation.
1298 **/
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw * hw)1299 STATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1300 {
1301 s32 ret_val;
1302 u16 reg_data, reg_data2;
1303 u32 tipg;
1304 u32 i = 0;
1305
1306 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1307
1308 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1309 ret_val =
1310 e1000_write_kmrn_reg_80003es2lan(hw,
1311 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1312 reg_data);
1313 if (ret_val)
1314 return ret_val;
1315
1316 /* Configure Transmit Inter-Packet Gap */
1317 tipg = E1000_READ_REG(hw, E1000_TIPG);
1318 tipg &= ~E1000_TIPG_IPGT_MASK;
1319 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1320 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1321
1322 do {
1323 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1324 ®_data);
1325 if (ret_val)
1326 return ret_val;
1327
1328 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1329 ®_data2);
1330 if (ret_val)
1331 return ret_val;
1332 i++;
1333 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1334
1335 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1336
1337 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1338 }
1339
1340 /**
1341 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1342 * @hw: pointer to the HW structure
1343 * @offset: register offset to be read
1344 * @data: pointer to the read data
1345 *
1346 * Acquire semaphore, then read the PHY register at offset
1347 * using the kumeran interface. The information retrieved is stored in data.
1348 * Release the semaphore before exiting.
1349 **/
e1000_read_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)1350 STATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1351 u16 *data)
1352 {
1353 u32 kmrnctrlsta;
1354 s32 ret_val;
1355
1356 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1357
1358 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1359 if (ret_val)
1360 return ret_val;
1361
1362 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1363 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1364 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1365 E1000_WRITE_FLUSH(hw);
1366
1367 usec_delay(2);
1368
1369 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1370 *data = (u16)kmrnctrlsta;
1371
1372 e1000_release_mac_csr_80003es2lan(hw);
1373
1374 return ret_val;
1375 }
1376
1377 /**
1378 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1379 * @hw: pointer to the HW structure
1380 * @offset: register offset to write to
1381 * @data: data to write at register offset
1382 *
1383 * Acquire semaphore, then write the data to PHY register
1384 * at the offset using the kumeran interface. Release semaphore
1385 * before exiting.
1386 **/
e1000_write_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)1387 STATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1388 u16 data)
1389 {
1390 u32 kmrnctrlsta;
1391 s32 ret_val;
1392
1393 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1394
1395 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1396 if (ret_val)
1397 return ret_val;
1398
1399 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1400 E1000_KMRNCTRLSTA_OFFSET) | data;
1401 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1402 E1000_WRITE_FLUSH(hw);
1403
1404 usec_delay(2);
1405
1406 e1000_release_mac_csr_80003es2lan(hw);
1407
1408 return ret_val;
1409 }
1410
1411 /**
1412 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1413 * @hw: pointer to the HW structure
1414 **/
e1000_read_mac_addr_80003es2lan(struct e1000_hw * hw)1415 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1416 {
1417 s32 ret_val;
1418
1419 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1420
1421 /* If there's an alternate MAC address place it in RAR0
1422 * so that it will override the Si installed default perm
1423 * address.
1424 */
1425 ret_val = e1000_check_alt_mac_addr_generic(hw);
1426 if (ret_val)
1427 return ret_val;
1428
1429 return e1000_read_mac_addr_generic(hw);
1430 }
1431
1432 /**
1433 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1434 * @hw: pointer to the HW structure
1435 *
1436 * In the case of a PHY power down to save power, or to turn off link during a
1437 * driver unload, or wake on lan is not enabled, remove the link.
1438 **/
e1000_power_down_phy_copper_80003es2lan(struct e1000_hw * hw)1439 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1440 {
1441 /* If the management interface is not enabled, then power down */
1442 if (!(hw->mac.ops.check_mng_mode(hw) ||
1443 hw->phy.ops.check_reset_block(hw)))
1444 e1000_power_down_phy_copper(hw);
1445
1446 return;
1447 }
1448
1449 /**
1450 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1451 * @hw: pointer to the HW structure
1452 *
1453 * Clears the hardware counters by reading the counter registers.
1454 **/
e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw * hw)1455 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1456 {
1457 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1458
1459 e1000_clear_hw_cntrs_base_generic(hw);
1460
1461 E1000_READ_REG(hw, E1000_PRC64);
1462 E1000_READ_REG(hw, E1000_PRC127);
1463 E1000_READ_REG(hw, E1000_PRC255);
1464 E1000_READ_REG(hw, E1000_PRC511);
1465 E1000_READ_REG(hw, E1000_PRC1023);
1466 E1000_READ_REG(hw, E1000_PRC1522);
1467 E1000_READ_REG(hw, E1000_PTC64);
1468 E1000_READ_REG(hw, E1000_PTC127);
1469 E1000_READ_REG(hw, E1000_PTC255);
1470 E1000_READ_REG(hw, E1000_PTC511);
1471 E1000_READ_REG(hw, E1000_PTC1023);
1472 E1000_READ_REG(hw, E1000_PTC1522);
1473
1474 E1000_READ_REG(hw, E1000_ALGNERRC);
1475 E1000_READ_REG(hw, E1000_RXERRC);
1476 E1000_READ_REG(hw, E1000_TNCRS);
1477 E1000_READ_REG(hw, E1000_CEXTERR);
1478 E1000_READ_REG(hw, E1000_TSCTC);
1479 E1000_READ_REG(hw, E1000_TSCTFC);
1480
1481 E1000_READ_REG(hw, E1000_MGTPRC);
1482 E1000_READ_REG(hw, E1000_MGTPDC);
1483 E1000_READ_REG(hw, E1000_MGTPTC);
1484
1485 E1000_READ_REG(hw, E1000_IAC);
1486 E1000_READ_REG(hw, E1000_ICRXOC);
1487
1488 E1000_READ_REG(hw, E1000_ICRXPTC);
1489 E1000_READ_REG(hw, E1000_ICRXATC);
1490 E1000_READ_REG(hw, E1000_ICTXPTC);
1491 E1000_READ_REG(hw, E1000_ICTXATC);
1492 E1000_READ_REG(hw, E1000_ICTXQEC);
1493 E1000_READ_REG(hw, E1000_ICTXQMTC);
1494 E1000_READ_REG(hw, E1000_ICRXDMTC);
1495 }
1496