1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2019 NXP
5 *
6 */
7 #include <unistd.h>
8 #include <stdio.h>
9 #include <string.h>
10 #include <stdlib.h>
11 #include <fcntl.h>
12 #include <errno.h>
13 #include <stdarg.h>
14 #include <inttypes.h>
15 #include <signal.h>
16 #include <pthread.h>
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
20 #include <sys/stat.h>
21 #include <sys/mman.h>
22 #include <sys/syscall.h>
23 #include <sys/epoll.h>
24 #include<sys/eventfd.h>
25
26 #include <rte_mbuf.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
33 #include <rte_dev.h>
34
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
40
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
42
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
45
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
47
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
52
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
55
56 /* Variable to store DPAA2 DQRR size */
57 uint8_t dpaa2_dqrr_size;
58 /* Variable to store DPAA2 EQCR size */
59 uint8_t dpaa2_eqcr_size;
60
61 /* Variable to hold the portal_key, once created.*/
62 static pthread_key_t dpaa2_portal_key;
63
64 /*Stashing Macros default for LS208x*/
65 static int dpaa2_core_cluster_base = 0x04;
66 static int dpaa2_cluster_sz = 2;
67
68 /* For LS208X platform There are four clusters with following mapping:
69 * Cluster 1 (ID = x04) : CPU0, CPU1;
70 * Cluster 2 (ID = x05) : CPU2, CPU3;
71 * Cluster 3 (ID = x06) : CPU4, CPU5;
72 * Cluster 4 (ID = x07) : CPU6, CPU7;
73 */
74 /* For LS108X platform There are two clusters with following mapping:
75 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
76 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
77 */
78 /* For LX2160 platform There are four clusters with following mapping:
79 * Cluster 1 (ID = x00) : CPU0, CPU1;
80 * Cluster 2 (ID = x01) : CPU2, CPU3;
81 * Cluster 3 (ID = x02) : CPU4, CPU5;
82 * Cluster 4 (ID = x03) : CPU6, CPU7;
83 * Cluster 1 (ID = x04) : CPU8, CPU9;
84 * Cluster 2 (ID = x05) : CPU10, CP11;
85 * Cluster 3 (ID = x06) : CPU12, CPU13;
86 * Cluster 4 (ID = x07) : CPU14, CPU15;
87 */
88
89 static int
dpaa2_get_core_id(void)90 dpaa2_get_core_id(void)
91 {
92 rte_cpuset_t cpuset;
93 int i, ret, cpu_id = -1;
94
95 ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),
96 &cpuset);
97 if (ret) {
98 DPAA2_BUS_ERR("pthread_getaffinity_np() failed");
99 return ret;
100 }
101
102 for (i = 0; i < RTE_MAX_LCORE; i++) {
103 if (CPU_ISSET(i, &cpuset)) {
104 if (cpu_id == -1)
105 cpu_id = i;
106 else
107 /* Multiple cpus are affined */
108 return -1;
109 }
110 }
111
112 return cpu_id;
113 }
114
115 static int
dpaa2_core_cluster_sdest(int cpu_id)116 dpaa2_core_cluster_sdest(int cpu_id)
117 {
118 int x = cpu_id / dpaa2_cluster_sz;
119
120 return dpaa2_core_cluster_base + x;
121 }
122
123 #ifdef RTE_EVENT_DPAA2
124 static void
dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id,int cpu_id)125 dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int cpu_id)
126 {
127 #define STRING_LEN 28
128 #define COMMAND_LEN 50
129 uint32_t cpu_mask = 1;
130 int ret;
131 size_t len = 0;
132 char *temp = NULL, *token = NULL;
133 char string[STRING_LEN], command[COMMAND_LEN];
134 FILE *file;
135
136 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
137 file = fopen("/proc/interrupts", "r");
138 if (!file) {
139 DPAA2_BUS_WARN("Failed to open /proc/interrupts file");
140 return;
141 }
142 while (getline(&temp, &len, file) != -1) {
143 if ((strstr(temp, string)) != NULL) {
144 token = strtok(temp, ":");
145 break;
146 }
147 }
148
149 if (!token) {
150 DPAA2_BUS_WARN("Failed to get interrupt id for dpio.%d",
151 dpio_id);
152 if (temp)
153 free(temp);
154 fclose(file);
155 return;
156 }
157
158 cpu_mask = cpu_mask << cpu_id;
159 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
160 cpu_mask, token);
161 ret = system(command);
162 if (ret < 0)
163 DPAA2_BUS_DEBUG(
164 "Failed to affine interrupts on respective core");
165 else
166 DPAA2_BUS_DEBUG(" %s command is executed", command);
167
168 free(temp);
169 fclose(file);
170 }
171
dpaa2_dpio_intr_init(struct dpaa2_dpio_dev * dpio_dev,int cpu_id)172 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
173 {
174 struct epoll_event epoll_ev;
175 int eventfd, dpio_epoll_fd, ret;
176 int threshold = 0x3, timeout = 0xFF;
177
178 dpio_epoll_fd = epoll_create(1);
179 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
180 if (ret) {
181 DPAA2_BUS_ERR("Interrupt registeration failed");
182 return -1;
183 }
184
185 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
186 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
187
188 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
189 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
190
191 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
192 QBMAN_SWP_INTERRUPT_DQRI);
193 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
194 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
195 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
196 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
197
198 eventfd = dpio_dev->intr_handle.fd;
199 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
200 epoll_ev.data.fd = eventfd;
201
202 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
203 if (ret < 0) {
204 DPAA2_BUS_ERR("epoll_ctl failed");
205 return -1;
206 }
207 dpio_dev->epoll_fd = dpio_epoll_fd;
208
209 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, cpu_id);
210
211 return 0;
212 }
213
dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev * dpio_dev)214 static void dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev *dpio_dev)
215 {
216 int ret;
217
218 ret = rte_dpaa2_intr_disable(&dpio_dev->intr_handle, 0);
219 if (ret)
220 DPAA2_BUS_ERR("DPIO interrupt disable failed");
221
222 close(dpio_dev->epoll_fd);
223 }
224 #endif
225
226 static int
dpaa2_configure_stashing(struct dpaa2_dpio_dev * dpio_dev,int cpu_id)227 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
228 {
229 int sdest, ret;
230
231 /* Set the STASH Destination depending on Current CPU ID.
232 * Valid values of SDEST are 4,5,6,7. Where,
233 */
234 sdest = dpaa2_core_cluster_sdest(cpu_id);
235 DPAA2_BUS_DEBUG("Portal= %d CPU= %u SDEST= %d",
236 dpio_dev->index, cpu_id, sdest);
237
238 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
239 dpio_dev->token, sdest);
240 if (ret) {
241 DPAA2_BUS_ERR("%d ERROR in SDEST", ret);
242 return -1;
243 }
244
245 #ifdef RTE_EVENT_DPAA2
246 if (dpaa2_dpio_intr_init(dpio_dev, cpu_id)) {
247 DPAA2_BUS_ERR("Interrupt registration failed for dpio");
248 return -1;
249 }
250 #endif
251
252 return 0;
253 }
254
dpaa2_put_qbman_swp(struct dpaa2_dpio_dev * dpio_dev)255 static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
256 {
257 if (dpio_dev) {
258 #ifdef RTE_EVENT_DPAA2
259 dpaa2_dpio_intr_deinit(dpio_dev);
260 #endif
261 rte_atomic16_clear(&dpio_dev->ref_count);
262 }
263 }
264
dpaa2_get_qbman_swp(void)265 static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
266 {
267 struct dpaa2_dpio_dev *dpio_dev = NULL;
268 int cpu_id;
269 int ret;
270
271 /* Get DPIO dev handle from list using index */
272 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
273 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
274 break;
275 }
276 if (!dpio_dev) {
277 DPAA2_BUS_ERR("No software portal resource left");
278 return NULL;
279 }
280
281 DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu",
282 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
283
284 /* Set the Stashing Destination */
285 cpu_id = dpaa2_get_core_id();
286 if (cpu_id < 0) {
287 DPAA2_BUS_WARN("Thread not affined to a single core");
288 if (dpaa2_svr_family != SVR_LX2160A)
289 qbman_swp_update(dpio_dev->sw_portal, 1);
290 } else {
291 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
292 if (ret) {
293 DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
294 rte_atomic16_clear(&dpio_dev->ref_count);
295 return NULL;
296 }
297 }
298
299 ret = pthread_setspecific(dpaa2_portal_key, (void *)dpio_dev);
300 if (ret) {
301 DPAA2_BUS_ERR("pthread_setspecific failed with ret: %d", ret);
302 dpaa2_put_qbman_swp(dpio_dev);
303 return NULL;
304 }
305
306 return dpio_dev;
307 }
308
309 int
dpaa2_affine_qbman_swp(void)310 dpaa2_affine_qbman_swp(void)
311 {
312 struct dpaa2_dpio_dev *dpio_dev;
313 uint64_t tid = syscall(SYS_gettid);
314
315 /* Populate the dpaa2_io_portal structure */
316 if (!RTE_PER_LCORE(_dpaa2_io).dpio_dev) {
317 dpio_dev = dpaa2_get_qbman_swp();
318 if (!dpio_dev) {
319 DPAA2_BUS_ERR("Error in software portal allocation");
320 return -1;
321 }
322 RTE_PER_LCORE(_dpaa2_io).dpio_dev = dpio_dev;
323
324 DPAA2_BUS_INFO(
325 "DPAA Portal=%p (%d) is affined to thread %" PRIu64,
326 dpio_dev, dpio_dev->index, tid);
327 }
328 return 0;
329 }
330
331 int
dpaa2_affine_qbman_ethrx_swp(void)332 dpaa2_affine_qbman_ethrx_swp(void)
333 {
334 struct dpaa2_dpio_dev *dpio_dev;
335 uint64_t tid = syscall(SYS_gettid);
336
337 /* Populate the dpaa2_io_portal structure */
338 if (!RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev) {
339 dpio_dev = dpaa2_get_qbman_swp();
340 if (!dpio_dev) {
341 DPAA2_BUS_ERR("Error in software portal allocation");
342 return -1;
343 }
344 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev = dpio_dev;
345
346 DPAA2_BUS_INFO(
347 "DPAA Portal=%p (%d) is affined for eth rx to thread %"
348 PRIu64, dpio_dev, dpio_dev->index, tid);
349 }
350 return 0;
351 }
352
dpaa2_portal_finish(void * arg)353 static void dpaa2_portal_finish(void *arg)
354 {
355 RTE_SET_USED(arg);
356
357 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).dpio_dev);
358 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev);
359
360 pthread_setspecific(dpaa2_portal_key, NULL);
361 }
362
363 static int
dpaa2_create_dpio_device(int vdev_fd,struct vfio_device_info * obj_info,int object_id)364 dpaa2_create_dpio_device(int vdev_fd,
365 struct vfio_device_info *obj_info,
366 int object_id)
367 {
368 struct dpaa2_dpio_dev *dpio_dev = NULL;
369 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
370 struct qbman_swp_desc p_des;
371 struct dpio_attr attr;
372 int ret;
373
374 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
375 DPAA2_BUS_ERR("Not sufficient number of DPIO regions");
376 return -1;
377 }
378
379 dpio_dev = rte_zmalloc(NULL, sizeof(struct dpaa2_dpio_dev),
380 RTE_CACHE_LINE_SIZE);
381 if (!dpio_dev) {
382 DPAA2_BUS_ERR("Memory allocation failed for DPIO Device");
383 return -1;
384 }
385
386 dpio_dev->dpio = NULL;
387 dpio_dev->hw_id = object_id;
388 rte_atomic16_init(&dpio_dev->ref_count);
389 /* Using single portal for all devices */
390 dpio_dev->mc_portal = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
391
392 dpio_dev->dpio = rte_zmalloc(NULL, sizeof(struct fsl_mc_io),
393 RTE_CACHE_LINE_SIZE);
394 if (!dpio_dev->dpio) {
395 DPAA2_BUS_ERR("Memory allocation failure");
396 goto err;
397 }
398
399 dpio_dev->dpio->regs = dpio_dev->mc_portal;
400 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
401 &dpio_dev->token)) {
402 DPAA2_BUS_ERR("Failed to allocate IO space");
403 goto err;
404 }
405
406 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
407 DPAA2_BUS_ERR("Failed to reset dpio");
408 goto err;
409 }
410
411 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
412 DPAA2_BUS_ERR("Failed to Enable dpio");
413 goto err;
414 }
415
416 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
417 dpio_dev->token, &attr)) {
418 DPAA2_BUS_ERR("DPIO Get attribute failed");
419 goto err;
420 }
421
422 /* find the SoC type for the first time */
423 if (!dpaa2_svr_family) {
424 struct mc_soc_version mc_plat_info = {0};
425
426 if (mc_get_soc_version(dpio_dev->dpio,
427 CMD_PRI_LOW, &mc_plat_info)) {
428 DPAA2_BUS_ERR("Unable to get SoC version information");
429 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
430 dpaa2_core_cluster_base = 0x02;
431 dpaa2_cluster_sz = 4;
432 DPAA2_BUS_DEBUG("LS108x (A53) Platform Detected");
433 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
434 dpaa2_core_cluster_base = 0x00;
435 dpaa2_cluster_sz = 2;
436 DPAA2_BUS_DEBUG("LX2160 Platform Detected");
437 }
438 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
439
440 if (dpaa2_svr_family == SVR_LX2160A) {
441 dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;
442 dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;
443 } else {
444 dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;
445 dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;
446 }
447 }
448
449 if (dpaa2_svr_family == SVR_LX2160A)
450 reg_info.index = DPAA2_SWP_CENA_MEM_REGION;
451 else
452 reg_info.index = DPAA2_SWP_CENA_REGION;
453
454 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
455 DPAA2_BUS_ERR("vfio: error getting region info");
456 goto err;
457 }
458
459 dpio_dev->ce_size = reg_info.size;
460 dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
461 PROT_WRITE | PROT_READ, MAP_SHARED,
462 vdev_fd, reg_info.offset);
463
464 reg_info.index = DPAA2_SWP_CINH_REGION;
465 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
466 DPAA2_BUS_ERR("vfio: error getting region info");
467 goto err;
468 }
469
470 dpio_dev->ci_size = reg_info.size;
471 dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
472 PROT_WRITE | PROT_READ, MAP_SHARED,
473 vdev_fd, reg_info.offset);
474
475 /* Configure & setup SW portal */
476 p_des.block = NULL;
477 p_des.idx = attr.qbman_portal_id;
478 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
479 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
480 p_des.irq = -1;
481 p_des.qman_version = attr.qbman_version;
482 p_des.eqcr_mode = qman_eqcr_vb_ring;
483 p_des.cena_access_mode = qman_cena_fastest_access;
484
485 dpio_dev->sw_portal = qbman_swp_init(&p_des);
486 if (dpio_dev->sw_portal == NULL) {
487 DPAA2_BUS_ERR("QBMan SW Portal Init failed");
488 goto err;
489 }
490
491 io_space_count++;
492 dpio_dev->index = io_space_count;
493
494 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
495 DPAA2_BUS_ERR("Fail to setup interrupt for %d",
496 dpio_dev->hw_id);
497 goto err;
498 }
499
500 dpio_dev->eqresp = rte_zmalloc(NULL, MAX_EQ_RESP_ENTRIES *
501 (sizeof(struct qbman_result) +
502 sizeof(struct eqresp_metadata)),
503 RTE_CACHE_LINE_SIZE);
504 if (!dpio_dev->eqresp) {
505 DPAA2_BUS_ERR("Memory allocation failed for eqresp");
506 goto err;
507 }
508 dpio_dev->eqresp_meta = (struct eqresp_metadata *)(dpio_dev->eqresp +
509 MAX_EQ_RESP_ENTRIES);
510
511
512 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
513
514 if (!dpaa2_portal_key) {
515 /* create the key, supplying a function that'll be invoked
516 * when a portal affined thread will be deleted.
517 */
518 ret = pthread_key_create(&dpaa2_portal_key,
519 dpaa2_portal_finish);
520 if (ret) {
521 DPAA2_BUS_DEBUG("Unable to create pthread key (%d)",
522 ret);
523 goto err;
524 }
525 }
526
527 return 0;
528
529 err:
530 if (dpio_dev->dpio) {
531 if (dpio_dev->token) {
532 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
533 dpio_dev->token);
534 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
535 dpio_dev->token);
536 }
537
538 rte_free(dpio_dev->eqresp);
539 rte_free(dpio_dev->dpio);
540 }
541
542 rte_free(dpio_dev);
543
544 /* For each element in the list, cleanup */
545 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
546 if (dpio_dev->dpio) {
547 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
548 dpio_dev->token);
549 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
550 dpio_dev->token);
551 rte_free(dpio_dev->dpio);
552 }
553 rte_free(dpio_dev);
554 }
555
556 /* Preventing re-use of the list with old entries */
557 TAILQ_INIT(&dpio_dev_list);
558
559 return -1;
560 }
561
562 void
dpaa2_free_dq_storage(struct queue_storage_info_t * q_storage)563 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
564 {
565 int i = 0;
566
567 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
568 if (q_storage->dq_storage[i])
569 rte_free(q_storage->dq_storage[i]);
570 }
571 }
572
573 int
dpaa2_alloc_dq_storage(struct queue_storage_info_t * q_storage)574 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
575 {
576 int i = 0;
577
578 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
579 q_storage->dq_storage[i] = rte_malloc(NULL,
580 dpaa2_dqrr_size * sizeof(struct qbman_result),
581 RTE_CACHE_LINE_SIZE);
582 if (!q_storage->dq_storage[i])
583 goto fail;
584 }
585 return 0;
586 fail:
587 while (--i >= 0)
588 rte_free(q_storage->dq_storage[i]);
589
590 return -1;
591 }
592
593 uint32_t
dpaa2_free_eq_descriptors(void)594 dpaa2_free_eq_descriptors(void)
595 {
596 struct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;
597 struct qbman_result *eqresp;
598 struct eqresp_metadata *eqresp_meta;
599 struct dpaa2_queue *txq;
600
601 while (dpio_dev->eqresp_ci != dpio_dev->eqresp_pi) {
602 eqresp = &dpio_dev->eqresp[dpio_dev->eqresp_ci];
603 eqresp_meta = &dpio_dev->eqresp_meta[dpio_dev->eqresp_ci];
604
605 if (!qbman_result_eqresp_rspid(eqresp))
606 break;
607
608 if (qbman_result_eqresp_rc(eqresp)) {
609 txq = eqresp_meta->dpaa2_q;
610 txq->cb_eqresp_free(dpio_dev->eqresp_ci);
611 }
612 qbman_result_eqresp_set_rspid(eqresp, 0);
613
614 dpio_dev->eqresp_ci + 1 < MAX_EQ_RESP_ENTRIES ?
615 dpio_dev->eqresp_ci++ : (dpio_dev->eqresp_ci = 0);
616 }
617
618 /* Return 1 less entry so that PI and CI are never same in a
619 * case there all the EQ responses are in use.
620 */
621 if (dpio_dev->eqresp_ci > dpio_dev->eqresp_pi)
622 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi - 1;
623 else
624 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi +
625 MAX_EQ_RESP_ENTRIES - 1;
626 }
627
628 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
629 .dev_type = DPAA2_IO,
630 .create = dpaa2_create_dpio_device,
631 };
632
633 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);
634