1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #ifndef _TXGBE_TYPE_H_ 7 #define _TXGBE_TYPE_H_ 8 9 #define TXGBE_DCB_TC_MAX TXGBE_MAX_UP 10 #define TXGBE_DCB_UP_MAX TXGBE_MAX_UP 11 #define TXGBE_DCB_BWG_MAX TXGBE_MAX_UP 12 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 13 #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 14 15 #define TXGBE_RX_HDR_SIZE 256 16 #define TXGBE_RX_BUF_SIZE 2048 17 18 #define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */ 19 #define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */ 20 #define TXGBE_NUM_POOL (64) 21 #define TXGBE_PBTXSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 22 #define TXGBE_MAX_FTQF_FILTERS 128 23 #define TXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 24 #define TXGBE_MAX_UP 8 25 #define TXGBE_MAX_QP (128) 26 #define TXGBE_MAX_UTA 128 27 28 #define TXGBE_FDIR_INIT_DONE_POLL 10 29 #define TXGBE_FDIRCMD_CMD_POLL 10 30 #define TXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 31 32 #define TXGBE_ALIGN 128 /* as intel did */ 33 34 #include "txgbe_status.h" 35 #include "txgbe_osdep.h" 36 #include "txgbe_devids.h" 37 38 struct txgbe_thermal_diode_data { 39 s16 temp; 40 s16 alarm_thresh; 41 s16 dalarm_thresh; 42 }; 43 44 struct txgbe_thermal_sensor_data { 45 struct txgbe_thermal_diode_data sensor[1]; 46 }; 47 48 /* Packet buffer allocation strategies */ 49 enum { 50 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 51 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 52 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 53 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 54 }; 55 56 /* Physical layer type */ 57 #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0 58 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001 59 #define TXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002 60 #define TXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004 61 #define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008 62 #define TXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010 63 #define TXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020 64 #define TXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040 65 #define TXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080 66 #define TXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100 67 #define TXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200 68 #define TXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400 69 #define TXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800 70 #define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000 71 #define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000 72 #define TXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000 73 #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000 74 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000 75 76 /* Software ATR hash keys */ 77 #define TXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 78 #define TXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 79 80 /* Software ATR input stream values and masks */ 81 #define TXGBE_ATR_HASH_MASK 0x7fff 82 #define TXGBE_ATR_L3TYPE_MASK 0x4 83 #define TXGBE_ATR_L3TYPE_IPV4 0x0 84 #define TXGBE_ATR_L3TYPE_IPV6 0x4 85 #define TXGBE_ATR_L4TYPE_MASK 0x3 86 #define TXGBE_ATR_L4TYPE_UDP 0x1 87 #define TXGBE_ATR_L4TYPE_TCP 0x2 88 #define TXGBE_ATR_L4TYPE_SCTP 0x3 89 #define TXGBE_ATR_TUNNEL_MASK 0x10 90 #define TXGBE_ATR_TUNNEL_ANY 0x10 91 enum txgbe_atr_flow_type { 92 TXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 93 TXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 94 TXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 95 TXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 96 TXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 97 TXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 98 TXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 99 TXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 100 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, 101 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, 102 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, 103 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, 104 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, 105 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, 106 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, 107 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, 108 }; 109 110 /* Flow Director ATR input struct. */ 111 struct txgbe_atr_input { 112 /* 113 * Byte layout in order, all values with MSB first: 114 * 115 * vm_pool - 1 byte 116 * flow_type - 1 byte 117 * vlan_id - 2 bytes 118 * src_ip - 16 bytes 119 * inner_mac - 6 bytes 120 * cloud_mode - 2 bytes 121 * tni_vni - 4 bytes 122 * dst_ip - 16 bytes 123 * src_port - 2 bytes 124 * dst_port - 2 bytes 125 * flex_bytes - 2 bytes 126 * bkt_hash - 2 bytes 127 */ 128 u8 vm_pool; 129 u8 flow_type; 130 __be16 pkt_type; 131 __be32 dst_ip[4]; 132 __be32 src_ip[4]; 133 __be16 src_port; 134 __be16 dst_port; 135 __be16 flex_bytes; 136 __be16 bkt_hash; 137 }; 138 139 enum txgbe_eeprom_type { 140 txgbe_eeprom_unknown = 0, 141 txgbe_eeprom_spi, 142 txgbe_eeprom_flash, 143 txgbe_eeprom_none /* No NVM support */ 144 }; 145 146 enum txgbe_mac_type { 147 txgbe_mac_unknown = 0, 148 txgbe_mac_raptor, 149 txgbe_mac_raptor_vf, 150 txgbe_num_macs 151 }; 152 153 enum txgbe_phy_type { 154 txgbe_phy_unknown = 0, 155 txgbe_phy_none, 156 txgbe_phy_tn, 157 txgbe_phy_aq, 158 txgbe_phy_ext_1g_t, 159 txgbe_phy_cu_mtd, 160 txgbe_phy_cu_unknown, 161 txgbe_phy_qt, 162 txgbe_phy_xaui, 163 txgbe_phy_nl, 164 txgbe_phy_sfp_tyco_passive, 165 txgbe_phy_sfp_unknown_passive, 166 txgbe_phy_sfp_unknown_active, 167 txgbe_phy_sfp_avago, 168 txgbe_phy_sfp_ftl, 169 txgbe_phy_sfp_ftl_active, 170 txgbe_phy_sfp_unknown, 171 txgbe_phy_sfp_intel, 172 txgbe_phy_qsfp_unknown_passive, 173 txgbe_phy_qsfp_unknown_active, 174 txgbe_phy_qsfp_intel, 175 txgbe_phy_qsfp_unknown, 176 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */ 177 txgbe_phy_sgmii, 178 txgbe_phy_fw, 179 txgbe_phy_generic 180 }; 181 182 /* 183 * SFP+ module type IDs: 184 * 185 * ID Module Type 186 * ============= 187 * 0 SFP_DA_CU 188 * 1 SFP_SR 189 * 2 SFP_LR 190 * 3 SFP_DA_CU_CORE0 - chip-specific 191 * 4 SFP_DA_CU_CORE1 - chip-specific 192 * 5 SFP_SR/LR_CORE0 - chip-specific 193 * 6 SFP_SR/LR_CORE1 - chip-specific 194 */ 195 enum txgbe_sfp_type { 196 txgbe_sfp_type_unknown = 0, 197 txgbe_sfp_type_da_cu, 198 txgbe_sfp_type_sr, 199 txgbe_sfp_type_lr, 200 txgbe_sfp_type_da_cu_core0, 201 txgbe_sfp_type_da_cu_core1, 202 txgbe_sfp_type_srlr_core0, 203 txgbe_sfp_type_srlr_core1, 204 txgbe_sfp_type_da_act_lmt_core0, 205 txgbe_sfp_type_da_act_lmt_core1, 206 txgbe_sfp_type_1g_cu_core0, 207 txgbe_sfp_type_1g_cu_core1, 208 txgbe_sfp_type_1g_sx_core0, 209 txgbe_sfp_type_1g_sx_core1, 210 txgbe_sfp_type_1g_lx_core0, 211 txgbe_sfp_type_1g_lx_core1, 212 txgbe_sfp_type_not_present = 0xFFFE, 213 txgbe_sfp_type_not_known = 0xFFFF 214 }; 215 216 enum txgbe_media_type { 217 txgbe_media_type_unknown = 0, 218 txgbe_media_type_fiber, 219 txgbe_media_type_fiber_qsfp, 220 txgbe_media_type_copper, 221 txgbe_media_type_backplane, 222 txgbe_media_type_cx4, 223 txgbe_media_type_virtual 224 }; 225 226 /* Flow Control Settings */ 227 enum txgbe_fc_mode { 228 txgbe_fc_none = 0, 229 txgbe_fc_rx_pause, 230 txgbe_fc_tx_pause, 231 txgbe_fc_full, 232 txgbe_fc_default 233 }; 234 235 /* Smart Speed Settings */ 236 #define TXGBE_SMARTSPEED_MAX_RETRIES 3 237 enum txgbe_smart_speed { 238 txgbe_smart_speed_auto = 0, 239 txgbe_smart_speed_on, 240 txgbe_smart_speed_off 241 }; 242 243 /* PCI bus types */ 244 enum txgbe_bus_type { 245 txgbe_bus_type_unknown = 0, 246 txgbe_bus_type_pci, 247 txgbe_bus_type_pcix, 248 txgbe_bus_type_pci_express, 249 txgbe_bus_type_internal, 250 txgbe_bus_type_reserved 251 }; 252 253 /* PCI bus speeds */ 254 enum txgbe_bus_speed { 255 txgbe_bus_speed_unknown = 0, 256 txgbe_bus_speed_33 = 33, 257 txgbe_bus_speed_66 = 66, 258 txgbe_bus_speed_100 = 100, 259 txgbe_bus_speed_120 = 120, 260 txgbe_bus_speed_133 = 133, 261 txgbe_bus_speed_2500 = 2500, 262 txgbe_bus_speed_5000 = 5000, 263 txgbe_bus_speed_8000 = 8000, 264 txgbe_bus_speed_reserved 265 }; 266 267 /* PCI bus widths */ 268 enum txgbe_bus_width { 269 txgbe_bus_width_unknown = 0, 270 txgbe_bus_width_pcie_x1 = 1, 271 txgbe_bus_width_pcie_x2 = 2, 272 txgbe_bus_width_pcie_x4 = 4, 273 txgbe_bus_width_pcie_x8 = 8, 274 txgbe_bus_width_32 = 32, 275 txgbe_bus_width_64 = 64, 276 txgbe_bus_width_reserved 277 }; 278 279 struct txgbe_hw; 280 281 struct txgbe_addr_filter_info { 282 u32 num_mc_addrs; 283 u32 rar_used_count; 284 u32 mta_in_use; 285 u32 overflow_promisc; 286 bool user_set_promisc; 287 }; 288 289 /* Bus parameters */ 290 struct txgbe_bus_info { 291 s32 (*get_bus_info)(struct txgbe_hw *hw); 292 void (*set_lan_id)(struct txgbe_hw *hw); 293 294 enum txgbe_bus_speed speed; 295 enum txgbe_bus_width width; 296 enum txgbe_bus_type type; 297 298 u16 func; 299 u8 lan_id; 300 u16 instance_id; 301 }; 302 303 /* Flow control parameters */ 304 struct txgbe_fc_info { 305 u32 high_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl High-water */ 306 u32 low_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl Low-water */ 307 u16 pause_time; /* Flow Control Pause timer */ 308 bool send_xon; /* Flow control send XON */ 309 bool strict_ieee; /* Strict IEEE mode */ 310 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 311 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 312 enum txgbe_fc_mode current_mode; /* FC mode in effect */ 313 enum txgbe_fc_mode requested_mode; /* FC mode requested by caller */ 314 }; 315 316 /* Statistics counters collected by the MAC */ 317 /* PB[] RxTx */ 318 struct txgbe_pb_stats { 319 u64 tx_pb_xon_packets; 320 u64 rx_pb_xon_packets; 321 u64 tx_pb_xoff_packets; 322 u64 rx_pb_xoff_packets; 323 u64 rx_pb_dropped; 324 u64 rx_pb_mbuf_alloc_errors; 325 u64 tx_pb_xon2off_packets; 326 }; 327 328 /* QP[] RxTx */ 329 struct txgbe_qp_stats { 330 u64 rx_qp_packets; 331 u64 tx_qp_packets; 332 u64 rx_qp_bytes; 333 u64 tx_qp_bytes; 334 u64 rx_qp_mc_packets; 335 }; 336 337 struct txgbe_hw_stats { 338 /* MNG RxTx */ 339 u64 mng_bmc2host_packets; 340 u64 mng_host2bmc_packets; 341 /* Basix RxTx */ 342 u64 rx_packets; 343 u64 tx_packets; 344 u64 rx_bytes; 345 u64 tx_bytes; 346 u64 rx_total_bytes; 347 u64 rx_total_packets; 348 u64 tx_total_packets; 349 u64 rx_total_missed_packets; 350 u64 rx_broadcast_packets; 351 u64 tx_broadcast_packets; 352 u64 rx_multicast_packets; 353 u64 tx_multicast_packets; 354 u64 rx_management_packets; 355 u64 tx_management_packets; 356 u64 rx_management_dropped; 357 u64 rx_dma_drop; 358 u64 rx_drop_packets; 359 360 /* Basic Error */ 361 u64 rx_crc_errors; 362 u64 rx_illegal_byte_errors; 363 u64 rx_error_bytes; 364 u64 rx_mac_short_packet_dropped; 365 u64 rx_length_errors; 366 u64 rx_undersize_errors; 367 u64 rx_fragment_errors; 368 u64 rx_oversize_errors; 369 u64 rx_jabber_errors; 370 u64 rx_l3_l4_xsum_error; 371 u64 mac_local_errors; 372 u64 mac_remote_errors; 373 374 /* Flow Director */ 375 u64 flow_director_added_filters; 376 u64 flow_director_removed_filters; 377 u64 flow_director_filter_add_errors; 378 u64 flow_director_filter_remove_errors; 379 u64 flow_director_matched_filters; 380 u64 flow_director_missed_filters; 381 382 /* FCoE */ 383 u64 rx_fcoe_crc_errors; 384 u64 rx_fcoe_mbuf_allocation_errors; 385 u64 rx_fcoe_dropped; 386 u64 rx_fcoe_packets; 387 u64 tx_fcoe_packets; 388 u64 rx_fcoe_bytes; 389 u64 tx_fcoe_bytes; 390 u64 rx_fcoe_no_ddp; 391 u64 rx_fcoe_no_ddp_ext_buff; 392 393 /* MACSEC */ 394 u64 tx_macsec_pkts_untagged; 395 u64 tx_macsec_pkts_encrypted; 396 u64 tx_macsec_pkts_protected; 397 u64 tx_macsec_octets_encrypted; 398 u64 tx_macsec_octets_protected; 399 u64 rx_macsec_pkts_untagged; 400 u64 rx_macsec_pkts_badtag; 401 u64 rx_macsec_pkts_nosci; 402 u64 rx_macsec_pkts_unknownsci; 403 u64 rx_macsec_octets_decrypted; 404 u64 rx_macsec_octets_validated; 405 u64 rx_macsec_sc_pkts_unchecked; 406 u64 rx_macsec_sc_pkts_delayed; 407 u64 rx_macsec_sc_pkts_late; 408 u64 rx_macsec_sa_pkts_ok; 409 u64 rx_macsec_sa_pkts_invalid; 410 u64 rx_macsec_sa_pkts_notvalid; 411 u64 rx_macsec_sa_pkts_unusedsa; 412 u64 rx_macsec_sa_pkts_notusingsa; 413 414 /* MAC RxTx */ 415 u64 rx_size_64_packets; 416 u64 rx_size_65_to_127_packets; 417 u64 rx_size_128_to_255_packets; 418 u64 rx_size_256_to_511_packets; 419 u64 rx_size_512_to_1023_packets; 420 u64 rx_size_1024_to_max_packets; 421 u64 tx_size_64_packets; 422 u64 tx_size_65_to_127_packets; 423 u64 tx_size_128_to_255_packets; 424 u64 tx_size_256_to_511_packets; 425 u64 tx_size_512_to_1023_packets; 426 u64 tx_size_1024_to_max_packets; 427 428 /* Flow Control */ 429 u64 tx_xon_packets; 430 u64 rx_xon_packets; 431 u64 tx_xoff_packets; 432 u64 rx_xoff_packets; 433 434 /* PB[] RxTx */ 435 struct { 436 u64 rx_up_packets; 437 u64 tx_up_packets; 438 u64 rx_up_bytes; 439 u64 tx_up_bytes; 440 u64 rx_up_drop_packets; 441 442 u64 tx_up_xon_packets; 443 u64 rx_up_xon_packets; 444 u64 tx_up_xoff_packets; 445 u64 rx_up_xoff_packets; 446 u64 rx_up_dropped; 447 u64 rx_up_mbuf_alloc_errors; 448 u64 tx_up_xon2off_packets; 449 } up[TXGBE_MAX_UP]; 450 451 /* QP[] RxTx */ 452 struct { 453 u64 rx_qp_packets; 454 u64 tx_qp_packets; 455 u64 rx_qp_bytes; 456 u64 tx_qp_bytes; 457 u64 rx_qp_mc_packets; 458 } qp[TXGBE_MAX_QP]; 459 460 }; 461 462 /* iterator type for walking multicast address lists */ 463 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr, 464 u32 *vmdq); 465 466 struct txgbe_link_info { 467 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val); 468 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg, 469 u16 *val); 470 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val); 471 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg, 472 u16 val); 473 474 u8 addr; 475 }; 476 477 struct txgbe_rom_info { 478 s32 (*init_params)(struct txgbe_hw *hw); 479 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data); 480 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data); 481 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words, 482 void *data); 483 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data); 484 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data); 485 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data); 486 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data); 487 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words, 488 void *data); 489 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data); 490 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data); 491 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val); 492 s32 (*update_checksum)(struct txgbe_hw *hw); 493 s32 (*calc_checksum)(struct txgbe_hw *hw); 494 495 enum txgbe_eeprom_type type; 496 u32 semaphore_delay; 497 u16 word_size; 498 u16 address_bits; 499 u16 word_page_size; 500 u16 ctrl_word_3; 501 502 u32 sw_addr; 503 }; 504 505 struct txgbe_flash_info { 506 u32 semaphore_delay; 507 u32 dword_size; 508 u16 address_bits; 509 }; 510 511 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 512 struct txgbe_mac_info { 513 s32 (*init_hw)(struct txgbe_hw *hw); 514 s32 (*reset_hw)(struct txgbe_hw *hw); 515 s32 (*start_hw)(struct txgbe_hw *hw); 516 s32 (*stop_hw)(struct txgbe_hw *hw); 517 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw); 518 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr); 519 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr); 520 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr); 521 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps); 522 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix, 523 u16 *wwpn_prefix); 524 s32 (*setup_sfp)(struct txgbe_hw *hw); 525 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval); 526 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw); 527 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw); 528 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw); 529 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw); 530 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask); 531 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask); 532 u64 (*autoc_read)(struct txgbe_hw *hw); 533 void (*autoc_write)(struct txgbe_hw *hw, u64 value); 534 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value); 535 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value); 536 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api); 537 538 /* Link */ 539 void (*disable_tx_laser)(struct txgbe_hw *hw); 540 void (*enable_tx_laser)(struct txgbe_hw *hw); 541 void (*flap_tx_laser)(struct txgbe_hw *hw); 542 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed, 543 bool autoneg_wait_to_complete); 544 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed, 545 bool autoneg_wait_to_complete); 546 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, 547 bool *link_up, bool link_up_wait_to_complete); 548 s32 (*get_link_capabilities)(struct txgbe_hw *hw, 549 u32 *speed, bool *autoneg); 550 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed); 551 552 /* Packet Buffer manipulation */ 553 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom, 554 int strategy); 555 556 /* LED */ 557 s32 (*led_on)(struct txgbe_hw *hw, u32 index); 558 s32 (*led_off)(struct txgbe_hw *hw, u32 index); 559 560 /* RAR, Multicast, VLAN */ 561 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 562 u32 enable_addr); 563 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr); 564 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index); 565 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq); 566 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq); 567 s32 (*init_rx_addrs)(struct txgbe_hw *hw); 568 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list, 569 u32 mc_addr_count, 570 txgbe_mc_addr_itr func, bool clear); 571 s32 (*clear_vfta)(struct txgbe_hw *hw); 572 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan, 573 u32 vind, bool vlan_on, bool vlvf_bypass); 574 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind, 575 bool vlan_on, u32 *vfta_delta, u32 vfta, 576 bool vlvf_bypass); 577 s32 (*init_uta_tables)(struct txgbe_hw *hw); 578 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf); 579 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw, 580 bool enable, int vf); 581 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode); 582 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size); 583 584 /* Flow Control */ 585 s32 (*fc_enable)(struct txgbe_hw *hw); 586 s32 (*setup_fc)(struct txgbe_hw *hw); 587 void (*fc_autoneg)(struct txgbe_hw *hw); 588 589 /* Manageability interface */ 590 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build, 591 u8 ver, u16 len, const char *driver_ver); 592 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw); 593 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw); 594 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map); 595 void (*disable_rx)(struct txgbe_hw *hw); 596 void (*enable_rx)(struct txgbe_hw *hw); 597 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw, 598 bool enable, int vf); 599 s32 (*dmac_update_tcs)(struct txgbe_hw *hw); 600 s32 (*dmac_config_tcs)(struct txgbe_hw *hw); 601 s32 (*dmac_config)(struct txgbe_hw *hw); 602 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee); 603 604 s32 (*kr_handle)(struct txgbe_hw *hw); 605 void (*bp_down_event)(struct txgbe_hw *hw); 606 607 enum txgbe_mac_type type; 608 u8 addr[ETH_ADDR_LEN]; 609 u8 perm_addr[ETH_ADDR_LEN]; 610 u8 san_addr[ETH_ADDR_LEN]; 611 /* prefix for World Wide Node Name (WWNN) */ 612 u16 wwnn_prefix; 613 /* prefix for World Wide Port Name (WWPN) */ 614 u16 wwpn_prefix; 615 #define TXGBE_MAX_MTA 128 616 u32 mta_shadow[TXGBE_MAX_MTA]; 617 s32 mc_filter_type; 618 u32 mcft_size; 619 u32 vft_size; 620 u32 num_rar_entries; 621 u32 rx_pb_size; 622 u32 max_tx_queues; 623 u32 max_rx_queues; 624 u64 autoc; 625 u64 orig_autoc; /* cached value of AUTOC */ 626 u8 san_mac_rar_index; 627 bool get_link_status; 628 bool orig_link_settings_stored; 629 bool autotry_restart; 630 u8 flags; 631 struct txgbe_thermal_sensor_data thermal_sensor_data; 632 bool set_lben; 633 u32 max_link_up_time; 634 }; 635 636 struct txgbe_phy_info { 637 u32 (*get_media_type)(struct txgbe_hw *hw); 638 s32 (*identify)(struct txgbe_hw *hw); 639 s32 (*identify_sfp)(struct txgbe_hw *hw); 640 s32 (*init)(struct txgbe_hw *hw); 641 s32 (*reset)(struct txgbe_hw *hw); 642 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr, 643 u32 device_type, u16 *phy_data); 644 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr, 645 u32 device_type, u16 phy_data); 646 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr, 647 u32 device_type, u16 *phy_data); 648 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr, 649 u32 device_type, u16 phy_data); 650 s32 (*setup_link)(struct txgbe_hw *hw); 651 s32 (*setup_internal_link)(struct txgbe_hw *hw); 652 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed, 653 bool autoneg_wait_to_complete); 654 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up); 655 s32 (*get_fw_version)(struct txgbe_hw *hw, u32 *fw_version); 656 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, 657 u8 dev_addr, u8 *data); 658 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, 659 u8 dev_addr, u8 data); 660 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset, 661 u8 *sff8472_data); 662 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset, 663 u8 *eeprom_data); 664 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset, 665 u8 eeprom_data); 666 s32 (*check_overtemp)(struct txgbe_hw *hw); 667 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on); 668 s32 (*handle_lasi)(struct txgbe_hw *hw); 669 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr, 670 u8 *value); 671 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr, 672 u8 value); 673 674 enum txgbe_phy_type type; 675 u32 addr; 676 u32 id; 677 enum txgbe_sfp_type sfp_type; 678 bool sfp_setup_needed; 679 u32 revision; 680 u32 media_type; 681 u32 phy_semaphore_mask; 682 bool reset_disable; 683 u32 autoneg_advertised; 684 u32 speeds_supported; 685 enum txgbe_smart_speed smart_speed; 686 bool smart_speed_active; 687 bool multispeed_fiber; 688 bool qsfp_shared_i2c_bus; 689 u32 nw_mng_if_sel; 690 u32 link_mode; 691 692 /* Some features need tri-state capability */ 693 u16 ffe_set; 694 u16 ffe_main; 695 u16 ffe_pre; 696 u16 ffe_post; 697 }; 698 699 #define TXGBE_DEVARG_BP_AUTO "auto_neg" 700 #define TXGBE_DEVARG_KR_POLL "poll" 701 #define TXGBE_DEVARG_KR_PRESENT "present" 702 #define TXGBE_DEVARG_KX_SGMII "sgmii" 703 #define TXGBE_DEVARG_FFE_SET "ffe_set" 704 #define TXGBE_DEVARG_FFE_MAIN "ffe_main" 705 #define TXGBE_DEVARG_FFE_PRE "ffe_pre" 706 #define TXGBE_DEVARG_FFE_POST "ffe_post" 707 708 static const char * const txgbe_valid_arguments[] = { 709 TXGBE_DEVARG_BP_AUTO, 710 TXGBE_DEVARG_KR_POLL, 711 TXGBE_DEVARG_KR_PRESENT, 712 TXGBE_DEVARG_KX_SGMII, 713 TXGBE_DEVARG_FFE_SET, 714 TXGBE_DEVARG_FFE_MAIN, 715 TXGBE_DEVARG_FFE_PRE, 716 TXGBE_DEVARG_FFE_POST, 717 NULL 718 }; 719 720 struct txgbe_mbx_stats { 721 u32 msgs_tx; 722 u32 msgs_rx; 723 724 u32 acks; 725 u32 reqs; 726 u32 rsts; 727 }; 728 729 struct txgbe_mbx_info { 730 void (*init_params)(struct txgbe_hw *hw); 731 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number); 732 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number); 733 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size, 734 u16 mbx_id); 735 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size, 736 u16 mbx_id); 737 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id); 738 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id); 739 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id); 740 741 struct txgbe_mbx_stats stats; 742 u32 timeout; 743 u32 usec_delay; 744 u32 v2p_mailbox; 745 u16 size; 746 }; 747 748 enum txgbe_isb_idx { 749 TXGBE_ISB_HEADER, 750 TXGBE_ISB_MISC, 751 TXGBE_ISB_VEC0, 752 TXGBE_ISB_VEC1, 753 TXGBE_ISB_MAX 754 }; 755 756 struct txgbe_devargs { 757 u16 auto_neg; 758 u16 poll; 759 u16 present; 760 u16 sgmii; 761 }; 762 763 struct txgbe_hw { 764 void IOMEM *hw_addr; 765 void *back; 766 struct txgbe_mac_info mac; 767 struct txgbe_addr_filter_info addr_ctrl; 768 struct txgbe_fc_info fc; 769 struct txgbe_phy_info phy; 770 struct txgbe_link_info link; 771 struct txgbe_rom_info rom; 772 struct txgbe_flash_info flash; 773 struct txgbe_bus_info bus; 774 struct txgbe_mbx_info mbx; 775 u16 device_id; 776 u16 vendor_id; 777 u16 subsystem_device_id; 778 u16 subsystem_vendor_id; 779 u8 revision_id; 780 bool adapter_stopped; 781 int api_version; 782 bool allow_unsupported_sfp; 783 bool need_crosstalk_fix; 784 bool dev_start; 785 struct txgbe_devargs devarg; 786 787 uint64_t isb_dma; 788 void IOMEM *isb_mem; 789 u16 nb_rx_queues; 790 u16 nb_tx_queues; 791 792 u32 fw_version; 793 u32 mode; 794 enum txgbe_link_status { 795 TXGBE_LINK_STATUS_NONE = 0, 796 TXGBE_LINK_STATUS_KX, 797 TXGBE_LINK_STATUS_KX4 798 } link_status; 799 enum txgbe_reset_type { 800 TXGBE_LAN_RESET = 0, 801 TXGBE_SW_RESET, 802 TXGBE_GLOBAL_RESET 803 } reset_type; 804 805 u32 q_rx_regs[128 * 4]; 806 u32 q_tx_regs[128 * 4]; 807 bool offset_loaded; 808 bool rx_loaded; 809 struct { 810 u64 rx_qp_packets; 811 u64 tx_qp_packets; 812 u64 rx_qp_bytes; 813 u64 tx_qp_bytes; 814 u64 rx_qp_mc_packets; 815 } qp_last[TXGBE_MAX_QP]; 816 }; 817 818 struct txgbe_backplane_ability { 819 u32 next_page; /* Next Page (bit0) */ 820 u32 link_ability; /* Link Ability (bit[7:0]) */ 821 u32 fec_ability; /* FEC Request (bit1), FEC Enable (bit0) */ 822 u32 current_link_mode; /* current link mode for local device */ 823 }; 824 825 #include "txgbe_regs.h" 826 #include "txgbe_dummy.h" 827 828 #endif /* _TXGBE_TYPE_H_ */ 829