1 /***********************license start***************
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38 ***********************license end**************************************/
39
40
41 /**
42 * cvmx-dbg-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon dbg.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_DBG_DEFS_H__
53 #define __CVMX_DBG_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
CVMX_DBG_DATA_FUNC(void)57 static inline uint64_t CVMX_DBG_DATA_FUNC(void)
58 {
59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
60 cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
62 }
63 #else
64 #define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
65 #endif
66
67 /**
68 * cvmx_dbg_data
69 *
70 * DBG_DATA = Debug Data Register
71 *
72 * Value returned on the debug-data lines from the RSLs
73 */
74 union cvmx_dbg_data {
75 uint64_t u64;
76 struct cvmx_dbg_data_s {
77 #ifdef __BIG_ENDIAN_BITFIELD
78 uint64_t reserved_23_63 : 41;
79 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
80 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
81 debug select value. */
82 uint64_t data : 17; /**< Value on the debug data lines. */
83 #else
84 uint64_t data : 17;
85 uint64_t dsel_ext : 1;
86 uint64_t c_mul : 5;
87 uint64_t reserved_23_63 : 41;
88 #endif
89 } s;
90 struct cvmx_dbg_data_cn30xx {
91 #ifdef __BIG_ENDIAN_BITFIELD
92 uint64_t reserved_31_63 : 33;
93 uint64_t pll_mul : 3; /**< pll_mul pins sampled at DCOK assertion */
94 uint64_t reserved_23_27 : 5;
95 uint64_t c_mul : 5; /**< Core PLL multiplier sampled at DCOK assertion */
96 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
97 debug select value. */
98 uint64_t data : 17; /**< Value on the debug data lines. */
99 #else
100 uint64_t data : 17;
101 uint64_t dsel_ext : 1;
102 uint64_t c_mul : 5;
103 uint64_t reserved_23_27 : 5;
104 uint64_t pll_mul : 3;
105 uint64_t reserved_31_63 : 33;
106 #endif
107 } cn30xx;
108 struct cvmx_dbg_data_cn30xx cn31xx;
109 struct cvmx_dbg_data_cn38xx {
110 #ifdef __BIG_ENDIAN_BITFIELD
111 uint64_t reserved_29_63 : 35;
112 uint64_t d_mul : 4; /**< D_MUL pins sampled on DCOK assertion */
113 uint64_t dclk_mul2 : 1; /**< Should always be set for fast DDR-II operation */
114 uint64_t cclk_div2 : 1; /**< Should always be clear for fast core clock */
115 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
116 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
117 debug select value. */
118 uint64_t data : 17; /**< Value on the debug data lines. */
119 #else
120 uint64_t data : 17;
121 uint64_t dsel_ext : 1;
122 uint64_t c_mul : 5;
123 uint64_t cclk_div2 : 1;
124 uint64_t dclk_mul2 : 1;
125 uint64_t d_mul : 4;
126 uint64_t reserved_29_63 : 35;
127 #endif
128 } cn38xx;
129 struct cvmx_dbg_data_cn38xx cn38xxp2;
130 struct cvmx_dbg_data_cn30xx cn50xx;
131 struct cvmx_dbg_data_cn58xx {
132 #ifdef __BIG_ENDIAN_BITFIELD
133 uint64_t reserved_29_63 : 35;
134 uint64_t rem : 6; /**< Remaining debug_select pins sampled at DCOK */
135 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
136 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
137 debug select value. */
138 uint64_t data : 17; /**< Value on the debug data lines. */
139 #else
140 uint64_t data : 17;
141 uint64_t dsel_ext : 1;
142 uint64_t c_mul : 5;
143 uint64_t rem : 6;
144 uint64_t reserved_29_63 : 35;
145 #endif
146 } cn58xx;
147 struct cvmx_dbg_data_cn58xx cn58xxp1;
148 };
149 typedef union cvmx_dbg_data cvmx_dbg_data_t;
150
151 #endif
152