Home
last modified time | relevance | path

Searched defs:csr_base_addr (Results 1 – 3 of 3) sorted by relevance

/dpdk/drivers/common/qat/qat_adf/
H A Dadf_transport_access_macros_gen4vf.h13 #define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \ argument
28 #define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \ argument
33 #define WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value) \ argument
38 #define WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value) \ argument
43 #define WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value) \ argument
H A Dadf_transport_access_macros.h94 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
97 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
100 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
103 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
106 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
116 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ argument
119 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ argument
122 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ argument
129 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
132 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ argument
[all …]
H A Dadf_transport_access_macros_gen4.h22 #define WRITE_CSR_RING_BASE_GEN4(csr_base_addr, bank, ring, value) \ argument
37 #define WRITE_CSR_RING_CONFIG_GEN4(csr_base_addr, bank, ring, value) \ argument
42 #define WRITE_CSR_RING_TAIL_GEN4(csr_base_addr, bank, ring, value) \ argument
47 #define WRITE_CSR_RING_HEAD_GEN4(csr_base_addr, bank, ring, value) \ argument