1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/isa/icu.h>
68 #include <x86/vmware.h>
69
70 #ifdef __i386__
71 #define IDENTBLUE_CYRIX486 0
72 #define IDENTBLUE_IBMCPU 1
73 #define IDENTBLUE_CYRIXM2 2
74
75 static void identifycyrix(void);
76 static void print_transmeta_info(void);
77 #endif
78 static u_int find_cpu_vendor_id(void);
79 static void print_AMD_info(void);
80 static void print_INTEL_info(void);
81 static void print_INTEL_TLB(u_int data);
82 static void print_hypervisor_info(void);
83 static void print_svm_info(void);
84 static void print_via_padlock_info(void);
85 static void print_vmx_info(void);
86
87 #ifdef __i386__
88 int cpu; /* Are we 386, 386sx, 486, etc? */
89 int cpu_class;
90 #endif
91 u_int cpu_feature; /* Feature flags */
92 u_int cpu_feature2; /* Feature flags */
93 u_int amd_feature; /* AMD feature flags */
94 u_int amd_feature2; /* AMD feature flags */
95 u_int amd_rascap; /* AMD RAS capabilities */
96 u_int amd_pminfo; /* AMD advanced power management info */
97 u_int amd_extended_feature_extensions;
98 u_int via_feature_rng; /* VIA RNG features */
99 u_int via_feature_xcrypt; /* VIA ACE features */
100 u_int cpu_high; /* Highest arg to CPUID */
101 u_int cpu_exthigh; /* Highest arg to extended CPUID */
102 u_int cpu_id; /* Stepping ID */
103 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
104 u_int cpu_procinfo2; /* Multicore info */
105 u_int cpu_procinfo3;
106 char cpu_vendor[20]; /* CPU Origin code */
107 u_int cpu_vendor_id; /* CPU vendor ID */
108 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
109 u_int cpu_clflush_line_size = 32;
110 u_int cpu_stdext_feature; /* %ebx */
111 u_int cpu_stdext_feature2; /* %ecx */
112 u_int cpu_stdext_feature3; /* %edx */
113 uint64_t cpu_ia32_arch_caps;
114 u_int cpu_max_ext_state_size;
115 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
116 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
117 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
118 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
119 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
120 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
121 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
122 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
123 const char machine[] = MACHINE;
124
125 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
126 &via_feature_rng, 0,
127 "VIA RNG feature available in CPU");
128 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
129 &via_feature_xcrypt, 0,
130 "VIA xcrypt feature available in CPU");
131
132 #ifdef __amd64__
133 #ifdef SCTL_MASK32
134 extern int adaptive_machine_arch;
135 #endif
136
137 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)138 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
139 {
140 #ifdef SCTL_MASK32
141 static const char machine32[] = "i386";
142 #endif
143 int error;
144
145 #ifdef SCTL_MASK32
146 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
147 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
148 else
149 #endif
150 error = SYSCTL_OUT(req, machine, sizeof(machine));
151 return (error);
152
153 }
154 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
155 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
156 #else
157 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
158 machine, "Machine class");
159 #endif
160
161 char cpu_model[128];
162 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
163 cpu_model, 0, "Machine model");
164
165 static int hw_clockrate;
166 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
167 &hw_clockrate, 0, "CPU instruction clock rate");
168
169 u_int hv_base;
170 u_int hv_high;
171 char hv_vendor[16];
172 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
173 0, "Hypervisor vendor");
174
175 static eventhandler_tag tsc_post_tag;
176
177 static char cpu_brand[48];
178
179 #ifdef __i386__
180 #define MAX_BRAND_INDEX 8
181
182 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
183 NULL, /* No brand */
184 "Intel Celeron",
185 "Intel Pentium III",
186 "Intel Pentium III Xeon",
187 NULL,
188 NULL,
189 NULL,
190 NULL,
191 "Intel Pentium 4"
192 };
193
194 static struct {
195 char *cpu_name;
196 int cpu_class;
197 } cpus[] = {
198 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
199 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
200 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
201 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
202 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
203 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
204 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
205 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
206 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
207 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
208 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
209 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
210 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
211 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
212 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
213 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
214 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
215 };
216 #endif
217
218 static struct {
219 char *vendor;
220 u_int vendor_id;
221 } cpu_vendors[] = {
222 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
223 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
224 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
225 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
226 #ifdef __i386__
227 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
228 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
229 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
230 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
231 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
232 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
233 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
234 #if 0
235 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
236 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
237 #endif
238 #endif
239 };
240
241 void
printcpuinfo(void)242 printcpuinfo(void)
243 {
244 u_int regs[4], i;
245 char *brand;
246
247 printf("CPU: ");
248 #ifdef __i386__
249 cpu_class = cpus[cpu].cpu_class;
250 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
251 #else
252 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
253 #endif
254
255 /* Check for extended CPUID information and a processor name. */
256 if (cpu_exthigh >= 0x80000004) {
257 brand = cpu_brand;
258 for (i = 0x80000002; i < 0x80000005; i++) {
259 do_cpuid(i, regs);
260 memcpy(brand, regs, sizeof(regs));
261 brand += sizeof(regs);
262 }
263 }
264
265 switch (cpu_vendor_id) {
266 case CPU_VENDOR_INTEL:
267 #ifdef __i386__
268 if ((cpu_id & 0xf00) > 0x300) {
269 u_int brand_index;
270
271 cpu_model[0] = '\0';
272
273 switch (cpu_id & 0x3000) {
274 case 0x1000:
275 strcpy(cpu_model, "Overdrive ");
276 break;
277 case 0x2000:
278 strcpy(cpu_model, "Dual ");
279 break;
280 }
281
282 switch (cpu_id & 0xf00) {
283 case 0x400:
284 strcat(cpu_model, "i486 ");
285 /* Check the particular flavor of 486 */
286 switch (cpu_id & 0xf0) {
287 case 0x00:
288 case 0x10:
289 strcat(cpu_model, "DX");
290 break;
291 case 0x20:
292 strcat(cpu_model, "SX");
293 break;
294 case 0x30:
295 strcat(cpu_model, "DX2");
296 break;
297 case 0x40:
298 strcat(cpu_model, "SL");
299 break;
300 case 0x50:
301 strcat(cpu_model, "SX2");
302 break;
303 case 0x70:
304 strcat(cpu_model,
305 "DX2 Write-Back Enhanced");
306 break;
307 case 0x80:
308 strcat(cpu_model, "DX4");
309 break;
310 }
311 break;
312 case 0x500:
313 /* Check the particular flavor of 586 */
314 strcat(cpu_model, "Pentium");
315 switch (cpu_id & 0xf0) {
316 case 0x00:
317 strcat(cpu_model, " A-step");
318 break;
319 case 0x10:
320 strcat(cpu_model, "/P5");
321 break;
322 case 0x20:
323 strcat(cpu_model, "/P54C");
324 break;
325 case 0x30:
326 strcat(cpu_model, "/P24T");
327 break;
328 case 0x40:
329 strcat(cpu_model, "/P55C");
330 break;
331 case 0x70:
332 strcat(cpu_model, "/P54C");
333 break;
334 case 0x80:
335 strcat(cpu_model, "/P55C (quarter-micron)");
336 break;
337 default:
338 /* nothing */
339 break;
340 }
341 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
342 /*
343 * XXX - If/when Intel fixes the bug, this
344 * should also check the version of the
345 * CPU, not just that it's a Pentium.
346 */
347 has_f00f_bug = 1;
348 #endif
349 break;
350 case 0x600:
351 /* Check the particular flavor of 686 */
352 switch (cpu_id & 0xf0) {
353 case 0x00:
354 strcat(cpu_model, "Pentium Pro A-step");
355 break;
356 case 0x10:
357 strcat(cpu_model, "Pentium Pro");
358 break;
359 case 0x30:
360 case 0x50:
361 case 0x60:
362 strcat(cpu_model,
363 "Pentium II/Pentium II Xeon/Celeron");
364 cpu = CPU_PII;
365 break;
366 case 0x70:
367 case 0x80:
368 case 0xa0:
369 case 0xb0:
370 strcat(cpu_model,
371 "Pentium III/Pentium III Xeon/Celeron");
372 cpu = CPU_PIII;
373 break;
374 default:
375 strcat(cpu_model, "Unknown 80686");
376 break;
377 }
378 break;
379 case 0xf00:
380 strcat(cpu_model, "Pentium 4");
381 cpu = CPU_P4;
382 break;
383 default:
384 strcat(cpu_model, "unknown");
385 break;
386 }
387
388 /*
389 * If we didn't get a brand name from the extended
390 * CPUID, try to look it up in the brand table.
391 */
392 if (cpu_high > 0 && *cpu_brand == '\0') {
393 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
394 if (brand_index <= MAX_BRAND_INDEX &&
395 cpu_brandtable[brand_index] != NULL)
396 strcpy(cpu_brand,
397 cpu_brandtable[brand_index]);
398 }
399 }
400 #else
401 /* Please make up your mind folks! */
402 strcat(cpu_model, "EM64T");
403 #endif
404 break;
405 case CPU_VENDOR_AMD:
406 /*
407 * Values taken from AMD Processor Recognition
408 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
409 * (also describes ``Features'' encodings.
410 */
411 strcpy(cpu_model, "AMD ");
412 #ifdef __i386__
413 switch (cpu_id & 0xFF0) {
414 case 0x410:
415 strcat(cpu_model, "Standard Am486DX");
416 break;
417 case 0x430:
418 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
419 break;
420 case 0x470:
421 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
422 break;
423 case 0x480:
424 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
425 break;
426 case 0x490:
427 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
428 break;
429 case 0x4E0:
430 strcat(cpu_model, "Am5x86 Write-Through");
431 break;
432 case 0x4F0:
433 strcat(cpu_model, "Am5x86 Write-Back");
434 break;
435 case 0x500:
436 strcat(cpu_model, "K5 model 0");
437 break;
438 case 0x510:
439 strcat(cpu_model, "K5 model 1");
440 break;
441 case 0x520:
442 strcat(cpu_model, "K5 PR166 (model 2)");
443 break;
444 case 0x530:
445 strcat(cpu_model, "K5 PR200 (model 3)");
446 break;
447 case 0x560:
448 strcat(cpu_model, "K6");
449 break;
450 case 0x570:
451 strcat(cpu_model, "K6 266 (model 1)");
452 break;
453 case 0x580:
454 strcat(cpu_model, "K6-2");
455 break;
456 case 0x590:
457 strcat(cpu_model, "K6-III");
458 break;
459 case 0x5a0:
460 strcat(cpu_model, "Geode LX");
461 break;
462 default:
463 strcat(cpu_model, "Unknown");
464 break;
465 }
466 #else
467 if ((cpu_id & 0xf00) == 0xf00)
468 strcat(cpu_model, "AMD64 Processor");
469 else
470 strcat(cpu_model, "Unknown");
471 #endif
472 break;
473 #ifdef __i386__
474 case CPU_VENDOR_CYRIX:
475 strcpy(cpu_model, "Cyrix ");
476 switch (cpu_id & 0xff0) {
477 case 0x440:
478 strcat(cpu_model, "MediaGX");
479 break;
480 case 0x520:
481 strcat(cpu_model, "6x86");
482 break;
483 case 0x540:
484 cpu_class = CPUCLASS_586;
485 strcat(cpu_model, "GXm");
486 break;
487 case 0x600:
488 strcat(cpu_model, "6x86MX");
489 break;
490 default:
491 /*
492 * Even though CPU supports the cpuid
493 * instruction, it can be disabled.
494 * Therefore, this routine supports all Cyrix
495 * CPUs.
496 */
497 switch (cyrix_did & 0xf0) {
498 case 0x00:
499 switch (cyrix_did & 0x0f) {
500 case 0x00:
501 strcat(cpu_model, "486SLC");
502 break;
503 case 0x01:
504 strcat(cpu_model, "486DLC");
505 break;
506 case 0x02:
507 strcat(cpu_model, "486SLC2");
508 break;
509 case 0x03:
510 strcat(cpu_model, "486DLC2");
511 break;
512 case 0x04:
513 strcat(cpu_model, "486SRx");
514 break;
515 case 0x05:
516 strcat(cpu_model, "486DRx");
517 break;
518 case 0x06:
519 strcat(cpu_model, "486SRx2");
520 break;
521 case 0x07:
522 strcat(cpu_model, "486DRx2");
523 break;
524 case 0x08:
525 strcat(cpu_model, "486SRu");
526 break;
527 case 0x09:
528 strcat(cpu_model, "486DRu");
529 break;
530 case 0x0a:
531 strcat(cpu_model, "486SRu2");
532 break;
533 case 0x0b:
534 strcat(cpu_model, "486DRu2");
535 break;
536 default:
537 strcat(cpu_model, "Unknown");
538 break;
539 }
540 break;
541 case 0x10:
542 switch (cyrix_did & 0x0f) {
543 case 0x00:
544 strcat(cpu_model, "486S");
545 break;
546 case 0x01:
547 strcat(cpu_model, "486S2");
548 break;
549 case 0x02:
550 strcat(cpu_model, "486Se");
551 break;
552 case 0x03:
553 strcat(cpu_model, "486S2e");
554 break;
555 case 0x0a:
556 strcat(cpu_model, "486DX");
557 break;
558 case 0x0b:
559 strcat(cpu_model, "486DX2");
560 break;
561 case 0x0f:
562 strcat(cpu_model, "486DX4");
563 break;
564 default:
565 strcat(cpu_model, "Unknown");
566 break;
567 }
568 break;
569 case 0x20:
570 if ((cyrix_did & 0x0f) < 8)
571 strcat(cpu_model, "6x86"); /* Where did you get it? */
572 else
573 strcat(cpu_model, "5x86");
574 break;
575 case 0x30:
576 strcat(cpu_model, "6x86");
577 break;
578 case 0x40:
579 if ((cyrix_did & 0xf000) == 0x3000) {
580 cpu_class = CPUCLASS_586;
581 strcat(cpu_model, "GXm");
582 } else
583 strcat(cpu_model, "MediaGX");
584 break;
585 case 0x50:
586 strcat(cpu_model, "6x86MX");
587 break;
588 case 0xf0:
589 switch (cyrix_did & 0x0f) {
590 case 0x0d:
591 strcat(cpu_model, "Overdrive CPU");
592 break;
593 case 0x0e:
594 strcpy(cpu_model, "Texas Instruments 486SXL");
595 break;
596 case 0x0f:
597 strcat(cpu_model, "486SLC/DLC");
598 break;
599 default:
600 strcat(cpu_model, "Unknown");
601 break;
602 }
603 break;
604 default:
605 strcat(cpu_model, "Unknown");
606 break;
607 }
608 break;
609 }
610 break;
611 case CPU_VENDOR_RISE:
612 strcpy(cpu_model, "Rise ");
613 switch (cpu_id & 0xff0) {
614 case 0x500: /* 6401 and 6441 (Kirin) */
615 case 0x520: /* 6510 (Lynx) */
616 strcat(cpu_model, "mP6");
617 break;
618 default:
619 strcat(cpu_model, "Unknown");
620 }
621 break;
622 #endif
623 case CPU_VENDOR_CENTAUR:
624 #ifdef __i386__
625 switch (cpu_id & 0xff0) {
626 case 0x540:
627 strcpy(cpu_model, "IDT WinChip C6");
628 break;
629 case 0x580:
630 strcpy(cpu_model, "IDT WinChip 2");
631 break;
632 case 0x590:
633 strcpy(cpu_model, "IDT WinChip 3");
634 break;
635 case 0x660:
636 strcpy(cpu_model, "VIA C3 Samuel");
637 break;
638 case 0x670:
639 if (cpu_id & 0x8)
640 strcpy(cpu_model, "VIA C3 Ezra");
641 else
642 strcpy(cpu_model, "VIA C3 Samuel 2");
643 break;
644 case 0x680:
645 strcpy(cpu_model, "VIA C3 Ezra-T");
646 break;
647 case 0x690:
648 strcpy(cpu_model, "VIA C3 Nehemiah");
649 break;
650 case 0x6a0:
651 case 0x6d0:
652 strcpy(cpu_model, "VIA C7 Esther");
653 break;
654 case 0x6f0:
655 strcpy(cpu_model, "VIA Nano");
656 break;
657 default:
658 strcpy(cpu_model, "VIA/IDT Unknown");
659 }
660 #else
661 strcpy(cpu_model, "VIA ");
662 if ((cpu_id & 0xff0) == 0x6f0)
663 strcat(cpu_model, "Nano Processor");
664 else
665 strcat(cpu_model, "Unknown");
666 #endif
667 break;
668 #ifdef __i386__
669 case CPU_VENDOR_IBM:
670 strcpy(cpu_model, "Blue Lightning CPU");
671 break;
672 case CPU_VENDOR_NSC:
673 switch (cpu_id & 0xff0) {
674 case 0x540:
675 strcpy(cpu_model, "Geode SC1100");
676 cpu = CPU_GEODE1100;
677 break;
678 default:
679 strcpy(cpu_model, "Geode/NSC unknown");
680 break;
681 }
682 break;
683 #endif
684 case CPU_VENDOR_HYGON:
685 strcpy(cpu_model, "Hygon ");
686 #ifdef __i386__
687 strcat(cpu_model, "Unknown");
688 #else
689 if ((cpu_id & 0xf00) == 0xf00)
690 strcat(cpu_model, "AMD64 Processor");
691 else
692 strcat(cpu_model, "Unknown");
693 #endif
694 break;
695
696 default:
697 strcat(cpu_model, "Unknown");
698 break;
699 }
700
701 /*
702 * Replace cpu_model with cpu_brand minus leading spaces if
703 * we have one.
704 */
705 brand = cpu_brand;
706 while (*brand == ' ')
707 ++brand;
708 if (*brand != '\0')
709 strcpy(cpu_model, brand);
710
711 printf("%s (", cpu_model);
712 if (tsc_freq != 0) {
713 hw_clockrate = (tsc_freq + 5000) / 1000000;
714 printf("%jd.%02d-MHz ",
715 (intmax_t)(tsc_freq + 4999) / 1000000,
716 (u_int)((tsc_freq + 4999) / 10000) % 100);
717 }
718 #ifdef __i386__
719 switch(cpu_class) {
720 case CPUCLASS_286:
721 printf("286");
722 break;
723 case CPUCLASS_386:
724 printf("386");
725 break;
726 #if defined(I486_CPU)
727 case CPUCLASS_486:
728 printf("486");
729 break;
730 #endif
731 #if defined(I586_CPU)
732 case CPUCLASS_586:
733 printf("586");
734 break;
735 #endif
736 #if defined(I686_CPU)
737 case CPUCLASS_686:
738 printf("686");
739 break;
740 #endif
741 default:
742 printf("Unknown"); /* will panic below... */
743 }
744 #else
745 printf("K8");
746 #endif
747 printf("-class CPU)\n");
748 if (*cpu_vendor)
749 printf(" Origin=\"%s\"", cpu_vendor);
750 if (cpu_id)
751 printf(" Id=0x%x", cpu_id);
752
753 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
754 cpu_vendor_id == CPU_VENDOR_AMD ||
755 cpu_vendor_id == CPU_VENDOR_HYGON ||
756 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
757 #ifdef __i386__
758 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
759 cpu_vendor_id == CPU_VENDOR_RISE ||
760 cpu_vendor_id == CPU_VENDOR_NSC ||
761 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
762 #endif
763 0) {
764 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
765 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
766 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
767 #ifdef __i386__
768 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
769 printf("\n DIR=0x%04x", cyrix_did);
770 #endif
771
772 /*
773 * AMD CPUID Specification
774 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
775 *
776 * Intel Processor Identification and CPUID Instruction
777 * http://www.intel.com/assets/pdf/appnote/241618.pdf
778 */
779 if (cpu_high > 0) {
780 /*
781 * Here we should probably set up flags indicating
782 * whether or not various features are available.
783 * The interesting ones are probably VME, PSE, PAE,
784 * and PGE. The code already assumes without bothering
785 * to check that all CPUs >= Pentium have a TSC and
786 * MSRs.
787 */
788 printf("\n Features=0x%b", cpu_feature,
789 "\020"
790 "\001FPU" /* Integral FPU */
791 "\002VME" /* Extended VM86 mode support */
792 "\003DE" /* Debugging Extensions (CR4.DE) */
793 "\004PSE" /* 4MByte page tables */
794 "\005TSC" /* Timestamp counter */
795 "\006MSR" /* Machine specific registers */
796 "\007PAE" /* Physical address extension */
797 "\010MCE" /* Machine Check support */
798 "\011CX8" /* CMPEXCH8 instruction */
799 "\012APIC" /* SMP local APIC */
800 "\013oldMTRR" /* Previous implementation of MTRR */
801 "\014SEP" /* Fast System Call */
802 "\015MTRR" /* Memory Type Range Registers */
803 "\016PGE" /* PG_G (global bit) support */
804 "\017MCA" /* Machine Check Architecture */
805 "\020CMOV" /* CMOV instruction */
806 "\021PAT" /* Page attributes table */
807 "\022PSE36" /* 36 bit address space support */
808 "\023PN" /* Processor Serial number */
809 "\024CLFLUSH" /* Has the CLFLUSH instruction */
810 "\025<b20>"
811 "\026DTS" /* Debug Trace Store */
812 "\027ACPI" /* ACPI support */
813 "\030MMX" /* MMX instructions */
814 "\031FXSR" /* FXSAVE/FXRSTOR */
815 "\032SSE" /* Streaming SIMD Extensions */
816 "\033SSE2" /* Streaming SIMD Extensions #2 */
817 "\034SS" /* Self snoop */
818 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
819 "\036TM" /* Thermal Monitor clock slowdown */
820 "\037IA64" /* CPU can execute IA64 instructions */
821 "\040PBE" /* Pending Break Enable */
822 );
823
824 if (cpu_feature2 != 0) {
825 printf("\n Features2=0x%b", cpu_feature2,
826 "\020"
827 "\001SSE3" /* SSE3 */
828 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
829 "\003DTES64" /* 64-bit Debug Trace */
830 "\004MON" /* MONITOR/MWAIT Instructions */
831 "\005DS_CPL" /* CPL Qualified Debug Store */
832 "\006VMX" /* Virtual Machine Extensions */
833 "\007SMX" /* Safer Mode Extensions */
834 "\010EST" /* Enhanced SpeedStep */
835 "\011TM2" /* Thermal Monitor 2 */
836 "\012SSSE3" /* SSSE3 */
837 "\013CNXT-ID" /* L1 context ID available */
838 "\014SDBG" /* IA32 silicon debug */
839 "\015FMA" /* Fused Multiply Add */
840 "\016CX16" /* CMPXCHG16B Instruction */
841 "\017xTPR" /* Send Task Priority Messages*/
842 "\020PDCM" /* Perf/Debug Capability MSR */
843 "\021<b16>"
844 "\022PCID" /* Process-context Identifiers*/
845 "\023DCA" /* Direct Cache Access */
846 "\024SSE4.1" /* SSE 4.1 */
847 "\025SSE4.2" /* SSE 4.2 */
848 "\026x2APIC" /* xAPIC Extensions */
849 "\027MOVBE" /* MOVBE Instruction */
850 "\030POPCNT" /* POPCNT Instruction */
851 "\031TSCDLT" /* TSC-Deadline Timer */
852 "\032AESNI" /* AES Crypto */
853 "\033XSAVE" /* XSAVE/XRSTOR States */
854 "\034OSXSAVE" /* OS-Enabled State Management*/
855 "\035AVX" /* Advanced Vector Extensions */
856 "\036F16C" /* Half-precision conversions */
857 "\037RDRAND" /* RDRAND Instruction */
858 "\040HV" /* Hypervisor */
859 );
860 }
861
862 if (amd_feature != 0) {
863 printf("\n AMD Features=0x%b", amd_feature,
864 "\020" /* in hex */
865 "\001<s0>" /* Same */
866 "\002<s1>" /* Same */
867 "\003<s2>" /* Same */
868 "\004<s3>" /* Same */
869 "\005<s4>" /* Same */
870 "\006<s5>" /* Same */
871 "\007<s6>" /* Same */
872 "\010<s7>" /* Same */
873 "\011<s8>" /* Same */
874 "\012<s9>" /* Same */
875 "\013<b10>" /* Undefined */
876 "\014SYSCALL" /* Have SYSCALL/SYSRET */
877 "\015<s12>" /* Same */
878 "\016<s13>" /* Same */
879 "\017<s14>" /* Same */
880 "\020<s15>" /* Same */
881 "\021<s16>" /* Same */
882 "\022<s17>" /* Same */
883 "\023<b18>" /* Reserved, unknown */
884 "\024MP" /* Multiprocessor Capable */
885 "\025NX" /* Has EFER.NXE, NX */
886 "\026<b21>" /* Undefined */
887 "\027MMX+" /* AMD MMX Extensions */
888 "\030<s23>" /* Same */
889 "\031<s24>" /* Same */
890 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
891 "\033Page1GB" /* 1-GB large page support */
892 "\034RDTSCP" /* RDTSCP */
893 "\035<b28>" /* Undefined */
894 "\036LM" /* 64 bit long mode */
895 "\0373DNow!+" /* AMD 3DNow! Extensions */
896 "\0403DNow!" /* AMD 3DNow! */
897 );
898 }
899
900 if (amd_feature2 != 0) {
901 printf("\n AMD Features2=0x%b", amd_feature2,
902 "\020"
903 "\001LAHF" /* LAHF/SAHF in long mode */
904 "\002CMP" /* CMP legacy */
905 "\003SVM" /* Secure Virtual Mode */
906 "\004ExtAPIC" /* Extended APIC register */
907 "\005CR8" /* CR8 in legacy mode */
908 "\006ABM" /* LZCNT instruction */
909 "\007SSE4A" /* SSE4A */
910 "\010MAS" /* Misaligned SSE mode */
911 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
912 "\012OSVW" /* OS visible workaround */
913 "\013IBS" /* Instruction based sampling */
914 "\014XOP" /* XOP extended instructions */
915 "\015SKINIT" /* SKINIT/STGI */
916 "\016WDT" /* Watchdog timer */
917 "\017<b14>"
918 "\020LWP" /* Lightweight Profiling */
919 "\021FMA4" /* 4-operand FMA instructions */
920 "\022TCE" /* Translation Cache Extension */
921 "\023<b18>"
922 "\024NodeId" /* NodeId MSR support */
923 "\025<b20>"
924 "\026TBM" /* Trailing Bit Manipulation */
925 "\027Topology" /* Topology Extensions */
926 "\030PCXC" /* Core perf count */
927 "\031PNXC" /* NB perf count */
928 "\032<b25>"
929 "\033DBE" /* Data Breakpoint extension */
930 "\034PTSC" /* Performance TSC */
931 "\035PL2I" /* L2I perf count */
932 "\036MWAITX" /* MONITORX/MWAITX instructions */
933 "\037ADMSKX" /* Address mask extension */
934 "\040<b31>"
935 );
936 }
937
938 if (cpu_stdext_feature != 0) {
939 printf("\n Structured Extended Features=0x%b",
940 cpu_stdext_feature,
941 "\020"
942 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
943 "\001FSGSBASE"
944 "\002TSCADJ"
945 "\003SGX"
946 /* Bit Manipulation Instructions */
947 "\004BMI1"
948 /* Hardware Lock Elision */
949 "\005HLE"
950 /* Advanced Vector Instructions 2 */
951 "\006AVX2"
952 /* FDP_EXCPTN_ONLY */
953 "\007FDPEXC"
954 /* Supervisor Mode Execution Prot. */
955 "\010SMEP"
956 /* Bit Manipulation Instructions */
957 "\011BMI2"
958 "\012ERMS"
959 /* Invalidate Processor Context ID */
960 "\013INVPCID"
961 /* Restricted Transactional Memory */
962 "\014RTM"
963 "\015PQM"
964 "\016NFPUSG"
965 /* Intel Memory Protection Extensions */
966 "\017MPX"
967 "\020PQE"
968 /* AVX512 Foundation */
969 "\021AVX512F"
970 "\022AVX512DQ"
971 /* Enhanced NRBG */
972 "\023RDSEED"
973 /* ADCX + ADOX */
974 "\024ADX"
975 /* Supervisor Mode Access Prevention */
976 "\025SMAP"
977 "\026AVX512IFMA"
978 /* Formerly PCOMMIT */
979 "\027<b22>"
980 "\030CLFLUSHOPT"
981 "\031CLWB"
982 "\032PROCTRACE"
983 "\033AVX512PF"
984 "\034AVX512ER"
985 "\035AVX512CD"
986 "\036SHA"
987 "\037AVX512BW"
988 "\040AVX512VL"
989 );
990 }
991
992 if (cpu_stdext_feature2 != 0) {
993 printf("\n Structured Extended Features2=0x%b",
994 cpu_stdext_feature2,
995 "\020"
996 "\001PREFETCHWT1"
997 "\002AVX512VBMI"
998 "\003UMIP"
999 "\004PKU"
1000 "\005OSPKE"
1001 "\006WAITPKG"
1002 "\007AVX512VBMI2"
1003 "\011GFNI"
1004 "\012VAES"
1005 "\013VPCLMULQDQ"
1006 "\014AVX512VNNI"
1007 "\015AVX512BITALG"
1008 "\016TME"
1009 "\017AVX512VPOPCNTDQ"
1010 "\021LA57"
1011 "\027RDPID"
1012 "\032CLDEMOTE"
1013 "\034MOVDIRI"
1014 "\035MOVDIR64B"
1015 "\036ENQCMD"
1016 "\037SGXLC"
1017 );
1018 }
1019
1020 if (cpu_stdext_feature3 != 0) {
1021 printf("\n Structured Extended Features3=0x%b",
1022 cpu_stdext_feature3,
1023 "\020"
1024 "\003AVX512_4VNNIW"
1025 "\004AVX512_4FMAPS"
1026 "\005FSRM"
1027 "\011AVX512VP2INTERSECT"
1028 "\012MCUOPT"
1029 "\013MD_CLEAR"
1030 "\016TSXFA"
1031 "\023PCONFIG"
1032 "\025IBT"
1033 "\033IBPB"
1034 "\034STIBP"
1035 "\035L1DFL"
1036 "\036ARCH_CAP"
1037 "\037CORE_CAP"
1038 "\040SSBD"
1039 );
1040 }
1041
1042 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1043 cpuid_count(0xd, 0x1, regs);
1044 if (regs[0] != 0) {
1045 printf("\n XSAVE Features=0x%b",
1046 regs[0],
1047 "\020"
1048 "\001XSAVEOPT"
1049 "\002XSAVEC"
1050 "\003XINUSE"
1051 "\004XSAVES");
1052 }
1053 }
1054
1055 if (cpu_ia32_arch_caps != 0) {
1056 printf("\n IA32_ARCH_CAPS=0x%b",
1057 (u_int)cpu_ia32_arch_caps,
1058 "\020"
1059 "\001RDCL_NO"
1060 "\002IBRS_ALL"
1061 "\003RSBA"
1062 "\004SKIP_L1DFL_VME"
1063 "\005SSB_NO"
1064 "\006MDS_NO"
1065 "\010TSX_CTRL"
1066 "\011TAA_NO"
1067 );
1068 }
1069
1070 if (amd_extended_feature_extensions != 0) {
1071 u_int amd_fe_masked;
1072
1073 amd_fe_masked = amd_extended_feature_extensions;
1074 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1075 amd_fe_masked &=
1076 ~(AMDFEID_IBRS_ALWAYSON |
1077 AMDFEID_PREFER_IBRS);
1078 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1079 amd_fe_masked &=
1080 ~AMDFEID_STIBP_ALWAYSON;
1081
1082 printf("\n "
1083 "AMD Extended Feature Extensions ID EBX="
1084 "0x%b", amd_fe_masked,
1085 "\020"
1086 "\001CLZERO"
1087 "\002IRPerf"
1088 "\003XSaveErPtr"
1089 "\004INVLPGB"
1090 "\005RDPRU"
1091 "\007BE"
1092 "\011MCOMMIT"
1093 "\012WBNOINVD"
1094 "\015IBPB"
1095 "\016INT_WBINVD"
1096 "\017IBRS"
1097 "\020STIBP"
1098 "\021IBRS_ALWAYSON"
1099 "\022STIBP_ALWAYSON"
1100 "\023PREFER_IBRS"
1101 "\024SAMEMODE_IBRS"
1102 "\025NOLMSLE"
1103 "\026INVLPGBNEST"
1104 "\030PPIN"
1105 "\031SSBD"
1106 "\032VIRT_SSBD"
1107 "\033SSB_NO"
1108 "\034CPPC"
1109 "\035PSFD"
1110 "\036BTC_NO"
1111 "\037IBPB_RET"
1112 );
1113 }
1114
1115 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1116 print_via_padlock_info();
1117
1118 if (cpu_feature2 & CPUID2_VMX)
1119 print_vmx_info();
1120
1121 if (amd_feature2 & AMDID2_SVM)
1122 print_svm_info();
1123
1124 if ((cpu_feature & CPUID_HTT) &&
1125 (cpu_vendor_id == CPU_VENDOR_AMD ||
1126 cpu_vendor_id == CPU_VENDOR_HYGON))
1127 cpu_feature &= ~CPUID_HTT;
1128
1129 /*
1130 * If this CPU supports P-state invariant TSC then
1131 * mention the capability.
1132 */
1133 if (tsc_is_invariant) {
1134 printf("\n TSC: P-state invariant");
1135 if (tsc_perf_stat)
1136 printf(", performance statistics");
1137 }
1138 }
1139 #ifdef __i386__
1140 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1141 printf(" DIR=0x%04x", cyrix_did);
1142 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1143 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1144 #ifndef CYRIX_CACHE_REALLY_WORKS
1145 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1146 printf("\n CPU cache: write-through mode");
1147 #endif
1148 #endif
1149 }
1150
1151 /* Avoid ugly blank lines: only print newline when we have to. */
1152 if (*cpu_vendor || cpu_id)
1153 printf("\n");
1154
1155 if (bootverbose) {
1156 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1157 cpu_vendor_id == CPU_VENDOR_HYGON)
1158 print_AMD_info();
1159 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1160 print_INTEL_info();
1161 #ifdef __i386__
1162 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1163 print_transmeta_info();
1164 #endif
1165 }
1166
1167 print_hypervisor_info();
1168 }
1169
1170 #ifdef __i386__
1171 void
panicifcpuunsupported(void)1172 panicifcpuunsupported(void)
1173 {
1174
1175 #if !defined(lint)
1176 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1177 #error This kernel is not configured for one of the supported CPUs
1178 #endif
1179 #else /* lint */
1180 #endif /* lint */
1181 /*
1182 * Now that we have told the user what they have,
1183 * let them know if that machine type isn't configured.
1184 */
1185 switch (cpu_class) {
1186 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1187 case CPUCLASS_386:
1188 #if !defined(I486_CPU)
1189 case CPUCLASS_486:
1190 #endif
1191 #if !defined(I586_CPU)
1192 case CPUCLASS_586:
1193 #endif
1194 #if !defined(I686_CPU)
1195 case CPUCLASS_686:
1196 #endif
1197 panic("CPU class not configured");
1198 default:
1199 break;
1200 }
1201 }
1202
1203 static volatile u_int trap_by_rdmsr;
1204
1205 /*
1206 * Special exception 6 handler.
1207 * The rdmsr instruction generates invalid opcodes fault on 486-class
1208 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1209 * function identblue() when this handler is called. Stacked eip should
1210 * be advanced.
1211 */
1212 inthand_t bluetrap6;
1213 __asm
1214 (" \n\
1215 .text \n\
1216 .p2align 2,0x90 \n\
1217 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1218 " __XSTRING(CNAME(bluetrap6)) ": \n\
1219 ss \n\
1220 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1221 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1222 iret \n\
1223 ");
1224
1225 /*
1226 * Special exception 13 handler.
1227 * Accessing non-existent MSR generates general protection fault.
1228 */
1229 inthand_t bluetrap13;
1230 __asm
1231 (" \n\
1232 .text \n\
1233 .p2align 2,0x90 \n\
1234 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1235 " __XSTRING(CNAME(bluetrap13)) ": \n\
1236 ss \n\
1237 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1238 popl %eax /* discard error code */ \n\
1239 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1240 iret \n\
1241 ");
1242
1243 /*
1244 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1245 * support cpuid instruction. This function should be called after
1246 * loading interrupt descriptor table register.
1247 *
1248 * I don't like this method that handles fault, but I couldn't get
1249 * information for any other methods. Does blue giant know?
1250 */
1251 static int
identblue(void)1252 identblue(void)
1253 {
1254
1255 trap_by_rdmsr = 0;
1256
1257 /*
1258 * Cyrix 486-class CPU does not support rdmsr instruction.
1259 * The rdmsr instruction generates invalid opcode fault, and exception
1260 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1261 * bluetrap6() set the magic number to trap_by_rdmsr.
1262 */
1263 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1264 GSEL(GCODE_SEL, SEL_KPL));
1265
1266 /*
1267 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1268 * In this case, rdmsr generates general protection fault, and
1269 * exception will be trapped by bluetrap13().
1270 */
1271 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1272 GSEL(GCODE_SEL, SEL_KPL));
1273
1274 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1275
1276 if (trap_by_rdmsr == 0xa8c1d)
1277 return IDENTBLUE_CYRIX486;
1278 else if (trap_by_rdmsr == 0xa89c4)
1279 return IDENTBLUE_CYRIXM2;
1280 return IDENTBLUE_IBMCPU;
1281 }
1282
1283 /*
1284 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1285 *
1286 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1287 * +-------+-------+---------------+
1288 * | SID | RID | Device ID |
1289 * | (DIR 1) | (DIR 0) |
1290 * +-------+-------+---------------+
1291 */
1292 static void
identifycyrix(void)1293 identifycyrix(void)
1294 {
1295 register_t saveintr;
1296 int ccr2_test = 0, dir_test = 0;
1297 u_char ccr2, ccr3;
1298
1299 saveintr = intr_disable();
1300
1301 ccr2 = read_cyrix_reg(CCR2);
1302 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1303 read_cyrix_reg(CCR2);
1304 if (read_cyrix_reg(CCR2) != ccr2)
1305 ccr2_test = 1;
1306 write_cyrix_reg(CCR2, ccr2);
1307
1308 ccr3 = read_cyrix_reg(CCR3);
1309 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1310 read_cyrix_reg(CCR3);
1311 if (read_cyrix_reg(CCR3) != ccr3)
1312 dir_test = 1; /* CPU supports DIRs. */
1313 write_cyrix_reg(CCR3, ccr3);
1314
1315 if (dir_test) {
1316 /* Device ID registers are available. */
1317 cyrix_did = read_cyrix_reg(DIR1) << 8;
1318 cyrix_did += read_cyrix_reg(DIR0);
1319 } else if (ccr2_test)
1320 cyrix_did = 0x0010; /* 486S A-step */
1321 else
1322 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1323
1324 intr_restore(saveintr);
1325 }
1326 #endif
1327
1328 /* Update TSC freq with the value indicated by the caller. */
1329 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1330 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1331 {
1332
1333 /* If there was an error during the transition, don't do anything. */
1334 if (status != 0)
1335 return;
1336
1337 /* Total setting for this level gives the new frequency in MHz. */
1338 hw_clockrate = level->total_set.freq;
1339 }
1340
1341 static void
hook_tsc_freq(void * arg __unused)1342 hook_tsc_freq(void *arg __unused)
1343 {
1344
1345 if (tsc_is_invariant)
1346 return;
1347
1348 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1349 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1350 }
1351
1352 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1353
1354 static struct {
1355 const char *vm_cpuid;
1356 int vm_guest;
1357 } vm_cpuids[] = {
1358 { "XenVMMXenVMM", VM_GUEST_XEN }, /* XEN */
1359 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1360 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1361 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1362 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1363 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1364 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */
1365 };
1366
1367 static void
identify_hypervisor_cpuid_base(void)1368 identify_hypervisor_cpuid_base(void)
1369 {
1370 u_int leaf, regs[4];
1371 int i;
1372
1373 /*
1374 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1375 * http://lkml.org/lkml/2008/10/1/246
1376 *
1377 * KB1009458: Mechanisms to determine if software is running in
1378 * a VMware virtual machine
1379 * http://kb.vmware.com/kb/1009458
1380 *
1381 * Search for a hypervisor that we recognize. If we cannot find
1382 * a specific hypervisor, return the first information about the
1383 * hypervisor that we found, as others may be able to use.
1384 */
1385 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1386 do_cpuid(leaf, regs);
1387
1388 /*
1389 * KVM from Linux kernels prior to commit
1390 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1391 * to 0 rather than a valid hv_high value. Check for
1392 * the KVM signature bytes and fixup %eax to the
1393 * highest supported leaf in that case.
1394 */
1395 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1396 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1397 regs[0] = leaf + 1;
1398
1399 if (regs[0] >= leaf) {
1400 for (i = 0; i < nitems(vm_cpuids); i++)
1401 if (strncmp((const char *)®s[1],
1402 vm_cpuids[i].vm_cpuid, 12) == 0) {
1403 vm_guest = vm_cpuids[i].vm_guest;
1404 break;
1405 }
1406
1407 /*
1408 * If this is the first entry or we found a
1409 * specific hypervisor, record the base, high value,
1410 * and vendor identifier.
1411 */
1412 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1413 hv_base = leaf;
1414 hv_high = regs[0];
1415 ((u_int *)&hv_vendor)[0] = regs[1];
1416 ((u_int *)&hv_vendor)[1] = regs[2];
1417 ((u_int *)&hv_vendor)[2] = regs[3];
1418 hv_vendor[12] = '\0';
1419
1420 /*
1421 * If we found a specific hypervisor, then
1422 * we are finished.
1423 */
1424 if (vm_guest != VM_GUEST_VM)
1425 return;
1426 }
1427 }
1428 }
1429 }
1430
1431 void
identify_hypervisor(void)1432 identify_hypervisor(void)
1433 {
1434 u_int regs[4];
1435 char *p;
1436
1437 TSENTER();
1438 /*
1439 * If CPUID2_HV is set, we are running in a hypervisor environment.
1440 */
1441 if (cpu_feature2 & CPUID2_HV) {
1442 vm_guest = VM_GUEST_VM;
1443 identify_hypervisor_cpuid_base();
1444
1445 /* If we have a definitive vendor, we can return now. */
1446 if (*hv_vendor != '\0') {
1447 TSEXIT();
1448 return;
1449 }
1450 }
1451
1452 /*
1453 * Examine SMBIOS strings for older hypervisors.
1454 */
1455 p = kern_getenv("smbios.system.serial");
1456 if (p != NULL) {
1457 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1458 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1459 if (regs[1] == VMW_HVMAGIC) {
1460 vm_guest = VM_GUEST_VMWARE;
1461 freeenv(p);
1462 TSEXIT();
1463 return;
1464 }
1465 }
1466 freeenv(p);
1467 }
1468 TSEXIT();
1469 }
1470
1471 bool
fix_cpuid(void)1472 fix_cpuid(void)
1473 {
1474 uint64_t msr;
1475
1476 /*
1477 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1478 * get the largest standard CPUID function number again if it is set
1479 * from BIOS. It is necessary for probing correct CPU topology later
1480 * and for the correct operation of the AVX-aware userspace.
1481 */
1482 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1483 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1484 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1485 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1486 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1487 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1488 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1489 msr &= ~IA32_MISC_EN_LIMCPUID;
1490 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1491 return (true);
1492 }
1493 }
1494
1495 /*
1496 * Re-enable AMD Topology Extension that could be disabled by BIOS
1497 * on some notebook processors. Without the extension it's really
1498 * hard to determine the correct CPU cache topology.
1499 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1500 * Models 60h-6Fh Processors, Publication # 50742.
1501 */
1502 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1503 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1504 msr = rdmsr(MSR_EXTFEATURES);
1505 if ((msr & ((uint64_t)1 << 54)) == 0) {
1506 msr |= (uint64_t)1 << 54;
1507 wrmsr(MSR_EXTFEATURES, msr);
1508 return (true);
1509 }
1510 }
1511 return (false);
1512 }
1513
1514 void
identify_cpu1(void)1515 identify_cpu1(void)
1516 {
1517 u_int regs[4];
1518
1519 do_cpuid(0, regs);
1520 cpu_high = regs[0];
1521 ((u_int *)&cpu_vendor)[0] = regs[1];
1522 ((u_int *)&cpu_vendor)[1] = regs[3];
1523 ((u_int *)&cpu_vendor)[2] = regs[2];
1524 cpu_vendor[12] = '\0';
1525
1526 do_cpuid(1, regs);
1527 cpu_id = regs[0];
1528 cpu_procinfo = regs[1];
1529 cpu_feature = regs[3];
1530 cpu_feature2 = regs[2];
1531 }
1532
1533 void
identify_cpu2(void)1534 identify_cpu2(void)
1535 {
1536 u_int regs[4], cpu_stdext_disable;
1537
1538 if (cpu_high >= 6) {
1539 cpuid_count(6, 0, regs);
1540 cpu_power_eax = regs[0];
1541 cpu_power_ebx = regs[1];
1542 cpu_power_ecx = regs[2];
1543 cpu_power_edx = regs[3];
1544 }
1545
1546 if (cpu_high >= 7) {
1547 cpuid_count(7, 0, regs);
1548 cpu_stdext_feature = regs[1];
1549
1550 /*
1551 * Some hypervisors failed to filter out unsupported
1552 * extended features. Allow to disable the
1553 * extensions, activation of which requires setting a
1554 * bit in CR4, and which VM monitors do not support.
1555 */
1556 cpu_stdext_disable = 0;
1557 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1558 cpu_stdext_feature &= ~cpu_stdext_disable;
1559
1560 cpu_stdext_feature2 = regs[2];
1561 cpu_stdext_feature3 = regs[3];
1562
1563 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1564 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1565 }
1566 }
1567
1568 void
identify_cpu_ext_features(void)1569 identify_cpu_ext_features(void)
1570 {
1571 u_int regs[4];
1572
1573 if (cpu_high >= 7) {
1574 cpuid_count(7, 0, regs);
1575 cpu_stdext_feature2 = regs[2];
1576 cpu_stdext_feature3 = regs[3];
1577 }
1578 }
1579
1580 void
identify_cpu_fixup_bsp(void)1581 identify_cpu_fixup_bsp(void)
1582 {
1583 u_int regs[4];
1584
1585 cpu_vendor_id = find_cpu_vendor_id();
1586
1587 if (fix_cpuid()) {
1588 do_cpuid(0, regs);
1589 cpu_high = regs[0];
1590 }
1591 }
1592
1593 /*
1594 * Final stage of CPU identification.
1595 */
1596 void
finishidentcpu(void)1597 finishidentcpu(void)
1598 {
1599 u_int regs[4];
1600 #ifdef __i386__
1601 u_char ccr3;
1602 #endif
1603
1604 identify_cpu_fixup_bsp();
1605
1606 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1607 do_cpuid(5, regs);
1608 cpu_mon_mwait_flags = regs[2];
1609 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1610 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1611 }
1612
1613 identify_cpu2();
1614
1615 #ifdef __i386__
1616 if (cpu_high > 0 &&
1617 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1618 cpu_vendor_id == CPU_VENDOR_AMD ||
1619 cpu_vendor_id == CPU_VENDOR_HYGON ||
1620 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1621 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1622 cpu_vendor_id == CPU_VENDOR_NSC)) {
1623 do_cpuid(0x80000000, regs);
1624 if (regs[0] >= 0x80000000)
1625 cpu_exthigh = regs[0];
1626 }
1627 #else
1628 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1629 cpu_vendor_id == CPU_VENDOR_AMD ||
1630 cpu_vendor_id == CPU_VENDOR_HYGON ||
1631 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1632 do_cpuid(0x80000000, regs);
1633 cpu_exthigh = regs[0];
1634 }
1635 #endif
1636 if (cpu_exthigh >= 0x80000001) {
1637 do_cpuid(0x80000001, regs);
1638 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1639 amd_feature2 = regs[2];
1640 }
1641 if (cpu_exthigh >= 0x80000007) {
1642 do_cpuid(0x80000007, regs);
1643 amd_rascap = regs[1];
1644 amd_pminfo = regs[3];
1645 }
1646 if (cpu_exthigh >= 0x80000008) {
1647 do_cpuid(0x80000008, regs);
1648 cpu_maxphyaddr = regs[0] & 0xff;
1649 amd_extended_feature_extensions = regs[1];
1650 cpu_procinfo2 = regs[2];
1651 cpu_procinfo3 = regs[3];
1652 } else {
1653 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1654 }
1655
1656 #ifdef __i386__
1657 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1658 if (cpu == CPU_486) {
1659 /*
1660 * These conditions are equivalent to:
1661 * - CPU does not support cpuid instruction.
1662 * - Cyrix/IBM CPU is detected.
1663 */
1664 if (identblue() == IDENTBLUE_IBMCPU) {
1665 strcpy(cpu_vendor, "IBM");
1666 cpu_vendor_id = CPU_VENDOR_IBM;
1667 cpu = CPU_BLUE;
1668 return;
1669 }
1670 }
1671 switch (cpu_id & 0xf00) {
1672 case 0x600:
1673 /*
1674 * Cyrix's datasheet does not describe DIRs.
1675 * Therefor, I assume it does not have them
1676 * and use the result of the cpuid instruction.
1677 * XXX they seem to have it for now at least. -Peter
1678 */
1679 identifycyrix();
1680 cpu = CPU_M2;
1681 break;
1682 default:
1683 identifycyrix();
1684 /*
1685 * This routine contains a trick.
1686 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1687 */
1688 switch (cyrix_did & 0x00f0) {
1689 case 0x00:
1690 case 0xf0:
1691 cpu = CPU_486DLC;
1692 break;
1693 case 0x10:
1694 cpu = CPU_CY486DX;
1695 break;
1696 case 0x20:
1697 if ((cyrix_did & 0x000f) < 8)
1698 cpu = CPU_M1;
1699 else
1700 cpu = CPU_M1SC;
1701 break;
1702 case 0x30:
1703 cpu = CPU_M1;
1704 break;
1705 case 0x40:
1706 /* MediaGX CPU */
1707 cpu = CPU_M1SC;
1708 break;
1709 default:
1710 /* M2 and later CPUs are treated as M2. */
1711 cpu = CPU_M2;
1712
1713 /*
1714 * enable cpuid instruction.
1715 */
1716 ccr3 = read_cyrix_reg(CCR3);
1717 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1718 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1719 write_cyrix_reg(CCR3, ccr3);
1720
1721 do_cpuid(0, regs);
1722 cpu_high = regs[0]; /* eax */
1723 do_cpuid(1, regs);
1724 cpu_id = regs[0]; /* eax */
1725 cpu_feature = regs[3]; /* edx */
1726 break;
1727 }
1728 }
1729 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1730 /*
1731 * There are BlueLightning CPUs that do not change
1732 * undefined flags by dividing 5 by 2. In this case,
1733 * the CPU identification routine in locore.s leaves
1734 * cpu_vendor null string and puts CPU_486 into the
1735 * cpu.
1736 */
1737 if (identblue() == IDENTBLUE_IBMCPU) {
1738 strcpy(cpu_vendor, "IBM");
1739 cpu_vendor_id = CPU_VENDOR_IBM;
1740 cpu = CPU_BLUE;
1741 return;
1742 }
1743 }
1744 #endif
1745 }
1746
1747 int
pti_get_default(void)1748 pti_get_default(void)
1749 {
1750
1751 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1752 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1753 return (0);
1754 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1755 return (0);
1756 return (1);
1757 }
1758
1759 static u_int
find_cpu_vendor_id(void)1760 find_cpu_vendor_id(void)
1761 {
1762 int i;
1763
1764 for (i = 0; i < nitems(cpu_vendors); i++)
1765 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1766 return (cpu_vendors[i].vendor_id);
1767 return (0);
1768 }
1769
1770 static void
print_AMD_assoc(int i)1771 print_AMD_assoc(int i)
1772 {
1773 if (i == 255)
1774 printf(", fully associative\n");
1775 else
1776 printf(", %d-way associative\n", i);
1777 }
1778
1779 static void
print_AMD_l2_assoc(int i)1780 print_AMD_l2_assoc(int i)
1781 {
1782 switch (i & 0x0f) {
1783 case 0: printf(", disabled/not present\n"); break;
1784 case 1: printf(", direct mapped\n"); break;
1785 case 2: printf(", 2-way associative\n"); break;
1786 case 4: printf(", 4-way associative\n"); break;
1787 case 6: printf(", 8-way associative\n"); break;
1788 case 8: printf(", 16-way associative\n"); break;
1789 case 15: printf(", fully associative\n"); break;
1790 default: printf(", reserved configuration\n"); break;
1791 }
1792 }
1793
1794 static void
print_AMD_info(void)1795 print_AMD_info(void)
1796 {
1797 #ifdef __i386__
1798 uint64_t amd_whcr;
1799 #endif
1800 u_int regs[4];
1801
1802 if (cpu_exthigh >= 0x80000005) {
1803 do_cpuid(0x80000005, regs);
1804 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1805 print_AMD_assoc(regs[0] >> 24);
1806
1807 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1808 print_AMD_assoc((regs[0] >> 8) & 0xff);
1809
1810 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1811 print_AMD_assoc(regs[1] >> 24);
1812
1813 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1814 print_AMD_assoc((regs[1] >> 8) & 0xff);
1815
1816 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1817 printf(", %d bytes/line", regs[2] & 0xff);
1818 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1819 print_AMD_assoc((regs[2] >> 16) & 0xff);
1820
1821 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1822 printf(", %d bytes/line", regs[3] & 0xff);
1823 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1824 print_AMD_assoc((regs[3] >> 16) & 0xff);
1825 }
1826
1827 if (cpu_exthigh >= 0x80000006) {
1828 do_cpuid(0x80000006, regs);
1829 if ((regs[0] >> 16) != 0) {
1830 printf("L2 2MB data TLB: %d entries",
1831 (regs[0] >> 16) & 0xfff);
1832 print_AMD_l2_assoc(regs[0] >> 28);
1833 printf("L2 2MB instruction TLB: %d entries",
1834 regs[0] & 0xfff);
1835 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1836 } else {
1837 printf("L2 2MB unified TLB: %d entries",
1838 regs[0] & 0xfff);
1839 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1840 }
1841 if ((regs[1] >> 16) != 0) {
1842 printf("L2 4KB data TLB: %d entries",
1843 (regs[1] >> 16) & 0xfff);
1844 print_AMD_l2_assoc(regs[1] >> 28);
1845
1846 printf("L2 4KB instruction TLB: %d entries",
1847 (regs[1] >> 16) & 0xfff);
1848 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1849 } else {
1850 printf("L2 4KB unified TLB: %d entries",
1851 (regs[1] >> 16) & 0xfff);
1852 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1853 }
1854 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1855 printf(", %d bytes/line", regs[2] & 0xff);
1856 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1857 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1858 }
1859
1860 #ifdef __i386__
1861 if (((cpu_id & 0xf00) == 0x500)
1862 && (((cpu_id & 0x0f0) > 0x80)
1863 || (((cpu_id & 0x0f0) == 0x80)
1864 && (cpu_id & 0x00f) > 0x07))) {
1865 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1866 amd_whcr = rdmsr(0xc0000082);
1867 if (!(amd_whcr & (0x3ff << 22))) {
1868 printf("Write Allocate Disable\n");
1869 } else {
1870 printf("Write Allocate Enable Limit: %dM bytes\n",
1871 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1872 printf("Write Allocate 15-16M bytes: %s\n",
1873 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1874 }
1875 } else if (((cpu_id & 0xf00) == 0x500)
1876 && ((cpu_id & 0x0f0) > 0x50)) {
1877 /* K6, K6-2(old core) */
1878 amd_whcr = rdmsr(0xc0000082);
1879 if (!(amd_whcr & (0x7f << 1))) {
1880 printf("Write Allocate Disable\n");
1881 } else {
1882 printf("Write Allocate Enable Limit: %dM bytes\n",
1883 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1884 printf("Write Allocate 15-16M bytes: %s\n",
1885 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1886 printf("Hardware Write Allocate Control: %s\n",
1887 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1888 }
1889 }
1890 #endif
1891 /*
1892 * Opteron Rev E shows a bug as in very rare occasions a read memory
1893 * barrier is not performed as expected if it is followed by a
1894 * non-atomic read-modify-write instruction.
1895 * As long as that bug pops up very rarely (intensive machine usage
1896 * on other operating systems generally generates one unexplainable
1897 * crash any 2 months) and as long as a model specific fix would be
1898 * impractical at this stage, print out a warning string if the broken
1899 * model and family are identified.
1900 */
1901 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1902 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1903 printf("WARNING: This architecture revision has known SMP "
1904 "hardware bugs which may cause random instability\n");
1905 }
1906
1907 static void
print_INTEL_info(void)1908 print_INTEL_info(void)
1909 {
1910 u_int regs[4];
1911 u_int rounds, regnum;
1912 u_int nwaycode, nway;
1913
1914 if (cpu_high >= 2) {
1915 rounds = 0;
1916 do {
1917 do_cpuid(0x2, regs);
1918 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1919 break; /* we have a buggy CPU */
1920
1921 for (regnum = 0; regnum <= 3; ++regnum) {
1922 if (regs[regnum] & (1<<31))
1923 continue;
1924 if (regnum != 0)
1925 print_INTEL_TLB(regs[regnum] & 0xff);
1926 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1927 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1928 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1929 }
1930 } while (--rounds > 0);
1931 }
1932
1933 if (cpu_exthigh >= 0x80000006) {
1934 do_cpuid(0x80000006, regs);
1935 nwaycode = (regs[2] >> 12) & 0x0f;
1936 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1937 nway = 1 << (nwaycode / 2);
1938 else
1939 nway = 0;
1940 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1941 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1942 }
1943 }
1944
1945 static void
print_INTEL_TLB(u_int data)1946 print_INTEL_TLB(u_int data)
1947 {
1948 switch (data) {
1949 case 0x0:
1950 case 0x40:
1951 default:
1952 break;
1953 case 0x1:
1954 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1955 break;
1956 case 0x2:
1957 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1958 break;
1959 case 0x3:
1960 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1961 break;
1962 case 0x4:
1963 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1964 break;
1965 case 0x6:
1966 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1967 break;
1968 case 0x8:
1969 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1970 break;
1971 case 0x9:
1972 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1973 break;
1974 case 0xa:
1975 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1976 break;
1977 case 0xb:
1978 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1979 break;
1980 case 0xc:
1981 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1982 break;
1983 case 0xd:
1984 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1985 break;
1986 case 0xe:
1987 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1988 break;
1989 case 0x1d:
1990 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1991 break;
1992 case 0x21:
1993 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1994 break;
1995 case 0x22:
1996 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1997 break;
1998 case 0x23:
1999 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2000 break;
2001 case 0x24:
2002 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2003 break;
2004 case 0x25:
2005 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2006 break;
2007 case 0x29:
2008 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2009 break;
2010 case 0x2c:
2011 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2012 break;
2013 case 0x30:
2014 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2015 break;
2016 case 0x39: /* De-listed in SDM rev. 54 */
2017 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2018 break;
2019 case 0x3b: /* De-listed in SDM rev. 54 */
2020 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2021 break;
2022 case 0x3c: /* De-listed in SDM rev. 54 */
2023 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2024 break;
2025 case 0x41:
2026 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2027 break;
2028 case 0x42:
2029 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2030 break;
2031 case 0x43:
2032 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2033 break;
2034 case 0x44:
2035 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2036 break;
2037 case 0x45:
2038 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2039 break;
2040 case 0x46:
2041 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2042 break;
2043 case 0x47:
2044 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2045 break;
2046 case 0x48:
2047 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2048 break;
2049 case 0x49:
2050 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2051 CPUID_TO_MODEL(cpu_id) == 0x6)
2052 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2053 else
2054 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2055 break;
2056 case 0x4a:
2057 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2058 break;
2059 case 0x4b:
2060 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2061 break;
2062 case 0x4c:
2063 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2064 break;
2065 case 0x4d:
2066 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2067 break;
2068 case 0x4e:
2069 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2070 break;
2071 case 0x4f:
2072 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2073 break;
2074 case 0x50:
2075 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2076 break;
2077 case 0x51:
2078 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2079 break;
2080 case 0x52:
2081 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2082 break;
2083 case 0x55:
2084 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2085 break;
2086 case 0x56:
2087 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2088 break;
2089 case 0x57:
2090 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2091 break;
2092 case 0x59:
2093 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2094 break;
2095 case 0x5a:
2096 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2097 break;
2098 case 0x5b:
2099 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2100 break;
2101 case 0x5c:
2102 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2103 break;
2104 case 0x5d:
2105 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2106 break;
2107 case 0x60:
2108 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2109 break;
2110 case 0x61:
2111 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2112 break;
2113 case 0x63:
2114 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2115 break;
2116 case 0x64:
2117 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2118 break;
2119 case 0x66:
2120 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2121 break;
2122 case 0x67:
2123 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2124 break;
2125 case 0x68:
2126 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2127 break;
2128 case 0x6a:
2129 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2130 break;
2131 case 0x6b:
2132 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2133 break;
2134 case 0x6c:
2135 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2136 break;
2137 case 0x6d:
2138 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2139 break;
2140 case 0x70:
2141 printf("Trace cache: 12K-uops, 8-way set associative\n");
2142 break;
2143 case 0x71:
2144 printf("Trace cache: 16K-uops, 8-way set associative\n");
2145 break;
2146 case 0x72:
2147 printf("Trace cache: 32K-uops, 8-way set associative\n");
2148 break;
2149 case 0x76:
2150 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2151 break;
2152 case 0x78:
2153 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2154 break;
2155 case 0x79:
2156 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2157 break;
2158 case 0x7a:
2159 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2160 break;
2161 case 0x7b:
2162 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2163 break;
2164 case 0x7c:
2165 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2166 break;
2167 case 0x7d:
2168 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2169 break;
2170 case 0x7f:
2171 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2172 break;
2173 case 0x80:
2174 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2175 break;
2176 case 0x82:
2177 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2178 break;
2179 case 0x83:
2180 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2181 break;
2182 case 0x84:
2183 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2184 break;
2185 case 0x85:
2186 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2187 break;
2188 case 0x86:
2189 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2190 break;
2191 case 0x87:
2192 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2193 break;
2194 case 0xa0:
2195 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2196 break;
2197 case 0xb0:
2198 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2199 break;
2200 case 0xb1:
2201 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2202 break;
2203 case 0xb2:
2204 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2205 break;
2206 case 0xb3:
2207 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2208 break;
2209 case 0xb4:
2210 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2211 break;
2212 case 0xb5:
2213 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2214 break;
2215 case 0xb6:
2216 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2217 break;
2218 case 0xba:
2219 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2220 break;
2221 case 0xc0:
2222 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2223 break;
2224 case 0xc1:
2225 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2226 break;
2227 case 0xc2:
2228 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2229 break;
2230 case 0xc3:
2231 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2232 break;
2233 case 0xc4:
2234 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2235 break;
2236 case 0xca:
2237 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2238 break;
2239 case 0xd0:
2240 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2241 break;
2242 case 0xd1:
2243 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2244 break;
2245 case 0xd2:
2246 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2247 break;
2248 case 0xd6:
2249 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2250 break;
2251 case 0xd7:
2252 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2253 break;
2254 case 0xd8:
2255 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2256 break;
2257 case 0xdc:
2258 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2259 break;
2260 case 0xdd:
2261 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2262 break;
2263 case 0xde:
2264 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2265 break;
2266 case 0xe2:
2267 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2268 break;
2269 case 0xe3:
2270 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2271 break;
2272 case 0xe4:
2273 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2274 break;
2275 case 0xea:
2276 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2277 break;
2278 case 0xeb:
2279 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2280 break;
2281 case 0xec:
2282 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2283 break;
2284 case 0xf0:
2285 printf("64-Byte prefetching\n");
2286 break;
2287 case 0xf1:
2288 printf("128-Byte prefetching\n");
2289 break;
2290 }
2291 }
2292
2293 static void
print_svm_info(void)2294 print_svm_info(void)
2295 {
2296 u_int features, regs[4];
2297 uint64_t msr;
2298 int comma;
2299
2300 printf("\n SVM: ");
2301 do_cpuid(0x8000000A, regs);
2302 features = regs[3];
2303
2304 msr = rdmsr(MSR_VM_CR);
2305 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2306 printf("(disabled in BIOS) ");
2307
2308 if (!bootverbose) {
2309 comma = 0;
2310 if (features & (1 << 0)) {
2311 printf("%sNP", comma ? "," : "");
2312 comma = 1;
2313 }
2314 if (features & (1 << 3)) {
2315 printf("%sNRIP", comma ? "," : "");
2316 comma = 1;
2317 }
2318 if (features & (1 << 5)) {
2319 printf("%sVClean", comma ? "," : "");
2320 comma = 1;
2321 }
2322 if (features & (1 << 6)) {
2323 printf("%sAFlush", comma ? "," : "");
2324 comma = 1;
2325 }
2326 if (features & (1 << 7)) {
2327 printf("%sDAssist", comma ? "," : "");
2328 comma = 1;
2329 }
2330 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2331 return;
2332 }
2333
2334 printf("Features=0x%b", features,
2335 "\020"
2336 "\001NP" /* Nested paging */
2337 "\002LbrVirt" /* LBR virtualization */
2338 "\003SVML" /* SVM lock */
2339 "\004NRIPS" /* NRIP save */
2340 "\005TscRateMsr" /* MSR based TSC rate control */
2341 "\006VmcbClean" /* VMCB clean bits */
2342 "\007FlushByAsid" /* Flush by ASID */
2343 "\010DecodeAssist" /* Decode assist */
2344 "\011<b8>"
2345 "\012<b9>"
2346 "\013PauseFilter" /* PAUSE intercept filter */
2347 "\014EncryptedMcodePatch"
2348 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2349 "\016AVIC" /* virtual interrupt controller */
2350 "\017<b14>"
2351 "\020V_VMSAVE_VMLOAD"
2352 "\021vGIF"
2353 "\022GMET" /* Guest Mode Execute Trap */
2354 "\023<b18>"
2355 "\024<b19>"
2356 "\025GuesSpecCtl" /* Guest Spec_ctl */
2357 "\026<b21>"
2358 "\027<b22>"
2359 "\030<b23>"
2360 "\031<b24>"
2361 "\032<b25>"
2362 "\033<b26>"
2363 "\034<b27>"
2364 "\035<b28>"
2365 "\036<b29>"
2366 "\037<b30>"
2367 "\040<b31>"
2368 );
2369 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2370 }
2371
2372 #ifdef __i386__
2373 static void
print_transmeta_info(void)2374 print_transmeta_info(void)
2375 {
2376 u_int regs[4], nreg = 0;
2377
2378 do_cpuid(0x80860000, regs);
2379 nreg = regs[0];
2380 if (nreg >= 0x80860001) {
2381 do_cpuid(0x80860001, regs);
2382 printf(" Processor revision %u.%u.%u.%u\n",
2383 (regs[1] >> 24) & 0xff,
2384 (regs[1] >> 16) & 0xff,
2385 (regs[1] >> 8) & 0xff,
2386 regs[1] & 0xff);
2387 }
2388 if (nreg >= 0x80860002) {
2389 do_cpuid(0x80860002, regs);
2390 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2391 (regs[1] >> 24) & 0xff,
2392 (regs[1] >> 16) & 0xff,
2393 (regs[1] >> 8) & 0xff,
2394 regs[1] & 0xff,
2395 regs[2]);
2396 }
2397 if (nreg >= 0x80860006) {
2398 char info[65];
2399 do_cpuid(0x80860003, (u_int*) &info[0]);
2400 do_cpuid(0x80860004, (u_int*) &info[16]);
2401 do_cpuid(0x80860005, (u_int*) &info[32]);
2402 do_cpuid(0x80860006, (u_int*) &info[48]);
2403 info[64] = 0;
2404 printf(" %s\n", info);
2405 }
2406 }
2407 #endif
2408
2409 static void
print_via_padlock_info(void)2410 print_via_padlock_info(void)
2411 {
2412 u_int regs[4];
2413
2414 do_cpuid(0xc0000001, regs);
2415 printf("\n VIA Padlock Features=0x%b", regs[3],
2416 "\020"
2417 "\003RNG" /* RNG */
2418 "\007AES" /* ACE */
2419 "\011AES-CTR" /* ACE2 */
2420 "\013SHA1,SHA256" /* PHE */
2421 "\015RSA" /* PMM */
2422 );
2423 }
2424
2425 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2426 vmx_settable(uint64_t basic, int msr, int true_msr)
2427 {
2428 uint64_t val;
2429
2430 if (basic & (1ULL << 55))
2431 val = rdmsr(true_msr);
2432 else
2433 val = rdmsr(msr);
2434
2435 /* Just report the controls that can be set to 1. */
2436 return (val >> 32);
2437 }
2438
2439 static void
print_vmx_info(void)2440 print_vmx_info(void)
2441 {
2442 uint64_t basic, msr;
2443 uint32_t entry, exit, mask, pin, proc, proc2;
2444 int comma;
2445
2446 printf("\n VT-x: ");
2447 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2448 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2449 printf("(disabled in BIOS) ");
2450 basic = rdmsr(MSR_VMX_BASIC);
2451 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2452 MSR_VMX_TRUE_PINBASED_CTLS);
2453 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2454 MSR_VMX_TRUE_PROCBASED_CTLS);
2455 if (proc & PROCBASED_SECONDARY_CONTROLS)
2456 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2457 MSR_VMX_PROCBASED_CTLS2);
2458 else
2459 proc2 = 0;
2460 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2461 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2462
2463 if (!bootverbose) {
2464 comma = 0;
2465 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2466 entry & VM_ENTRY_LOAD_PAT) {
2467 printf("%sPAT", comma ? "," : "");
2468 comma = 1;
2469 }
2470 if (proc & PROCBASED_HLT_EXITING) {
2471 printf("%sHLT", comma ? "," : "");
2472 comma = 1;
2473 }
2474 if (proc & PROCBASED_MTF) {
2475 printf("%sMTF", comma ? "," : "");
2476 comma = 1;
2477 }
2478 if (proc & PROCBASED_PAUSE_EXITING) {
2479 printf("%sPAUSE", comma ? "," : "");
2480 comma = 1;
2481 }
2482 if (proc2 & PROCBASED2_ENABLE_EPT) {
2483 printf("%sEPT", comma ? "," : "");
2484 comma = 1;
2485 }
2486 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2487 printf("%sUG", comma ? "," : "");
2488 comma = 1;
2489 }
2490 if (proc2 & PROCBASED2_ENABLE_VPID) {
2491 printf("%sVPID", comma ? "," : "");
2492 comma = 1;
2493 }
2494 if (proc & PROCBASED_USE_TPR_SHADOW &&
2495 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2496 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2497 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2498 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2499 printf("%sVID", comma ? "," : "");
2500 comma = 1;
2501 if (pin & PINBASED_POSTED_INTERRUPT)
2502 printf(",PostIntr");
2503 }
2504 return;
2505 }
2506
2507 mask = basic >> 32;
2508 printf("Basic Features=0x%b", mask,
2509 "\020"
2510 "\02132PA" /* 32-bit physical addresses */
2511 "\022SMM" /* SMM dual-monitor */
2512 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2513 "\030TRUE" /* TRUE_CTLS MSRs */
2514 );
2515 printf("\n Pin-Based Controls=0x%b", pin,
2516 "\020"
2517 "\001ExtINT" /* External-interrupt exiting */
2518 "\004NMI" /* NMI exiting */
2519 "\006VNMI" /* Virtual NMIs */
2520 "\007PreTmr" /* Activate VMX-preemption timer */
2521 "\010PostIntr" /* Process posted interrupts */
2522 );
2523 printf("\n Primary Processor Controls=0x%b", proc,
2524 "\020"
2525 "\003INTWIN" /* Interrupt-window exiting */
2526 "\004TSCOff" /* Use TSC offsetting */
2527 "\010HLT" /* HLT exiting */
2528 "\012INVLPG" /* INVLPG exiting */
2529 "\013MWAIT" /* MWAIT exiting */
2530 "\014RDPMC" /* RDPMC exiting */
2531 "\015RDTSC" /* RDTSC exiting */
2532 "\020CR3-LD" /* CR3-load exiting */
2533 "\021CR3-ST" /* CR3-store exiting */
2534 "\024CR8-LD" /* CR8-load exiting */
2535 "\025CR8-ST" /* CR8-store exiting */
2536 "\026TPR" /* Use TPR shadow */
2537 "\027NMIWIN" /* NMI-window exiting */
2538 "\030MOV-DR" /* MOV-DR exiting */
2539 "\031IO" /* Unconditional I/O exiting */
2540 "\032IOmap" /* Use I/O bitmaps */
2541 "\034MTF" /* Monitor trap flag */
2542 "\035MSRmap" /* Use MSR bitmaps */
2543 "\036MONITOR" /* MONITOR exiting */
2544 "\037PAUSE" /* PAUSE exiting */
2545 );
2546 if (proc & PROCBASED_SECONDARY_CONTROLS)
2547 printf("\n Secondary Processor Controls=0x%b", proc2,
2548 "\020"
2549 "\001APIC" /* Virtualize APIC accesses */
2550 "\002EPT" /* Enable EPT */
2551 "\003DT" /* Descriptor-table exiting */
2552 "\004RDTSCP" /* Enable RDTSCP */
2553 "\005x2APIC" /* Virtualize x2APIC mode */
2554 "\006VPID" /* Enable VPID */
2555 "\007WBINVD" /* WBINVD exiting */
2556 "\010UG" /* Unrestricted guest */
2557 "\011APIC-reg" /* APIC-register virtualization */
2558 "\012VID" /* Virtual-interrupt delivery */
2559 "\013PAUSE-loop" /* PAUSE-loop exiting */
2560 "\014RDRAND" /* RDRAND exiting */
2561 "\015INVPCID" /* Enable INVPCID */
2562 "\016VMFUNC" /* Enable VM functions */
2563 "\017VMCS" /* VMCS shadowing */
2564 "\020EPT#VE" /* EPT-violation #VE */
2565 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2566 );
2567 printf("\n Exit Controls=0x%b", mask,
2568 "\020"
2569 "\003DR" /* Save debug controls */
2570 /* Ignore Host address-space size */
2571 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2572 "\020AckInt" /* Acknowledge interrupt on exit */
2573 "\023PAT-SV" /* Save MSR_PAT */
2574 "\024PAT-LD" /* Load MSR_PAT */
2575 "\025EFER-SV" /* Save MSR_EFER */
2576 "\026EFER-LD" /* Load MSR_EFER */
2577 "\027PTMR-SV" /* Save VMX-preemption timer value */
2578 );
2579 printf("\n Entry Controls=0x%b", mask,
2580 "\020"
2581 "\003DR" /* Save debug controls */
2582 /* Ignore IA-32e mode guest */
2583 /* Ignore Entry to SMM */
2584 /* Ignore Deactivate dual-monitor treatment */
2585 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2586 "\017PAT" /* Load MSR_PAT */
2587 "\020EFER" /* Load MSR_EFER */
2588 );
2589 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2590 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2591 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2592 mask = msr;
2593 printf("\n EPT Features=0x%b", mask,
2594 "\020"
2595 "\001XO" /* Execute-only translations */
2596 "\007PW4" /* Page-walk length of 4 */
2597 "\011UC" /* EPT paging-structure mem can be UC */
2598 "\017WB" /* EPT paging-structure mem can be WB */
2599 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2600 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2601 "\025INVEPT" /* INVEPT is supported */
2602 "\026AD" /* Accessed and dirty flags for EPT */
2603 "\032single" /* INVEPT single-context type */
2604 "\033all" /* INVEPT all-context type */
2605 );
2606 mask = msr >> 32;
2607 printf("\n VPID Features=0x%b", mask,
2608 "\020"
2609 "\001INVVPID" /* INVVPID is supported */
2610 "\011individual" /* INVVPID individual-address type */
2611 "\012single" /* INVVPID single-context type */
2612 "\013all" /* INVVPID all-context type */
2613 /* INVVPID single-context-retaining-globals type */
2614 "\014single-globals"
2615 );
2616 }
2617 }
2618
2619 static void
print_hypervisor_info(void)2620 print_hypervisor_info(void)
2621 {
2622
2623 if (*hv_vendor != '\0')
2624 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2625 }
2626
2627 /*
2628 * Returns the maximum physical address that can be used with the
2629 * current system.
2630 */
2631 vm_paddr_t
cpu_getmaxphyaddr(void)2632 cpu_getmaxphyaddr(void)
2633 {
2634
2635 #if defined(__i386__)
2636 if (!pae_mode)
2637 return (0xffffffff);
2638 #endif
2639 return ((1ULL << cpu_maxphyaddr) - 1);
2640 }
2641