xref: /f-stack/freebsd/mips/mips/intr_machdep.c (revision 22ce4aff)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2006 Oleksandr Tymoshenko
5  * Copyright (c) 2002-2004 Juli Mallett <[email protected]>
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions, and the following disclaimer,
13  *    without modification, immediately at the beginning of the file.
14  * 2. The name of the author may not be used to endorse or promote products
15  *    derived from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 #include "opt_hwpmc_hooks.h"
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/interrupt.h>
40 #include <sys/pmc.h>
41 #include <sys/pmckern.h>
42 
43 #include <machine/clock.h>
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/cpuinfo.h>
47 #include <machine/cpuregs.h>
48 #include <machine/frame.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 
53 #ifndef INTRNG
54 #define INTRCNT_COUNT	256
55 #define	INTRNAME_LEN	(2*MAXCOMLEN + 1)
56 
57 MALLOC_DECLARE(M_MIPSINTR);
58 MALLOC_DEFINE(M_MIPSINTR, "mipsintr", "MIPS interrupt handling");
59 
60 u_long *intrcnt;
61 char *intrnames;
62 size_t sintrcnt;
63 size_t sintrnames;
64 #endif
65 
66 static struct intr_event *hardintr_events[NHARD_IRQS];
67 static struct intr_event *softintr_events[NSOFT_IRQS];
68 static mips_intrcnt_t mips_intr_counters[NSOFT_IRQS + NHARD_IRQS];
69 
70 static int intrcnt_index;
71 
72 static cpu_intr_mask_t		hardintr_mask_func;
73 static cpu_intr_unmask_t	hardintr_unmask_func;
74 
75 mips_intrcnt_t
mips_intrcnt_create(const char * name)76 mips_intrcnt_create(const char* name)
77 {
78 	mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
79 
80 	mips_intrcnt_setname(counter, name);
81 	return counter;
82 }
83 
84 void
mips_intrcnt_setname(mips_intrcnt_t counter,const char * name)85 mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
86 {
87 	int idx = counter - intrcnt;
88 
89 	KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
90 
91 	snprintf(intrnames + (MAXCOMLEN + 1) * idx,
92 	    MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
93 }
94 
95 static void
mips_mask_hard_irq(void * source)96 mips_mask_hard_irq(void *source)
97 {
98 	uintptr_t irq = (uintptr_t)source;
99 
100 	mips_wr_status(mips_rd_status() & ~(((1 << irq) << 8) << 2));
101 }
102 
103 static void
mips_unmask_hard_irq(void * source)104 mips_unmask_hard_irq(void *source)
105 {
106 	uintptr_t irq = (uintptr_t)source;
107 
108 	mips_wr_status(mips_rd_status() | (((1 << irq) << 8) << 2));
109 }
110 
111 static void
mips_mask_soft_irq(void * source)112 mips_mask_soft_irq(void *source)
113 {
114 	uintptr_t irq = (uintptr_t)source;
115 
116 	mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
117 }
118 
119 static void
mips_unmask_soft_irq(void * source)120 mips_unmask_soft_irq(void *source)
121 {
122 	uintptr_t irq = (uintptr_t)source;
123 
124 	mips_wr_status(mips_rd_status() | ((1 << irq) << 8));
125 }
126 
127 /*
128  * Perform initialization of interrupts prior to setting
129  * handlings
130  */
131 void
cpu_init_interrupts()132 cpu_init_interrupts()
133 {
134 	int i;
135 	char name[MAXCOMLEN + 1];
136 
137 #ifndef INTRNG
138 	intrcnt = mallocarray(INTRCNT_COUNT, sizeof(u_long), M_MIPSINTR,
139 	    M_WAITOK | M_ZERO);
140 	intrnames = mallocarray(INTRCNT_COUNT, INTRNAME_LEN, M_MIPSINTR,
141 	    M_WAITOK | M_ZERO);
142 	sintrcnt = INTRCNT_COUNT * sizeof(u_long);
143 	sintrnames = INTRCNT_COUNT * INTRNAME_LEN;
144 #endif
145 
146 	/*
147 	 * Initialize all available vectors so spare IRQ
148 	 * would show up in systat output
149 	 */
150 	for (i = 0; i < NSOFT_IRQS; i++) {
151 		snprintf(name, MAXCOMLEN + 1, "sint%d:", i);
152 		mips_intr_counters[i] = mips_intrcnt_create(name);
153 	}
154 
155 	for (i = 0; i < NHARD_IRQS; i++) {
156 		snprintf(name, MAXCOMLEN + 1, "int%d:", i);
157 		mips_intr_counters[NSOFT_IRQS + i] = mips_intrcnt_create(name);
158 	}
159 }
160 
161 void
cpu_set_hardintr_mask_func(cpu_intr_mask_t func)162 cpu_set_hardintr_mask_func(cpu_intr_mask_t func)
163 {
164 
165 	hardintr_mask_func = func;
166 }
167 
168 void
cpu_set_hardintr_unmask_func(cpu_intr_unmask_t func)169 cpu_set_hardintr_unmask_func(cpu_intr_unmask_t func)
170 {
171 
172 	hardintr_unmask_func = func;
173 }
174 
175 void
cpu_establish_hardintr(const char * name,driver_filter_t * filt,void (* handler)(void *),void * arg,int irq,int flags,void ** cookiep)176 cpu_establish_hardintr(const char *name, driver_filter_t *filt,
177     void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
178 {
179 	struct intr_event *event;
180 	int error;
181 
182 	/*
183 	 * We have 6 levels, but thats 0 - 5 (not including 6)
184 	 */
185 	if (irq < 0 || irq >= NHARD_IRQS)
186 		panic("%s called for unknown hard intr %d", __func__, irq);
187 
188 	if (hardintr_mask_func == NULL)
189 		hardintr_mask_func = mips_mask_hard_irq;
190 
191 	if (hardintr_unmask_func == NULL)
192 		hardintr_unmask_func = mips_unmask_hard_irq;
193 
194 	event = hardintr_events[irq];
195 	if (event == NULL) {
196 		error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
197 		    irq, hardintr_mask_func, hardintr_unmask_func,
198 		    NULL, NULL, "int%d", irq);
199 		if (error)
200 			return;
201 		hardintr_events[irq] = event;
202 		mips_unmask_hard_irq((void*)(uintptr_t)irq);
203 	}
204 
205 	intr_event_add_handler(event, name, filt, handler, arg,
206 	    intr_priority(flags), flags, cookiep);
207 
208 	mips_intrcnt_setname(mips_intr_counters[NSOFT_IRQS + irq],
209 			     event->ie_fullname);
210 }
211 
212 void
cpu_establish_softintr(const char * name,driver_filter_t * filt,void (* handler)(void *),void * arg,int irq,int flags,void ** cookiep)213 cpu_establish_softintr(const char *name, driver_filter_t *filt,
214     void (*handler)(void*), void *arg, int irq, int flags,
215     void **cookiep)
216 {
217 	struct intr_event *event;
218 	int error;
219 
220 #if 0
221 	printf("Establish SOFT IRQ %d: filt %p handler %p arg %p\n",
222 	    irq, filt, handler, arg);
223 #endif
224 	if (irq < 0 || irq > NSOFT_IRQS)
225 		panic("%s called for unknown hard intr %d", __func__, irq);
226 
227 	event = softintr_events[irq];
228 	if (event == NULL) {
229 		error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
230 		    irq, mips_mask_soft_irq, mips_unmask_soft_irq,
231 		    NULL, NULL, "sint%d:", irq);
232 		if (error)
233 			return;
234 		softintr_events[irq] = event;
235 		mips_unmask_soft_irq((void*)(uintptr_t)irq);
236 	}
237 
238 	intr_event_add_handler(event, name, filt, handler, arg,
239 	    intr_priority(flags), flags, cookiep);
240 
241 	mips_intrcnt_setname(mips_intr_counters[irq], event->ie_fullname);
242 }
243 
244 void
cpu_intr(struct trapframe * tf)245 cpu_intr(struct trapframe *tf)
246 {
247 	struct intr_event *event;
248 	register_t cause, status;
249 	int hard, i, intr;
250 
251 	critical_enter();
252 
253 	cause = mips_rd_cause();
254 	status = mips_rd_status();
255 	intr = (cause & MIPS_INT_MASK) >> 8;
256 	/*
257 	 * Do not handle masked interrupts. They were masked by
258 	 * pre_ithread function (mips_mask_XXX_intr) and will be
259 	 * unmasked once ithread is through with handler
260 	 */
261 	intr &= (status & MIPS_INT_MASK) >> 8;
262 	while ((i = fls(intr)) != 0) {
263 		intr &= ~(1 << (i - 1));
264 		switch (i) {
265 		case 1: case 2:
266 			/* Software interrupt. */
267 			i--; /* Get a 0-offset interrupt. */
268 			hard = 0;
269 			event = softintr_events[i];
270 			mips_intrcnt_inc(mips_intr_counters[i]);
271 			break;
272 		default:
273 			/* Hardware interrupt. */
274 			i -= 2; /* Trim software interrupt bits. */
275 			i--; /* Get a 0-offset interrupt. */
276 			hard = 1;
277 			event = hardintr_events[i];
278 			mips_intrcnt_inc(mips_intr_counters[NSOFT_IRQS + i]);
279 			break;
280 		}
281 
282 		if (!event || CK_SLIST_EMPTY(&event->ie_handlers)) {
283 			printf("stray %s interrupt %d\n",
284 			    hard ? "hard" : "soft", i);
285 			continue;
286 		}
287 
288 		if (intr_event_handle(event, tf) != 0) {
289 			printf("stray %s interrupt %d\n",
290 			    hard ? "hard" : "soft", i);
291 		}
292 	}
293 
294 	KASSERT(i == 0, ("all interrupts handled"));
295 
296 	critical_exit();
297 
298 #ifdef HWPMC_HOOKS
299 	if (pmc_hook && (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN))
300 		pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf);
301 #endif
302 }
303