1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause
3 *
4 * Copyright (c) 2001 Matt Thomas.
5 * Copyright (c) 2001 Tsubai Masanari.
6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by
20 * Internet Research Institute, Inc.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35 /*-
36 * Copyright (C) 2003 Benno Rice.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
47 *
48 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 *
59 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
60 */
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/bus.h>
65 #include <sys/conf.h>
66 #include <sys/cpu.h>
67 #include <sys/kernel.h>
68 #include <sys/ktr.h>
69 #include <sys/lock.h>
70 #include <sys/proc.h>
71 #include <sys/sysctl.h>
72 #include <sys/sched.h>
73 #include <sys/smp.h>
74 #include <sys/endian.h>
75
76 #include <machine/bus.h>
77 #include <machine/cpu.h>
78 #include <machine/hid.h>
79 #include <machine/md_var.h>
80 #include <machine/smp.h>
81 #include <machine/spr.h>
82
83 #include <dev/ofw/openfirm.h>
84
85 static void cpu_6xx_setup(int cpuid, uint16_t vers);
86 static void cpu_970_setup(int cpuid, uint16_t vers);
87 static void cpu_booke_setup(int cpuid, uint16_t vers);
88 static void cpu_powerx_setup(int cpuid, uint16_t vers);
89
90 int powerpc_pow_enabled;
91 void (*cpu_idle_hook)(sbintime_t) = NULL;
92 static void cpu_idle_60x(sbintime_t);
93 static void cpu_idle_booke(sbintime_t);
94 #ifdef BOOKE_E500
95 static void cpu_idle_e500mc(sbintime_t sbt);
96 #endif
97 #if defined(__powerpc64__) && defined(AIM)
98 static void cpu_idle_powerx(sbintime_t);
99 static void cpu_idle_power9(sbintime_t);
100 #endif
101
102 struct cputab {
103 const char *name;
104 uint16_t version;
105 uint16_t revfmt;
106 int features; /* Do not include PPC_FEATURE_32 or
107 * PPC_FEATURE_HAS_MMU */
108 int features2;
109 void (*cpu_setup)(int cpuid, uint16_t vers);
110 };
111 #define REVFMT_MAJMIN 1 /* %u.%u */
112 #define REVFMT_HEX 2 /* 0x%04x */
113 #define REVFMT_DEC 3 /* %u */
114 static const struct cputab models[] = {
115 { "Motorola PowerPC 601", MPC601, REVFMT_DEC,
116 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup },
117 { "Motorola PowerPC 602", MPC602, REVFMT_DEC,
118 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
119 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN,
120 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
121 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN,
122 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
123 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN,
124 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
125 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN,
126 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
127 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN,
128 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
129 { "Motorola PowerPC 620", MPC620, REVFMT_HEX,
130 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
131 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN,
132 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
133 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN,
134 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
135 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN,
136 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
137 0, cpu_970_setup },
138 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN,
139 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
140 0, cpu_970_setup },
141 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN,
142 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
143 0, cpu_970_setup },
144 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN,
145 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
146 0, cpu_970_setup },
147 { "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN,
148 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
149 { "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN,
150 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
151 { "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN,
152 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4 |
153 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
154 { "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN,
155 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER5_PLUS |
156 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
157 { "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN,
158 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
159 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
160 PPC_FEATURE_TRUE_LE, 0, NULL },
161 { "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN,
162 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
163 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
164 PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, PPC_FEATURE2_DSCR, NULL },
165 { "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN,
166 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
167 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
168 PPC_FEATURE_HAS_VSX, PPC_FEATURE2_DSCR, NULL },
169 { "IBM POWER8E", IBMPOWER8E, REVFMT_MAJMIN,
170 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
171 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
172 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
173 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_DSCR | PPC_FEATURE2_ISEL |
174 PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO, cpu_powerx_setup },
175 { "IBM POWER8NVL", IBMPOWER8NVL, REVFMT_MAJMIN,
176 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
177 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
178 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
179 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_DSCR | PPC_FEATURE2_ISEL |
180 PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO, cpu_powerx_setup },
181 { "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN,
182 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
183 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
184 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
185 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_DSCR | PPC_FEATURE2_ISEL |
186 PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO, cpu_powerx_setup },
187 { "IBM POWER9", IBMPOWER9, REVFMT_MAJMIN,
188 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
189 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
190 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
191 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_DSCR | PPC_FEATURE2_EBB |
192 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
193 PPC_FEATURE2_ARCH_3_00 | PPC_FEATURE2_HAS_IEEE128 |
194 PPC_FEATURE2_DARN, cpu_powerx_setup },
195 { "IBM POWER10", IBMPOWER10, REVFMT_MAJMIN,
196 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
197 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
198 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
199 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_DSCR | PPC_FEATURE2_EBB |
200 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
201 PPC_FEATURE2_ARCH_3_00 | PPC_FEATURE2_HAS_IEEE128 |
202 PPC_FEATURE2_DARN | PPC_FEATURE2_ARCH_3_1 | PPC_FEATURE2_MMA,
203 cpu_powerx_setup },
204 { "IBM POWER11", IBMPOWER11, REVFMT_MAJMIN,
205 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
206 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
207 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
208 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_DSCR | PPC_FEATURE2_EBB |
209 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
210 PPC_FEATURE2_ARCH_3_00 | PPC_FEATURE2_HAS_IEEE128 |
211 PPC_FEATURE2_DARN | PPC_FEATURE2_ARCH_3_1 | PPC_FEATURE2_MMA,
212 cpu_powerx_setup },
213 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN,
214 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
215 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN,
216 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
217 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN,
218 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
219 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN,
220 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
221 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN,
222 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
223 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN,
224 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
225 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN,
226 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
227 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN,
228 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
229 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
230 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
231 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
232 PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_BOOKE,
233 PPC_FEATURE2_ISEL, cpu_booke_setup },
234 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
235 PPC_FEATURE_HAS_SPE | PPC_FEATURE_BOOKE |
236 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
237 PPC_FEATURE2_ISEL, cpu_booke_setup },
238 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
239 PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 |
240 PPC_FEATURE_ARCH_2_06, PPC_FEATURE2_ISEL,
241 cpu_booke_setup },
242 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
243 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE |
244 PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
245 PPC_FEATURE2_ISEL, cpu_booke_setup },
246 { "Freescale e6500 core", FSL_E6500, REVFMT_MAJMIN,
247 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
248 PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
249 PPC_FEATURE2_ISEL, cpu_booke_setup },
250 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN,
251 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
252 PPC_FEATURE_CELL | PPC_FEATURE_SMT, 0, NULL},
253 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, 0, NULL },
254 };
255
256 static void cpu_6xx_print_cacheinfo(u_int, uint16_t);
257 static int cpu_feature_bit(SYSCTL_HANDLER_ARGS);
258
259 static char model[64];
260 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD, model, 0, "");
261
262 static const struct cputab *cput;
263
264 u_long cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
265 u_long cpu_features2 = 0;
266 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
267 &cpu_features, sizeof(cpu_features), "LX", "PowerPC CPU features");
268 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD,
269 &cpu_features2, sizeof(cpu_features2), "LX", "PowerPC CPU features 2");
270
271 #ifdef __powerpc64__
272 register_t lpcr = LPCR_LPES;
273 #endif
274
275 /* Provide some user-friendly aliases for bits in cpu_features */
276 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint,
277 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 0, PPC_FEATURE_HAS_FPU,
278 cpu_feature_bit, "I", "Floating point instructions executed in hardware");
279 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
280 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
281
282 /*
283 * Phase 1 (early) CPU setup. Setup the cpu_features/cpu_features2 variables,
284 * so they can be used during platform and MMU bringup.
285 */
286 void
cpu_feature_setup(void)287 cpu_feature_setup(void)
288 {
289 u_int pvr;
290 uint16_t vers;
291 const struct cputab *cp;
292
293 pvr = mfpvr();
294 vers = pvr >> 16;
295 for (cp = models; cp->version != 0; cp++) {
296 if (cp->version == vers)
297 break;
298 }
299
300 cput = cp;
301 cpu_features |= cp->features;
302 cpu_features2 |= cp->features2;
303 }
304
305 void
cpu_setup(u_int cpuid)306 cpu_setup(u_int cpuid)
307 {
308 uint64_t cps;
309 const char *name;
310 u_int maj, min, pvr;
311 uint16_t rev, revfmt, vers;
312
313 pvr = mfpvr();
314 vers = pvr >> 16;
315 rev = pvr;
316 switch (vers) {
317 case MPC7410:
318 min = (pvr >> 0) & 0xff;
319 maj = min <= 4 ? 1 : 2;
320 break;
321 case FSL_E500v1:
322 case FSL_E500v2:
323 case FSL_E500mc:
324 case FSL_E5500:
325 maj = (pvr >> 4) & 0xf;
326 min = (pvr >> 0) & 0xf;
327 break;
328 default:
329 maj = (pvr >> 8) & 0xf;
330 min = (pvr >> 0) & 0xf;
331 }
332
333 revfmt = cput->revfmt;
334 name = cput->name;
335 if (rev == MPC750 && pvr == 15) {
336 name = "Motorola MPC755";
337 revfmt = REVFMT_HEX;
338 }
339 strncpy(model, name, sizeof(model) - 1);
340
341 printf("cpu%d: %s revision ", cpuid, name);
342
343 switch (revfmt) {
344 case REVFMT_MAJMIN:
345 printf("%u.%u", maj, min);
346 break;
347 case REVFMT_HEX:
348 printf("0x%04x", rev);
349 break;
350 case REVFMT_DEC:
351 printf("%u", rev);
352 break;
353 }
354
355 if (cpu_est_clockrate(0, &cps) == 0)
356 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
357 printf("\n");
358
359 printf("cpu%d: Features %b\n", cpuid, (int)cpu_features,
360 PPC_FEATURE_BITMASK);
361 if (cpu_features2 != 0)
362 printf("cpu%d: Features2 %b\n", cpuid, (int)cpu_features2,
363 PPC_FEATURE2_BITMASK);
364
365 /*
366 * Configure CPU
367 */
368 if (cput->cpu_setup != NULL)
369 cput->cpu_setup(cpuid, vers);
370 }
371
372 /* Get current clock frequency for the given cpu id. */
373 int
cpu_est_clockrate(int cpu_id,uint64_t * cps)374 cpu_est_clockrate(int cpu_id, uint64_t *cps)
375 {
376 uint16_t vers;
377 register_t msr;
378 phandle_t cpu, dev, root;
379 uint32_t freq32;
380 int res = 0;
381 char buf[8];
382
383 vers = mfpvr() >> 16;
384 msr = mfmsr();
385 mtmsr(msr & ~PSL_EE);
386
387 switch (vers) {
388 case MPC7450:
389 case MPC7455:
390 case MPC7457:
391 case MPC750:
392 case IBM750FX:
393 case MPC7400:
394 case MPC7410:
395 case MPC7447A:
396 case MPC7448:
397 mtspr(SPR_MMCR0_74XX, SPR_MMCR0_FC);
398 mtspr(SPR_PMC1_74XX, 0);
399 mtspr(SPR_MMCR0_74XX,
400 SPR_MMCR0_74XX_PMC1SEL(PMCN_CYCLES));
401 DELAY(1000);
402 *cps = (mfspr(SPR_PMC1_74XX) * 1000) + 4999;
403 mtspr(SPR_MMCR0_74XX, SPR_MMCR0_FC);
404
405 mtmsr(msr);
406 return (0);
407 case IBM970:
408 case IBM970FX:
409 case IBM970MP:
410 isync();
411 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
412 isync();
413 mtspr(SPR_MMCR1, 0);
414 mtspr(SPR_MMCRA, 0);
415 mtspr(SPR_PMC1, 0);
416 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMC970N_CYCLES));
417 isync();
418 DELAY(1000);
419 powerpc_sync();
420 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
421 *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
422
423 mtmsr(msr);
424 return (0);
425
426 default:
427 root = OF_peer(0);
428 if (root == 0)
429 return (ENXIO);
430
431 dev = OF_child(root);
432 while (dev != 0) {
433 res = OF_getprop(dev, "name", buf, sizeof(buf));
434 if (res > 0 && strcmp(buf, "cpus") == 0)
435 break;
436 dev = OF_peer(dev);
437 }
438 cpu = OF_child(dev);
439 while (cpu != 0) {
440 res = OF_getprop(cpu, "device_type", buf,
441 sizeof(buf));
442 if (res > 0 && strcmp(buf, "cpu") == 0)
443 break;
444 cpu = OF_peer(cpu);
445 }
446 if (cpu == 0)
447 return (ENOENT);
448 if (OF_getprop(cpu, "ibm,extended-clock-frequency",
449 cps, sizeof(*cps)) >= 0) {
450 *cps = be64toh(*cps);
451 return (0);
452 } else if (OF_getencprop(cpu, "clock-frequency",
453 &freq32, sizeof(freq32)) >= 0) {
454 *cps = freq32;
455 return (0);
456 } else {
457 return (ENOENT);
458 }
459 }
460 }
461
462 void
cpu_6xx_setup(int cpuid,uint16_t vers)463 cpu_6xx_setup(int cpuid, uint16_t vers)
464 {
465 register_t hid0, pvr;
466 const char *bitmask;
467
468 hid0 = mfspr(SPR_HID0);
469 pvr = mfpvr();
470
471 /*
472 * Configure power-saving mode.
473 */
474 switch (vers) {
475 case MPC603:
476 case MPC603e:
477 case MPC603ev:
478 case MPC604ev:
479 case MPC750:
480 case IBM750FX:
481 case MPC7400:
482 case MPC7410:
483 case MPC8240:
484 case MPC8245:
485 /* Select DOZE mode. */
486 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
487 hid0 |= HID0_DOZE | HID0_DPM;
488 powerpc_pow_enabled = 1;
489 break;
490
491 case MPC7448:
492 case MPC7447A:
493 case MPC7457:
494 case MPC7455:
495 case MPC7450:
496 /* Enable the 7450 branch caches */
497 hid0 |= HID0_SGE | HID0_BTIC;
498 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
499 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
500 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
501 || (pvr >> 16) == MPC7457)
502 hid0 &= ~HID0_BTIC;
503 /* Select NAP mode. */
504 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
505 hid0 |= HID0_NAP | HID0_DPM;
506 powerpc_pow_enabled = 1;
507 break;
508
509 default:
510 /* No power-saving mode is available. */ ;
511 }
512
513 switch (vers) {
514 case IBM750FX:
515 case MPC750:
516 hid0 &= ~HID0_DBP; /* XXX correct? */
517 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
518 break;
519
520 case MPC7400:
521 case MPC7410:
522 hid0 &= ~HID0_SPD;
523 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
524 hid0 |= HID0_EIEC;
525 break;
526 }
527
528 mtspr(SPR_HID0, hid0);
529
530 if (bootverbose)
531 cpu_6xx_print_cacheinfo(cpuid, vers);
532
533 switch (vers) {
534 case MPC7447A:
535 case MPC7448:
536 case MPC7450:
537 case MPC7455:
538 case MPC7457:
539 bitmask = HID0_7450_BITMASK;
540 break;
541 default:
542 bitmask = HID0_BITMASK;
543 break;
544 }
545
546 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
547
548 if (cpu_idle_hook == NULL)
549 cpu_idle_hook = cpu_idle_60x;
550 }
551
552 static void
cpu_6xx_print_cacheinfo(u_int cpuid,uint16_t vers)553 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
554 {
555 register_t hid;
556
557 hid = mfspr(SPR_HID0);
558 printf("cpu%u: ", cpuid);
559 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
560 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
561
562 printf("cpu%u: ", cpuid);
563 if (mfspr(SPR_L2CR) & L2CR_L2E) {
564 switch (vers) {
565 case MPC7450:
566 case MPC7455:
567 case MPC7457:
568 printf("256KB L2 cache, ");
569 if (mfspr(SPR_L3CR) & L3CR_L3E)
570 printf("%cMB L3 backside cache",
571 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
572 else
573 printf("L3 cache disabled");
574 printf("\n");
575 break;
576 case IBM750FX:
577 printf("512KB L2 cache\n");
578 break;
579 default:
580 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
581 case L2SIZ_256K:
582 printf("256KB ");
583 break;
584 case L2SIZ_512K:
585 printf("512KB ");
586 break;
587 case L2SIZ_1M:
588 printf("1MB ");
589 break;
590 }
591 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
592 ? "through" : "back");
593 if (mfspr(SPR_L2CR) & L2CR_L2PE)
594 printf(", with parity");
595 printf(" backside cache\n");
596 break;
597 }
598 } else
599 printf("L2 cache disabled\n");
600 }
601
602 static void
cpu_booke_setup(int cpuid,uint16_t vers)603 cpu_booke_setup(int cpuid, uint16_t vers)
604 {
605 #ifdef BOOKE_E500
606 register_t hid0;
607 const char *bitmask;
608
609 hid0 = mfspr(SPR_HID0);
610
611 switch (vers) {
612 case FSL_E500mc:
613 bitmask = HID0_E500MC_BITMASK;
614 cpu_idle_hook = cpu_idle_e500mc;
615 break;
616 case FSL_E5500:
617 case FSL_E6500:
618 bitmask = HID0_E5500_BITMASK;
619 cpu_idle_hook = cpu_idle_e500mc;
620 break;
621 case FSL_E500v1:
622 case FSL_E500v2:
623 /* Only e500v1/v2 support HID0 power management setup. */
624
625 /* Program power-management mode. */
626 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
627 hid0 |= HID0_DOZE;
628
629 mtspr(SPR_HID0, hid0);
630 default:
631 bitmask = HID0_E500_BITMASK;
632 break;
633 }
634 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
635 #endif
636
637 if (cpu_idle_hook == NULL)
638 cpu_idle_hook = cpu_idle_booke;
639 }
640
641 static void
cpu_970_setup(int cpuid,uint16_t vers)642 cpu_970_setup(int cpuid, uint16_t vers)
643 {
644 #ifdef AIM
645 uint32_t hid0_hi, hid0_lo;
646
647 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
648 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
649
650 /* Configure power-saving mode */
651 switch (vers) {
652 case IBM970MP:
653 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
654 hid0_hi &= ~HID0_DOZE;
655 break;
656 default:
657 hid0_hi |= (HID0_NAP | HID0_DPM);
658 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
659 break;
660 }
661 powerpc_pow_enabled = 1;
662
663 __asm __volatile (" \
664 sync; isync; \
665 sldi %0,%0,32; or %0,%0,%1; \
666 mtspr %2, %0; \
667 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
668 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
669 sync; isync"
670 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
671
672 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
673 : "=r" (hid0_hi) : "K" (SPR_HID0));
674 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
675 #endif
676
677 cpu_idle_hook = cpu_idle_60x;
678 }
679
680 static void
cpu_powerx_setup(int cpuid,uint16_t vers)681 cpu_powerx_setup(int cpuid, uint16_t vers)
682 {
683
684 #if defined(__powerpc64__) && defined(AIM)
685 if ((mfmsr() & PSL_HV) == 0)
686 return;
687
688 /* Nuke the FSCR, to disable all facilities. */
689 mtspr(SPR_FSCR, 0);
690
691 /* Configure power-saving */
692 switch (vers) {
693 case IBMPOWER8:
694 case IBMPOWER8E:
695 case IBMPOWER8NVL:
696 cpu_idle_hook = cpu_idle_powerx;
697 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
698 isync();
699 break;
700 case IBMPOWER9:
701 cpu_idle_hook = cpu_idle_power9;
702 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
703 isync();
704 break;
705 default:
706 return;
707 }
708
709 #endif
710 }
711
712 static int
cpu_feature_bit(SYSCTL_HANDLER_ARGS)713 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
714 {
715 int result;
716
717 result = (cpu_features & arg2) ? 1 : 0;
718
719 return (sysctl_handle_int(oidp, &result, 0, req));
720 }
721
722 void
cpu_idle(int busy)723 cpu_idle(int busy)
724 {
725 sbintime_t sbt = -1;
726
727 #ifdef INVARIANTS
728 if ((mfmsr() & PSL_EE) != PSL_EE) {
729 struct thread *td = curthread;
730 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
731 panic("ints disabled in idleproc!");
732 }
733 #endif
734
735 CTR1(KTR_SPARE2, "cpu_idle(%d)", busy);
736
737 if (cpu_idle_hook != NULL) {
738 if (!busy) {
739 critical_enter();
740 sbt = cpu_idleclock();
741 }
742 cpu_idle_hook(sbt);
743 if (!busy) {
744 cpu_activeclock();
745 critical_exit();
746 }
747 }
748
749 CTR1(KTR_SPARE2, "cpu_idle(%d) done", busy);
750 }
751
752 static void
cpu_idle_60x(sbintime_t sbt)753 cpu_idle_60x(sbintime_t sbt)
754 {
755 #ifdef AIM
756 register_t msr;
757 uint16_t vers;
758 #endif
759
760 if (!powerpc_pow_enabled)
761 return;
762
763 #ifdef AIM
764 msr = mfmsr();
765 vers = mfpvr() >> 16;
766
767 switch (vers) {
768 case IBM970:
769 case IBM970FX:
770 case IBM970MP:
771 case MPC7447A:
772 case MPC7448:
773 case MPC7450:
774 case MPC7455:
775 case MPC7457:
776 /* 0x7e00066c: dssall */
777 __asm __volatile("\
778 .long 0x7e00066c; sync; mtmsr %0; isync"
779 :: "r"(msr | PSL_POW));
780 break;
781 default:
782 powerpc_sync();
783 mtmsr(msr | PSL_POW);
784 break;
785 }
786 #endif
787 }
788
789 #ifdef BOOKE_E500
790 static void
cpu_idle_e500mc(sbintime_t sbt)791 cpu_idle_e500mc(sbintime_t sbt)
792 {
793 /*
794 * Base binutils doesn't know what the 'wait' instruction is, so
795 * use the opcode encoding here.
796 */
797 __asm __volatile(".long 0x7c00007c");
798 }
799 #endif
800
801 static void
cpu_idle_booke(sbintime_t sbt)802 cpu_idle_booke(sbintime_t sbt)
803 {
804 #ifdef BOOKE_E500
805 register_t msr;
806
807 msr = mfmsr();
808
809 powerpc_sync();
810 mtmsr(msr | PSL_WE);
811 #endif
812 }
813
814 #if defined(__powerpc64__) && defined(AIM)
815 static void
cpu_idle_powerx(sbintime_t sbt)816 cpu_idle_powerx(sbintime_t sbt)
817 {
818 /* Sleeping when running on one cpu gives no advantages - avoid it */
819 if (smp_started == 0)
820 return;
821
822 spinlock_enter();
823 if (sched_runnable()) {
824 spinlock_exit();
825 return;
826 }
827
828 if (can_wakeup == 0)
829 can_wakeup = 1;
830 mb();
831
832 enter_idle_powerx();
833 spinlock_exit();
834 }
835
836 static void
cpu_idle_power9(sbintime_t sbt)837 cpu_idle_power9(sbintime_t sbt)
838 {
839 register_t msr;
840
841 msr = mfmsr();
842
843 /* Suspend external interrupts until stop instruction completes. */
844 mtmsr(msr & ~PSL_EE);
845 /* Set the stop state to lowest latency, wake up to next instruction */
846 /* Set maximum transition level to 2, for deepest lossless sleep. */
847 mtspr(SPR_PSSCR, (2 << PSSCR_MTL_S) | (0 << PSSCR_RL_S));
848 /* "stop" instruction (PowerISA 3.0) */
849 __asm __volatile (".long 0x4c0002e4");
850 /*
851 * Re-enable external interrupts to capture the interrupt that caused
852 * the wake up.
853 */
854 mtmsr(msr);
855
856 }
857 #endif
858
859 int
cpu_idle_wakeup(int cpu)860 cpu_idle_wakeup(int cpu)
861 {
862
863 return (0);
864 }
865