1 /*
2  * \file       trc_cmp_cfg_etmv4.h
3  * \brief      OpenCSD :
4  *
5  * \copyright  Copyright (c) 2015, ARM Limited. All Rights Reserved.
6  */
7 
8 
9 /*
10  * Redistribution and use in source and binary forms, with or without modification,
11  * are permitted provided that the following conditions are met:
12  *
13  * 1. Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  *
16  * 2. Redistributions in binary form must reproduce the above copyright notice,
17  * this list of conditions and the following disclaimer in the documentation
18  * and/or other materials provided with the distribution.
19  *
20  * 3. Neither the name of the copyright holder nor the names of its contributors
21  * may be used to endorse or promote products derived from this software without
22  * specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27  * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
37 #define ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
38 
39 #include "trc_pkt_types_etmv4.h"
40 #include "common/trc_cs_config.h"
41 
42 
43 /** @addtogroup ocsd_protocol_cfg
44 @{*/
45 
46 /** @name ETMv4 configuration
47 @{*/
48 
49 /*!
50  * @class EtmV4Config
51  * @brief Interpreter class for etm v4 config structure.
52  *
53  * Provides quick value interpretation methods for the ETMv4 config register values.
54  * Primarily inlined for efficient code.
55  */
56 class EtmV4Config : public CSConfig // public ocsd_etmv4_cfg
57 {
58 public:
59     EtmV4Config();  /**< Default constructor */
60     EtmV4Config(const ocsd_etmv4_cfg *cfg_regs);
~EtmV4Config()61     ~EtmV4Config() {}; /**< Default destructor */
62 
63 // operations to convert to and from C-API structure
64 
65     //! copy assignment operator for base structure into class.
66     EtmV4Config & operator=(const ocsd_etmv4_cfg *p_cfg);
67 
68     //! cast operator returning struct const reference
69     operator const ocsd_etmv4_cfg &() const { return m_cfg; };
70     //! cast operator returning struct const pointer
71     operator const ocsd_etmv4_cfg *() const { return &m_cfg; };
72 
coreProfile()73     const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; };
archVersion()74     const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; };
75 
76     /* idr 0 */
77     const bool LSasInstP0() const;
78     const bool hasDataTrace() const;
79     const bool hasBranchBroadcast() const;
80     const bool hasCondTrace() const;
81     const bool hasCycleCountI() const;
82     const bool hasRetStack() const;
83     const uint8_t numEvents() const;
84 
85     typedef enum _condType {
86         COND_PASS_FAIL,
87         COND_HAS_ASPR
88     } condType;
89 
90     const condType hasCondType() const;
91 
92     typedef enum _QSuppType {
93         Q_NONE,
94         Q_ICOUNT_ONLY,
95         Q_NO_ICOUNT_ONLY,
96         Q_FULL
97     } QSuppType;
98 
99     const QSuppType getQSuppType();
100     const bool hasQElem();
101     const bool hasQFilter();
102 
103     const bool hasTrcExcpData() const;
104     const uint32_t TimeStampSize() const;
105 
106     const bool commitOpt1() const;
107 
108     /* idr 1 */
109     const uint8_t MajVersion() const;
110     const uint8_t MinVersion() const;
111 
112     /* idr 2 */
113     const uint32_t iaSizeMax() const;
114     const uint32_t cidSize() const;
115     const uint32_t vmidSize();
116     const uint32_t daSize() const;
117     const uint32_t dvSize() const;
118     const uint32_t ccSize() const;
119     const bool vmidOpt() const;
120 
121     /* id regs 8-13*/
122     const uint32_t MaxSpecDepth() const;
123     const uint32_t P0_Key_Max() const;
124     const uint32_t P1_Key_Max() const;
125     const uint32_t P1_Spcl_Key_Max() const;
126     const uint32_t CondKeyMax() const;
127     const uint32_t CondSpecKeyMax() const;
128     const uint32_t CondKeyMaxIncr() const;
129 
130     /* trace idr */
131     virtual const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device.
132 
133     /* config R */
134     const bool enabledDVTrace() const;
135     const bool enabledDATrace() const;
136     const bool enabledDataTrace() const;
137 
138     typedef enum {
139         LSP0_NONE,
140         LSP0_L,
141         LSP0_S,
142         LSP0_LS
143     } LSP0_t;
144 
145     const bool enabledLSP0Trace() const;
146     const LSP0_t LSP0Type() const;
147 
148     const bool enabledBrBroad() const;
149     const bool enabledCCI() const;
150     const bool enabledCID() const;
151     const bool enabledVMID() const;
152 
153     typedef enum {
154         COND_TR_DIS,
155         COND_TR_LD,
156         COND_TR_ST,
157         COND_TR_LDST,
158         COND_TR_ALL
159     } CondITrace_t;
160 
161     const CondITrace_t enabledCondITrace();
162 
163     const bool enabledTS() const;
164     const bool enabledRetStack() const;
165 
166     const bool enabledQE() const;
167 
168 private:
169     void PrivateInit();
170     void CalcQSupp();
171     void CalcVMIDSize();
172 
173     bool m_QSuppCalc;
174     bool m_QSuppFilter;
175     QSuppType m_QSuppType;
176 
177     bool m_VMIDSzCalc;
178     uint32_t m_VMIDSize;
179 
180     bool m_condTraceCalc;
181     CondITrace_t m_CondTrace;
182 
183     ocsd_etmv4_cfg m_cfg;
184 };
185 
186 /* idr 0 */
LSasInstP0()187 inline const bool EtmV4Config::LSasInstP0() const
188 {
189     return (bool)((m_cfg.reg_idr0 & 0x6) == 0x6);
190 }
191 
hasDataTrace()192 inline const bool EtmV4Config::hasDataTrace() const
193 {
194     return (bool)((m_cfg.reg_idr0 & 0x18) == 0x18);
195 }
196 
hasBranchBroadcast()197 inline const bool EtmV4Config::hasBranchBroadcast() const
198 {
199     return (bool)((m_cfg.reg_idr0 & 0x20) == 0x20);
200 }
201 
hasCondTrace()202 inline const bool EtmV4Config::hasCondTrace() const
203 {
204     return (bool)((m_cfg.reg_idr0 & 0x40) == 0x40);
205 }
206 
hasCycleCountI()207 inline const bool EtmV4Config::hasCycleCountI() const
208 {
209     return (bool)((m_cfg.reg_idr0 & 0x80) == 0x80);
210 }
211 
hasRetStack()212 inline const bool EtmV4Config::hasRetStack() const
213 {
214     return (bool)((m_cfg.reg_idr0 & 0x200) == 0x200);
215 }
216 
numEvents()217 inline const uint8_t EtmV4Config::numEvents() const
218 {
219     return ((m_cfg.reg_idr0 >> 10) & 0x3) + 1;
220 }
221 
hasCondType()222 inline const EtmV4Config::condType EtmV4Config::hasCondType() const
223 {
224     return ((m_cfg.reg_idr0 & 0x3000) == 0x1000) ? EtmV4Config::COND_HAS_ASPR : EtmV4Config::COND_PASS_FAIL;
225 }
226 
getQSuppType()227 inline const EtmV4Config::QSuppType EtmV4Config::getQSuppType()
228 {
229     if(!m_QSuppCalc) CalcQSupp();
230     return m_QSuppType;
231 }
232 
hasQElem()233 inline const bool EtmV4Config::hasQElem()
234 {
235     if(!m_QSuppCalc) CalcQSupp();
236     return (bool)(m_QSuppType != Q_NONE);
237 }
238 
hasQFilter()239 inline const bool EtmV4Config::hasQFilter()
240 {
241     if(!m_QSuppCalc) CalcQSupp();
242     return m_QSuppFilter;
243 }
244 
hasTrcExcpData()245 inline const bool EtmV4Config::hasTrcExcpData() const
246 {
247     return (bool)((m_cfg.reg_idr0 & 0x20000) == 0x20000);
248 }
249 
TimeStampSize()250 inline const uint32_t EtmV4Config::TimeStampSize() const
251 {
252     uint32_t tsSizeF = (m_cfg.reg_idr0 >> 24) & 0x1F;
253     if(tsSizeF == 0x6)
254         return 48;
255     if(tsSizeF == 0x8)
256         return 64;
257     return 0;
258 }
259 
commitOpt1()260 inline const bool EtmV4Config::commitOpt1() const
261 {
262     return (bool)((m_cfg.reg_idr0 & 0x20000000) == 0x20000000) && hasCycleCountI();
263 }
264 
265     /* idr 1 */
MajVersion()266 inline const uint8_t EtmV4Config::MajVersion() const
267 {
268     return (uint8_t)((m_cfg.reg_idr1 >> 8) & 0xF);
269 }
270 
MinVersion()271 inline const uint8_t EtmV4Config::MinVersion() const
272 {
273     return (uint8_t)((m_cfg.reg_idr1 >> 4) & 0xF);
274 }
275 
276 
277 /* idr 2 */
iaSizeMax()278 inline const uint32_t EtmV4Config::iaSizeMax() const
279 {
280     return ((m_cfg.reg_idr2 & 0x1F) == 0x8) ? 64 : 32;
281 }
282 
cidSize()283 inline const uint32_t EtmV4Config::cidSize() const
284 {
285     return (((m_cfg.reg_idr2 >> 5) & 0x1F) == 0x4) ? 32 : 0;
286 }
287 
vmidSize()288 inline const uint32_t EtmV4Config::vmidSize()
289 {
290     if(!m_VMIDSzCalc)
291     {
292         CalcVMIDSize();
293     }
294     return m_VMIDSize;
295 }
296 
daSize()297 inline const uint32_t EtmV4Config::daSize() const
298 {
299     uint32_t daSizeF = ((m_cfg.reg_idr2 >> 15) & 0x1F);
300     if(daSizeF)
301         return (((m_cfg.reg_idr2 >> 15) & 0x1F) == 0x8) ? 64 : 32;
302     return 0;
303 }
304 
dvSize()305 inline const uint32_t EtmV4Config::dvSize() const
306 {
307     uint32_t dvSizeF = ((m_cfg.reg_idr2 >> 20) & 0x1F);
308     if(dvSizeF)
309         return (((m_cfg.reg_idr2 >> 20) & 0x1F) == 0x8) ? 64 : 32;
310     return 0;
311 }
312 
ccSize()313 inline const uint32_t EtmV4Config::ccSize() const
314 {
315     return ((m_cfg.reg_idr2 >> 25) & 0xF) + 12;
316 }
317 
vmidOpt()318 inline const bool EtmV4Config::vmidOpt() const
319 {
320     return (bool)((m_cfg.reg_idr2 & 0x20000000) == 0x20000000) && (MinVersion() > 0);
321 }
322 
323 /* id regs 8-13*/
324 
MaxSpecDepth()325 inline const uint32_t EtmV4Config::MaxSpecDepth() const
326 {
327     return m_cfg.reg_idr8;
328 }
329 
P0_Key_Max()330 inline const uint32_t EtmV4Config::P0_Key_Max() const
331 {
332     return (m_cfg.reg_idr9 == 0) ? 1 : m_cfg.reg_idr9;
333 }
334 
P1_Key_Max()335 inline const uint32_t EtmV4Config::P1_Key_Max() const
336 {
337     return m_cfg.reg_idr10;
338 }
339 
P1_Spcl_Key_Max()340 inline const uint32_t  EtmV4Config::P1_Spcl_Key_Max() const
341 {
342     return m_cfg.reg_idr11;
343 }
344 
CondKeyMax()345 inline const uint32_t EtmV4Config::CondKeyMax() const
346 {
347     return m_cfg.reg_idr12;
348 }
349 
CondSpecKeyMax()350 inline const uint32_t EtmV4Config::CondSpecKeyMax() const
351 {
352     return m_cfg.reg_idr13;
353 }
354 
CondKeyMaxIncr()355 inline const uint32_t EtmV4Config::CondKeyMaxIncr() const
356 {
357     return m_cfg.reg_idr12 - m_cfg.reg_idr13;
358 }
359 
getTraceID()360 inline const uint8_t EtmV4Config::getTraceID() const
361 {
362     return (uint8_t)(m_cfg.reg_traceidr & 0x7F);
363 }
364 
365     /* config R */
enabledDVTrace()366 inline const bool EtmV4Config::enabledDVTrace() const
367 {
368     return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 17)) != 0);
369 }
370 
enabledDATrace()371 inline const bool EtmV4Config::enabledDATrace() const
372 {
373     return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 16)) != 0);
374 }
375 
enabledDataTrace()376 inline const bool EtmV4Config::enabledDataTrace() const
377 {
378     return enabledDATrace() || enabledDVTrace();
379 }
380 
enabledLSP0Trace()381 inline const bool EtmV4Config::enabledLSP0Trace() const
382 {
383     return ((m_cfg.reg_configr & 0x6) != 0);
384 }
385 
LSP0Type()386 inline const EtmV4Config::LSP0_t EtmV4Config::LSP0Type() const
387 {
388     return (LSP0_t)((m_cfg.reg_configr & 0x6) >> 1);
389 }
390 
enabledBrBroad()391 inline const bool EtmV4Config::enabledBrBroad() const
392 {
393     return ((m_cfg.reg_configr & (0x1 << 3)) != 0);
394 }
395 
enabledCCI()396 inline const bool EtmV4Config::enabledCCI() const
397 {
398     return ((m_cfg.reg_configr & (0x1 << 4)) != 0);
399 }
400 
enabledCID()401 inline const bool EtmV4Config::enabledCID() const
402 {
403     return ((m_cfg.reg_configr & (0x1 << 6)) != 0);
404 }
405 
enabledVMID()406 inline const bool EtmV4Config::enabledVMID() const
407 {
408     return ((m_cfg.reg_configr & (0x1 << 7)) != 0);
409 }
410 
enabledCondITrace()411 inline const EtmV4Config::CondITrace_t EtmV4Config::enabledCondITrace()
412 {
413     if(!m_condTraceCalc)
414     {
415         switch((m_cfg.reg_configr >> 8) & 0x7)
416         {
417         default:
418         case 0: m_CondTrace = COND_TR_DIS; break;
419         case 1: m_CondTrace = COND_TR_LD; break;
420         case 2: m_CondTrace = COND_TR_ST; break;
421         case 3: m_CondTrace = COND_TR_LDST; break;
422         case 7: m_CondTrace = COND_TR_ALL; break;
423         }
424         m_condTraceCalc = true;
425     }
426     return m_CondTrace;
427 }
428 
enabledTS()429 inline const bool EtmV4Config::enabledTS() const
430 {
431     return ((m_cfg.reg_configr & (0x1 << 11)) != 0);
432 }
433 
enabledRetStack()434 inline const bool EtmV4Config::enabledRetStack() const
435 {
436     return ((m_cfg.reg_configr & (0x1 << 12)) != 0);
437 }
438 
enabledQE()439 inline const bool EtmV4Config::enabledQE() const
440 {
441        return ((m_cfg.reg_configr & (0x3 << 13)) != 0);
442 }
443 
444 /** @}*/
445 /** @}*/
446 
447 #endif // ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
448 
449 /* End of File trc_cmp_cfg_etmv4.h */
450