1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
3 */
4
5 #include <string.h>
6
7 #include <rte_ethdev_driver.h>
8 #include <rte_cycles.h>
9 #include <rte_malloc.h>
10
11 #include "lio_logs.h"
12 #include "lio_23xx_vf.h"
13 #include "lio_23xx_reg.h"
14 #include "lio_mbox.h"
15
16 static int
cn23xx_vf_reset_io_queues(struct lio_device * lio_dev,uint32_t num_queues)17 cn23xx_vf_reset_io_queues(struct lio_device *lio_dev, uint32_t num_queues)
18 {
19 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
20 uint64_t d64, q_no;
21 int ret_val = 0;
22
23 PMD_INIT_FUNC_TRACE();
24
25 for (q_no = 0; q_no < num_queues; q_no++) {
26 /* set RST bit to 1. This bit applies to both IQ and OQ */
27 d64 = lio_read_csr64(lio_dev,
28 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
29 d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
30 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
31 d64);
32 }
33
34 /* wait until the RST bit is clear or the RST and QUIET bits are set */
35 for (q_no = 0; q_no < num_queues; q_no++) {
36 volatile uint64_t reg_val;
37
38 reg_val = lio_read_csr64(lio_dev,
39 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
40 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
41 !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
42 loop) {
43 reg_val = lio_read_csr64(
44 lio_dev,
45 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
46 loop = loop - 1;
47 }
48
49 if (loop == 0) {
50 lio_dev_err(lio_dev,
51 "clearing the reset reg failed or setting the quiet reg failed for qno: %lu\n",
52 (unsigned long)q_no);
53 return -1;
54 }
55
56 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
57 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
58 reg_val);
59
60 reg_val = lio_read_csr64(
61 lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
62 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
63 lio_dev_err(lio_dev,
64 "clearing the reset failed for qno: %lu\n",
65 (unsigned long)q_no);
66 ret_val = -1;
67 }
68 }
69
70 return ret_val;
71 }
72
73 static int
cn23xx_vf_setup_global_input_regs(struct lio_device * lio_dev)74 cn23xx_vf_setup_global_input_regs(struct lio_device *lio_dev)
75 {
76 uint64_t q_no;
77 uint64_t d64;
78
79 PMD_INIT_FUNC_TRACE();
80
81 if (cn23xx_vf_reset_io_queues(lio_dev,
82 lio_dev->sriov_info.rings_per_vf))
83 return -1;
84
85 for (q_no = 0; q_no < (lio_dev->sriov_info.rings_per_vf); q_no++) {
86 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_DOORBELL(q_no),
87 0xFFFFFFFF);
88
89 d64 = lio_read_csr64(lio_dev,
90 CN23XX_SLI_IQ_INSTR_COUNT64(q_no));
91
92 d64 &= 0xEFFFFFFFFFFFFFFFL;
93
94 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_INSTR_COUNT64(q_no),
95 d64);
96
97 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
98 * the Input Queues
99 */
100 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
101 CN23XX_PKT_INPUT_CTL_MASK);
102 }
103
104 return 0;
105 }
106
107 static void
cn23xx_vf_setup_global_output_regs(struct lio_device * lio_dev)108 cn23xx_vf_setup_global_output_regs(struct lio_device *lio_dev)
109 {
110 uint32_t reg_val;
111 uint32_t q_no;
112
113 PMD_INIT_FUNC_TRACE();
114
115 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
116 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
117 0xFFFFFFFF);
118
119 reg_val =
120 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no));
121
122 reg_val &= 0xEFFFFFFFFFFFFFFFL;
123
124 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no), reg_val);
125
126 reg_val =
127 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
128
129 /* set IPTR & DPTR */
130 reg_val |=
131 (CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
132
133 /* reset BMODE */
134 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
135
136 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
137 * for Output Queue Scatter List
138 * reset ROR_P, NSR_P
139 */
140 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
141 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
142
143 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
144 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
145 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
146 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
147 #endif
148 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
149 * for Output Queue Data
150 * reset ROR, NSR
151 */
152 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
153 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
154 /* set the ES bit */
155 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
156
157 /* write all the selected settings */
158 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
159 reg_val);
160 }
161 }
162
163 static int
cn23xx_vf_setup_device_regs(struct lio_device * lio_dev)164 cn23xx_vf_setup_device_regs(struct lio_device *lio_dev)
165 {
166 PMD_INIT_FUNC_TRACE();
167
168 if (cn23xx_vf_setup_global_input_regs(lio_dev))
169 return -1;
170
171 cn23xx_vf_setup_global_output_regs(lio_dev);
172
173 return 0;
174 }
175
176 static void
cn23xx_vf_setup_iq_regs(struct lio_device * lio_dev,uint32_t iq_no)177 cn23xx_vf_setup_iq_regs(struct lio_device *lio_dev, uint32_t iq_no)
178 {
179 struct lio_instr_queue *iq = lio_dev->instr_queue[iq_no];
180 uint64_t pkt_in_done = 0;
181
182 PMD_INIT_FUNC_TRACE();
183
184 /* Write the start of the input queue's ring and its size */
185 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
186 iq->base_addr_dma);
187 lio_write_csr(lio_dev, CN23XX_SLI_IQ_SIZE(iq_no), iq->nb_desc);
188
189 /* Remember the doorbell & instruction count register addr
190 * for this queue
191 */
192 iq->doorbell_reg = (uint8_t *)lio_dev->hw_addr +
193 CN23XX_SLI_IQ_DOORBELL(iq_no);
194 iq->inst_cnt_reg = (uint8_t *)lio_dev->hw_addr +
195 CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
196 lio_dev_dbg(lio_dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
197 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
198
199 /* Store the current instruction counter (used in flush_iq
200 * calculation)
201 */
202 pkt_in_done = rte_read64(iq->inst_cnt_reg);
203
204 /* Clear the count by writing back what we read, but don't
205 * enable data traffic here
206 */
207 rte_write64(pkt_in_done, iq->inst_cnt_reg);
208 }
209
210 static void
cn23xx_vf_setup_oq_regs(struct lio_device * lio_dev,uint32_t oq_no)211 cn23xx_vf_setup_oq_regs(struct lio_device *lio_dev, uint32_t oq_no)
212 {
213 struct lio_droq *droq = lio_dev->droq[oq_no];
214
215 PMD_INIT_FUNC_TRACE();
216
217 lio_write_csr64(lio_dev, CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
218 droq->desc_ring_dma);
219 lio_write_csr(lio_dev, CN23XX_SLI_OQ_SIZE(oq_no), droq->nb_desc);
220
221 lio_write_csr(lio_dev, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
222 (droq->buffer_size | (OCTEON_RH_SIZE << 16)));
223
224 /* Get the mapped address of the pkt_sent and pkts_credit regs */
225 droq->pkts_sent_reg = (uint8_t *)lio_dev->hw_addr +
226 CN23XX_SLI_OQ_PKTS_SENT(oq_no);
227 droq->pkts_credit_reg = (uint8_t *)lio_dev->hw_addr +
228 CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);
229 }
230
231 static void
cn23xx_vf_free_mbox(struct lio_device * lio_dev)232 cn23xx_vf_free_mbox(struct lio_device *lio_dev)
233 {
234 PMD_INIT_FUNC_TRACE();
235
236 rte_free(lio_dev->mbox[0]);
237 lio_dev->mbox[0] = NULL;
238
239 rte_free(lio_dev->mbox);
240 lio_dev->mbox = NULL;
241 }
242
243 static int
cn23xx_vf_setup_mbox(struct lio_device * lio_dev)244 cn23xx_vf_setup_mbox(struct lio_device *lio_dev)
245 {
246 struct lio_mbox *mbox;
247
248 PMD_INIT_FUNC_TRACE();
249
250 if (lio_dev->mbox == NULL) {
251 lio_dev->mbox = rte_zmalloc(NULL, sizeof(void *), 0);
252 if (lio_dev->mbox == NULL)
253 return -ENOMEM;
254 }
255
256 mbox = rte_zmalloc(NULL, sizeof(struct lio_mbox), 0);
257 if (mbox == NULL) {
258 rte_free(lio_dev->mbox);
259 lio_dev->mbox = NULL;
260 return -ENOMEM;
261 }
262
263 rte_spinlock_init(&mbox->lock);
264
265 mbox->lio_dev = lio_dev;
266
267 mbox->q_no = 0;
268
269 mbox->state = LIO_MBOX_STATE_IDLE;
270
271 /* VF mbox interrupt reg */
272 mbox->mbox_int_reg = (uint8_t *)lio_dev->hw_addr +
273 CN23XX_VF_SLI_PKT_MBOX_INT(0);
274 /* VF reads from SIG0 reg */
275 mbox->mbox_read_reg = (uint8_t *)lio_dev->hw_addr +
276 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0);
277 /* VF writes into SIG1 reg */
278 mbox->mbox_write_reg = (uint8_t *)lio_dev->hw_addr +
279 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1);
280
281 lio_dev->mbox[0] = mbox;
282
283 rte_write64(LIO_PFVFSIG, mbox->mbox_read_reg);
284
285 return 0;
286 }
287
288 static int
cn23xx_vf_enable_io_queues(struct lio_device * lio_dev)289 cn23xx_vf_enable_io_queues(struct lio_device *lio_dev)
290 {
291 uint32_t q_no;
292
293 PMD_INIT_FUNC_TRACE();
294
295 for (q_no = 0; q_no < lio_dev->num_iqs; q_no++) {
296 uint64_t reg_val;
297
298 /* set the corresponding IQ IS_64B bit */
299 if (lio_dev->io_qmask.iq64B & (1ULL << q_no)) {
300 reg_val = lio_read_csr64(
301 lio_dev,
302 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
303 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B;
304 lio_write_csr64(lio_dev,
305 CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
306 reg_val);
307 }
308
309 /* set the corresponding IQ ENB bit */
310 if (lio_dev->io_qmask.iq & (1ULL << q_no)) {
311 reg_val = lio_read_csr64(
312 lio_dev,
313 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
314 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB;
315 lio_write_csr64(lio_dev,
316 CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
317 reg_val);
318 }
319 }
320 for (q_no = 0; q_no < lio_dev->num_oqs; q_no++) {
321 uint32_t reg_val;
322
323 /* set the corresponding OQ ENB bit */
324 if (lio_dev->io_qmask.oq & (1ULL << q_no)) {
325 reg_val = lio_read_csr(
326 lio_dev,
327 CN23XX_SLI_OQ_PKT_CONTROL(q_no));
328 reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB;
329 lio_write_csr(lio_dev,
330 CN23XX_SLI_OQ_PKT_CONTROL(q_no),
331 reg_val);
332 }
333 }
334
335 return 0;
336 }
337
338 static void
cn23xx_vf_disable_io_queues(struct lio_device * lio_dev)339 cn23xx_vf_disable_io_queues(struct lio_device *lio_dev)
340 {
341 uint32_t num_queues;
342
343 PMD_INIT_FUNC_TRACE();
344
345 /* per HRM, rings can only be disabled via reset operation,
346 * NOT via SLI_PKT()_INPUT/OUTPUT_CONTROL[ENB]
347 */
348 num_queues = lio_dev->num_iqs;
349 if (num_queues < lio_dev->num_oqs)
350 num_queues = lio_dev->num_oqs;
351
352 cn23xx_vf_reset_io_queues(lio_dev, num_queues);
353 }
354
355 void
cn23xx_vf_ask_pf_to_do_flr(struct lio_device * lio_dev)356 cn23xx_vf_ask_pf_to_do_flr(struct lio_device *lio_dev)
357 {
358 struct lio_mbox_cmd mbox_cmd;
359
360 memset(&mbox_cmd, 0, sizeof(struct lio_mbox_cmd));
361 mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
362 mbox_cmd.msg.s.resp_needed = 0;
363 mbox_cmd.msg.s.cmd = LIO_VF_FLR_REQUEST;
364 mbox_cmd.msg.s.len = 1;
365 mbox_cmd.q_no = 0;
366 mbox_cmd.recv_len = 0;
367 mbox_cmd.recv_status = 0;
368 mbox_cmd.fn = NULL;
369 mbox_cmd.fn_arg = 0;
370
371 lio_mbox_write(lio_dev, &mbox_cmd);
372 }
373
374 static void
cn23xx_pfvf_hs_callback(struct lio_device * lio_dev,struct lio_mbox_cmd * cmd,void * arg)375 cn23xx_pfvf_hs_callback(struct lio_device *lio_dev,
376 struct lio_mbox_cmd *cmd, void *arg)
377 {
378 uint32_t major = 0;
379
380 PMD_INIT_FUNC_TRACE();
381
382 rte_memcpy((uint8_t *)&lio_dev->pfvf_hsword, cmd->msg.s.params, 6);
383 if (cmd->recv_len > 1) {
384 struct lio_version *lio_ver = (struct lio_version *)cmd->data;
385
386 major = lio_ver->major;
387 major = major << 16;
388 }
389
390 rte_atomic64_set((rte_atomic64_t *)arg, major | 1);
391 }
392
393 int
cn23xx_pfvf_handshake(struct lio_device * lio_dev)394 cn23xx_pfvf_handshake(struct lio_device *lio_dev)
395 {
396 struct lio_mbox_cmd mbox_cmd;
397 struct lio_version *lio_ver = (struct lio_version *)&mbox_cmd.data[0];
398 uint32_t q_no, count = 0;
399 rte_atomic64_t status;
400 uint32_t pfmajor;
401 uint32_t vfmajor;
402 uint32_t ret;
403
404 PMD_INIT_FUNC_TRACE();
405
406 /* Sending VF_ACTIVE indication to the PF driver */
407 lio_dev_dbg(lio_dev, "requesting info from PF\n");
408
409 mbox_cmd.msg.mbox_msg64 = 0;
410 mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
411 mbox_cmd.msg.s.resp_needed = 1;
412 mbox_cmd.msg.s.cmd = LIO_VF_ACTIVE;
413 mbox_cmd.msg.s.len = 2;
414 mbox_cmd.data[0] = 0;
415 lio_ver->major = LIO_BASE_MAJOR_VERSION;
416 lio_ver->minor = LIO_BASE_MINOR_VERSION;
417 lio_ver->micro = LIO_BASE_MICRO_VERSION;
418 mbox_cmd.q_no = 0;
419 mbox_cmd.recv_len = 0;
420 mbox_cmd.recv_status = 0;
421 mbox_cmd.fn = (lio_mbox_callback)cn23xx_pfvf_hs_callback;
422 mbox_cmd.fn_arg = (void *)&status;
423
424 if (lio_mbox_write(lio_dev, &mbox_cmd)) {
425 lio_dev_err(lio_dev, "Write to mailbox failed\n");
426 return -1;
427 }
428
429 rte_atomic64_set(&status, 0);
430
431 do {
432 rte_delay_ms(1);
433 } while ((rte_atomic64_read(&status) == 0) && (count++ < 10000));
434
435 ret = rte_atomic64_read(&status);
436 if (ret == 0) {
437 lio_dev_err(lio_dev, "cn23xx_pfvf_handshake timeout\n");
438 return -1;
439 }
440
441 for (q_no = 0; q_no < lio_dev->num_iqs; q_no++)
442 lio_dev->instr_queue[q_no]->txpciq.s.pkind =
443 lio_dev->pfvf_hsword.pkind;
444
445 vfmajor = LIO_BASE_MAJOR_VERSION;
446 pfmajor = ret >> 16;
447 if (pfmajor != vfmajor) {
448 lio_dev_err(lio_dev,
449 "VF LiquidIO driver (major version %d) is not compatible with LiquidIO PF driver (major version %d)\n",
450 vfmajor, pfmajor);
451 ret = -EPERM;
452 } else {
453 lio_dev_dbg(lio_dev,
454 "VF LiquidIO driver (major version %d), LiquidIO PF driver (major version %d)\n",
455 vfmajor, pfmajor);
456 ret = 0;
457 }
458
459 lio_dev_dbg(lio_dev, "got data from PF pkind is %d\n",
460 lio_dev->pfvf_hsword.pkind);
461
462 return ret;
463 }
464
465 void
cn23xx_vf_handle_mbox(struct lio_device * lio_dev)466 cn23xx_vf_handle_mbox(struct lio_device *lio_dev)
467 {
468 uint64_t mbox_int_val;
469
470 /* read and clear by writing 1 */
471 mbox_int_val = rte_read64(lio_dev->mbox[0]->mbox_int_reg);
472 rte_write64(mbox_int_val, lio_dev->mbox[0]->mbox_int_reg);
473 if (lio_mbox_read(lio_dev->mbox[0]))
474 lio_mbox_process_message(lio_dev->mbox[0]);
475 }
476
477 int
cn23xx_vf_setup_device(struct lio_device * lio_dev)478 cn23xx_vf_setup_device(struct lio_device *lio_dev)
479 {
480 uint64_t reg_val;
481
482 PMD_INIT_FUNC_TRACE();
483
484 /* INPUT_CONTROL[RPVF] gives the VF IOq count */
485 reg_val = lio_read_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(0));
486
487 lio_dev->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
488 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
489 lio_dev->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
490 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
491
492 reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
493
494 lio_dev->sriov_info.rings_per_vf =
495 reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
496
497 lio_dev->default_config = lio_get_conf(lio_dev);
498 if (lio_dev->default_config == NULL)
499 return -1;
500
501 lio_dev->fn_list.setup_iq_regs = cn23xx_vf_setup_iq_regs;
502 lio_dev->fn_list.setup_oq_regs = cn23xx_vf_setup_oq_regs;
503 lio_dev->fn_list.setup_mbox = cn23xx_vf_setup_mbox;
504 lio_dev->fn_list.free_mbox = cn23xx_vf_free_mbox;
505
506 lio_dev->fn_list.setup_device_regs = cn23xx_vf_setup_device_regs;
507
508 lio_dev->fn_list.enable_io_queues = cn23xx_vf_enable_io_queues;
509 lio_dev->fn_list.disable_io_queues = cn23xx_vf_disable_io_queues;
510
511 return 0;
512 }
513
514