1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #include <rte_cryptodev.h>
6 #include <cryptodev_pmd.h>
7 #include <rte_event_crypto_adapter.h>
8 #include <rte_ip.h>
9
10 #include "cn10k_cryptodev.h"
11 #include "cn10k_cryptodev_ops.h"
12 #include "cn10k_ipsec_la_ops.h"
13 #include "cn10k_ipsec.h"
14 #include "cnxk_ae.h"
15 #include "cnxk_cryptodev.h"
16 #include "cnxk_cryptodev_ops.h"
17 #include "cnxk_se.h"
18
19 #include "roc_api.h"
20
21 static inline struct cnxk_se_sess *
cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp * qp,struct rte_crypto_op * op)22 cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op)
23 {
24 const int driver_id = cn10k_cryptodev_driver_id;
25 struct rte_crypto_sym_op *sym_op = op->sym;
26 struct rte_cryptodev_sym_session *sess;
27 struct cnxk_se_sess *priv;
28 int ret;
29
30 /* Create temporary session */
31 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
32 if (sess == NULL)
33 return NULL;
34
35 ret = sym_session_configure(qp->lf.roc_cpt, driver_id, sym_op->xform,
36 sess, qp->sess_mp_priv);
37 if (ret)
38 goto sess_put;
39
40 priv = get_sym_session_private_data(sess, driver_id);
41
42 sym_op->session = sess;
43
44 return priv;
45
46 sess_put:
47 rte_mempool_put(qp->sess_mp, sess);
48 return NULL;
49 }
50
51 static __rte_always_inline int __rte_hot
cpt_sec_inst_fill(struct cnxk_cpt_qp * qp,struct rte_crypto_op * op,struct cn10k_sec_session * sess,struct cpt_inst_s * inst)52 cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,
53 struct cn10k_sec_session *sess, struct cpt_inst_s *inst)
54 {
55 struct rte_crypto_sym_op *sym_op = op->sym;
56 struct cn10k_ipsec_sa *sa;
57 int ret;
58
59 if (unlikely(sym_op->m_dst && sym_op->m_dst != sym_op->m_src)) {
60 plt_dp_err("Out of place is not supported");
61 return -ENOTSUP;
62 }
63
64 if (unlikely(!rte_pktmbuf_is_contiguous(sym_op->m_src))) {
65 plt_dp_err("Scatter Gather mode is not supported");
66 return -ENOTSUP;
67 }
68
69 sa = &sess->sa;
70
71 if (sa->is_outbound)
72 ret = process_outb_sa(&qp->lf, op, sa, inst);
73 else
74 ret = process_inb_sa(op, sa, inst);
75
76 return ret;
77 }
78
79 static __rte_always_inline int __rte_hot
cpt_sym_inst_fill(struct cnxk_cpt_qp * qp,struct rte_crypto_op * op,struct cnxk_se_sess * sess,struct cpt_inflight_req * infl_req,struct cpt_inst_s * inst)80 cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,
81 struct cnxk_se_sess *sess, struct cpt_inflight_req *infl_req,
82 struct cpt_inst_s *inst)
83 {
84 uint64_t cpt_op;
85 int ret;
86
87 cpt_op = sess->cpt_op;
88
89 if (cpt_op & ROC_SE_OP_CIPHER_MASK)
90 ret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst);
91 else
92 ret = fill_digest_params(op, sess, &qp->meta_info, infl_req,
93 inst);
94
95 return ret;
96 }
97
98 static inline int
cn10k_cpt_fill_inst(struct cnxk_cpt_qp * qp,struct rte_crypto_op * ops[],struct cpt_inst_s inst[],struct cpt_inflight_req * infl_req)99 cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[],
100 struct cpt_inst_s inst[], struct cpt_inflight_req *infl_req)
101 {
102 struct cn10k_sec_session *sec_sess;
103 struct rte_crypto_asym_op *asym_op;
104 struct rte_crypto_sym_op *sym_op;
105 struct cnxk_ae_sess *ae_sess;
106 struct cnxk_se_sess *sess;
107 struct rte_crypto_op *op;
108 uint64_t w7;
109 int ret;
110
111 const union cpt_res_s res = {
112 .cn10k.compcode = CPT_COMP_NOT_DONE,
113 };
114
115 op = ops[0];
116
117 inst[0].w0.u64 = 0;
118 inst[0].w2.u64 = 0;
119 inst[0].w3.u64 = 0;
120
121 sym_op = op->sym;
122
123 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
124 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
125 sec_sess = get_sec_session_private_data(
126 sym_op->sec_session);
127 ret = cpt_sec_inst_fill(qp, op, sec_sess, &inst[0]);
128 if (unlikely(ret))
129 return 0;
130 w7 = sec_sess->sa.inst.w7;
131 } else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
132 sess = get_sym_session_private_data(
133 sym_op->session, cn10k_cryptodev_driver_id);
134 ret = cpt_sym_inst_fill(qp, op, sess, infl_req,
135 &inst[0]);
136 if (unlikely(ret))
137 return 0;
138 w7 = sess->cpt_inst_w7;
139 } else {
140 sess = cn10k_cpt_sym_temp_sess_create(qp, op);
141 if (unlikely(sess == NULL)) {
142 plt_dp_err("Could not create temp session");
143 return 0;
144 }
145
146 ret = cpt_sym_inst_fill(qp, op, sess, infl_req,
147 &inst[0]);
148 if (unlikely(ret)) {
149 sym_session_clear(cn10k_cryptodev_driver_id,
150 op->sym->session);
151 rte_mempool_put(qp->sess_mp, op->sym->session);
152 return 0;
153 }
154 w7 = sess->cpt_inst_w7;
155 }
156 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
157
158 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
159 asym_op = op->asym;
160 ae_sess = (struct cnxk_ae_sess *)
161 asym_op->session->sess_private_data;
162 ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0],
163 ae_sess);
164 if (unlikely(ret))
165 return 0;
166 w7 = ae_sess->cpt_inst_w7;
167 } else {
168 plt_dp_err("Not supported Asym op without session");
169 return 0;
170 }
171 } else {
172 plt_dp_err("Unsupported op type");
173 return 0;
174 }
175
176 inst[0].res_addr = (uint64_t)&infl_req->res;
177 __atomic_store_n(&infl_req->res.u64[0], res.u64[0], __ATOMIC_RELAXED);
178 infl_req->cop = op;
179
180 inst[0].w7.u64 = w7;
181
182 return 1;
183 }
184
185 #define PKTS_PER_LOOP 32
186 #define PKTS_PER_STEORL 16
187
188 static uint16_t
cn10k_cpt_enqueue_burst(void * qptr,struct rte_crypto_op ** ops,uint16_t nb_ops)189 cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
190 {
191 uint64_t lmt_base, lmt_arg, io_addr;
192 struct cpt_inflight_req *infl_req;
193 uint16_t nb_allowed, count = 0;
194 struct cnxk_cpt_qp *qp = qptr;
195 struct pending_queue *pend_q;
196 struct cpt_inst_s *inst;
197 uint16_t lmt_id;
198 uint64_t head;
199 int ret, i;
200
201 pend_q = &qp->pend_q;
202
203 const uint64_t pq_mask = pend_q->pq_mask;
204
205 head = pend_q->head;
206 nb_allowed = pending_queue_free_cnt(head, pend_q->tail, pq_mask);
207 nb_ops = RTE_MIN(nb_ops, nb_allowed);
208
209 if (unlikely(nb_ops == 0))
210 return 0;
211
212 lmt_base = qp->lmtline.lmt_base;
213 io_addr = qp->lmtline.io_addr;
214
215 ROC_LMT_BASE_ID_GET(lmt_base, lmt_id);
216 inst = (struct cpt_inst_s *)lmt_base;
217
218 again:
219 for (i = 0; i < RTE_MIN(PKTS_PER_LOOP, nb_ops); i++) {
220 infl_req = &pend_q->req_queue[head];
221 infl_req->op_flags = 0;
222
223 ret = cn10k_cpt_fill_inst(qp, ops + i, &inst[2 * i], infl_req);
224 if (unlikely(ret != 1)) {
225 plt_dp_err("Could not process op: %p", ops + i);
226 if (i == 0)
227 goto pend_q_commit;
228 break;
229 }
230
231 pending_queue_advance(&head, pq_mask);
232 }
233
234 if (i > PKTS_PER_STEORL) {
235 lmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 |
236 (uint64_t)lmt_id;
237 roc_lmt_submit_steorl(lmt_arg, io_addr);
238 lmt_arg = ROC_CN10K_CPT_LMT_ARG |
239 (i - PKTS_PER_STEORL - 1) << 12 |
240 (uint64_t)(lmt_id + PKTS_PER_STEORL);
241 roc_lmt_submit_steorl(lmt_arg, io_addr);
242 } else {
243 lmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 |
244 (uint64_t)lmt_id;
245 roc_lmt_submit_steorl(lmt_arg, io_addr);
246 }
247
248 rte_io_wmb();
249
250 if (nb_ops - i > 0 && i == PKTS_PER_LOOP) {
251 nb_ops -= i;
252 ops += i;
253 count += i;
254 goto again;
255 }
256
257 pend_q_commit:
258 rte_atomic_thread_fence(__ATOMIC_RELEASE);
259
260 pend_q->head = head;
261 pend_q->time_out = rte_get_timer_cycles() +
262 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
263
264 return count + i;
265 }
266
267 uint16_t
cn10k_cpt_crypto_adapter_enqueue(uintptr_t base,struct rte_crypto_op * op)268 cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)
269 {
270 union rte_event_crypto_metadata *ec_mdata;
271 struct cpt_inflight_req *infl_req;
272 struct rte_event *rsp_info;
273 uint64_t lmt_base, lmt_arg;
274 struct cpt_inst_s *inst;
275 struct cnxk_cpt_qp *qp;
276 uint8_t cdev_id;
277 uint16_t lmt_id;
278 uint16_t qp_id;
279 int ret;
280
281 ec_mdata = cnxk_event_crypto_mdata_get(op);
282 if (!ec_mdata) {
283 rte_errno = EINVAL;
284 return 0;
285 }
286
287 cdev_id = ec_mdata->request_info.cdev_id;
288 qp_id = ec_mdata->request_info.queue_pair_id;
289 qp = rte_cryptodevs[cdev_id].data->queue_pairs[qp_id];
290 rsp_info = &ec_mdata->response_info;
291
292 if (unlikely(!qp->ca.enabled)) {
293 rte_errno = EINVAL;
294 return 0;
295 }
296
297 if (unlikely(rte_mempool_get(qp->ca.req_mp, (void **)&infl_req))) {
298 rte_errno = ENOMEM;
299 return 0;
300 }
301 infl_req->op_flags = 0;
302
303 lmt_base = qp->lmtline.lmt_base;
304 ROC_LMT_BASE_ID_GET(lmt_base, lmt_id);
305 inst = (struct cpt_inst_s *)lmt_base;
306
307 ret = cn10k_cpt_fill_inst(qp, &op, inst, infl_req);
308 if (unlikely(ret != 1)) {
309 plt_dp_err("Could not process op: %p", op);
310 rte_mempool_put(qp->ca.req_mp, infl_req);
311 return 0;
312 }
313
314 infl_req->cop = op;
315 infl_req->res.cn10k.compcode = CPT_COMP_NOT_DONE;
316 infl_req->qp = qp;
317 inst->w0.u64 = 0;
318 inst->res_addr = (uint64_t)&infl_req->res;
319 inst->w2.u64 = CNXK_CPT_INST_W2(
320 (RTE_EVENT_TYPE_CRYPTODEV << 28) | rsp_info->flow_id,
321 rsp_info->sched_type, rsp_info->queue_id, 0);
322 inst->w3.u64 = CNXK_CPT_INST_W3(1, infl_req);
323
324 if (roc_cpt_is_iq_full(&qp->lf)) {
325 rte_mempool_put(qp->ca.req_mp, infl_req);
326 rte_errno = EAGAIN;
327 return 0;
328 }
329
330 if (!rsp_info->sched_type)
331 roc_sso_hws_head_wait(base);
332
333 lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;
334 roc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr);
335
336 rte_io_wmb();
337
338 return 1;
339 }
340
341 static inline void
cn10k_cpt_sec_post_process(struct rte_crypto_op * cop,struct cpt_cn10k_res_s * res)342 cn10k_cpt_sec_post_process(struct rte_crypto_op *cop,
343 struct cpt_cn10k_res_s *res)
344 {
345 struct rte_mbuf *mbuf = cop->sym->m_src;
346 const uint16_t m_len = res->rlen;
347
348 mbuf->data_len = m_len;
349 mbuf->pkt_len = m_len;
350
351 switch (res->uc_compcode) {
352 case ROC_IE_OT_UCC_SUCCESS:
353 break;
354 case ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM:
355 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
356 break;
357 case ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM:
358 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD |
359 RTE_MBUF_F_RX_IP_CKSUM_GOOD;
360 break;
361 case ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM:
362 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD |
363 RTE_MBUF_F_RX_IP_CKSUM_GOOD;
364 break;
365 case ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM:
366 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
367 break;
368 case ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST:
369 cop->aux_flags = RTE_CRYPTO_OP_AUX_FLAGS_IPSEC_SOFT_EXPIRY;
370 break;
371 default:
372 plt_dp_err("Success with unknown microcode completion code");
373 break;
374 }
375 }
376
377 static inline void
cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp * qp,struct rte_crypto_op * cop,struct cpt_inflight_req * infl_req,struct cpt_cn10k_res_s * res)378 cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,
379 struct rte_crypto_op *cop,
380 struct cpt_inflight_req *infl_req,
381 struct cpt_cn10k_res_s *res)
382 {
383 const uint8_t uc_compcode = res->uc_compcode;
384 const uint8_t compcode = res->compcode;
385 unsigned int sz;
386
387 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
388
389 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC &&
390 cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
391 if (likely(compcode == CPT_COMP_WARN)) {
392 /* Success with additional info */
393 cn10k_cpt_sec_post_process(cop, res);
394 } else {
395 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
396 plt_dp_info("HW completion code 0x%x", res->compcode);
397 if (compcode == CPT_COMP_GOOD) {
398 plt_dp_info(
399 "Request failed with microcode error");
400 plt_dp_info("MC completion code 0x%x",
401 uc_compcode);
402 }
403 }
404
405 return;
406 }
407
408 if (likely(compcode == CPT_COMP_GOOD || compcode == CPT_COMP_WARN)) {
409 if (unlikely(uc_compcode)) {
410 if (uc_compcode == ROC_SE_ERR_GC_ICV_MISCOMPARE)
411 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
412 else
413 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
414
415 plt_dp_info("Request failed with microcode error");
416 plt_dp_info("MC completion code 0x%x",
417 res->uc_compcode);
418 goto temp_sess_free;
419 }
420
421 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
422 /* Verify authentication data if required */
423 if (unlikely(infl_req->op_flags &
424 CPT_OP_FLAGS_AUTH_VERIFY)) {
425 uintptr_t *rsp = infl_req->mdata;
426 compl_auth_verify(cop, (uint8_t *)rsp[0],
427 rsp[1]);
428 }
429 } else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
430 struct rte_crypto_asym_op *op = cop->asym;
431 uintptr_t *mdata = infl_req->mdata;
432 struct cnxk_ae_sess *sess;
433
434 sess = (struct cnxk_ae_sess *)
435 op->session->sess_private_data;
436
437 cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]);
438 }
439 } else {
440 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
441 plt_dp_info("HW completion code 0x%x", res->compcode);
442
443 switch (compcode) {
444 case CPT_COMP_INSTERR:
445 plt_dp_err("Request failed with instruction error");
446 break;
447 case CPT_COMP_FAULT:
448 plt_dp_err("Request failed with DMA fault");
449 break;
450 case CPT_COMP_HWERR:
451 plt_dp_err("Request failed with hardware error");
452 break;
453 default:
454 plt_dp_err(
455 "Request failed with unknown completion code");
456 }
457 }
458
459 temp_sess_free:
460 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
461 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
462 sym_session_clear(cn10k_cryptodev_driver_id,
463 cop->sym->session);
464 sz = rte_cryptodev_sym_get_existing_header_session_size(
465 cop->sym->session);
466 memset(cop->sym->session, 0, sz);
467 rte_mempool_put(qp->sess_mp, cop->sym->session);
468 cop->sym->session = NULL;
469 }
470 }
471 }
472
473 uintptr_t
cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1)474 cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1)
475 {
476 struct cpt_inflight_req *infl_req;
477 struct rte_crypto_op *cop;
478 struct cnxk_cpt_qp *qp;
479 union cpt_res_s res;
480
481 infl_req = (struct cpt_inflight_req *)(get_work1);
482 cop = infl_req->cop;
483 qp = infl_req->qp;
484
485 res.u64[0] = __atomic_load_n(&infl_req->res.u64[0], __ATOMIC_RELAXED);
486
487 cn10k_cpt_dequeue_post_process(qp, infl_req->cop, infl_req, &res.cn10k);
488
489 if (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))
490 rte_mempool_put(qp->meta_info.pool, infl_req->mdata);
491
492 rte_mempool_put(qp->ca.req_mp, infl_req);
493 return (uintptr_t)cop;
494 }
495
496 static uint16_t
cn10k_cpt_dequeue_burst(void * qptr,struct rte_crypto_op ** ops,uint16_t nb_ops)497 cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
498 {
499 struct cpt_inflight_req *infl_req;
500 struct cnxk_cpt_qp *qp = qptr;
501 struct pending_queue *pend_q;
502 uint64_t infl_cnt, pq_tail;
503 struct rte_crypto_op *cop;
504 union cpt_res_s res;
505 int i;
506
507 pend_q = &qp->pend_q;
508
509 const uint64_t pq_mask = pend_q->pq_mask;
510
511 pq_tail = pend_q->tail;
512 infl_cnt = pending_queue_infl_cnt(pend_q->head, pq_tail, pq_mask);
513 nb_ops = RTE_MIN(nb_ops, infl_cnt);
514
515 /* Ensure infl_cnt isn't read before data lands */
516 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
517
518 for (i = 0; i < nb_ops; i++) {
519 infl_req = &pend_q->req_queue[pq_tail];
520
521 res.u64[0] = __atomic_load_n(&infl_req->res.u64[0],
522 __ATOMIC_RELAXED);
523
524 if (unlikely(res.cn10k.compcode == CPT_COMP_NOT_DONE)) {
525 if (unlikely(rte_get_timer_cycles() >
526 pend_q->time_out)) {
527 plt_err("Request timed out");
528 cnxk_cpt_dump_on_err(qp);
529 pend_q->time_out = rte_get_timer_cycles() +
530 DEFAULT_COMMAND_TIMEOUT *
531 rte_get_timer_hz();
532 }
533 break;
534 }
535
536 pending_queue_advance(&pq_tail, pq_mask);
537
538 cop = infl_req->cop;
539
540 ops[i] = cop;
541
542 cn10k_cpt_dequeue_post_process(qp, cop, infl_req, &res.cn10k);
543
544 if (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))
545 rte_mempool_put(qp->meta_info.pool, infl_req->mdata);
546 }
547
548 pend_q->tail = pq_tail;
549
550 return i;
551 }
552
553 void
cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev * dev)554 cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
555 {
556 dev->enqueue_burst = cn10k_cpt_enqueue_burst;
557 dev->dequeue_burst = cn10k_cpt_dequeue_burst;
558
559 rte_mb();
560 }
561
562 static void
cn10k_cpt_dev_info_get(struct rte_cryptodev * dev,struct rte_cryptodev_info * info)563 cn10k_cpt_dev_info_get(struct rte_cryptodev *dev,
564 struct rte_cryptodev_info *info)
565 {
566 if (info != NULL) {
567 cnxk_cpt_dev_info_get(dev, info);
568 info->driver_id = cn10k_cryptodev_driver_id;
569 }
570 }
571
572 struct rte_cryptodev_ops cn10k_cpt_ops = {
573 /* Device control ops */
574 .dev_configure = cnxk_cpt_dev_config,
575 .dev_start = cnxk_cpt_dev_start,
576 .dev_stop = cnxk_cpt_dev_stop,
577 .dev_close = cnxk_cpt_dev_close,
578 .dev_infos_get = cn10k_cpt_dev_info_get,
579
580 .stats_get = NULL,
581 .stats_reset = NULL,
582 .queue_pair_setup = cnxk_cpt_queue_pair_setup,
583 .queue_pair_release = cnxk_cpt_queue_pair_release,
584
585 /* Symmetric crypto ops */
586 .sym_session_get_size = cnxk_cpt_sym_session_get_size,
587 .sym_session_configure = cnxk_cpt_sym_session_configure,
588 .sym_session_clear = cnxk_cpt_sym_session_clear,
589
590 /* Asymmetric crypto ops */
591 .asym_session_get_size = cnxk_ae_session_size_get,
592 .asym_session_configure = cnxk_ae_session_cfg,
593 .asym_session_clear = cnxk_ae_session_clear,
594
595 };
596