1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2015-2018 Intel Corporation 3 */ 4 #ifndef _ICP_QAT_HW_H_ 5 #define _ICP_QAT_HW_H_ 6 7 enum icp_qat_hw_ae_id { 8 ICP_QAT_HW_AE_0 = 0, 9 ICP_QAT_HW_AE_1 = 1, 10 ICP_QAT_HW_AE_2 = 2, 11 ICP_QAT_HW_AE_3 = 3, 12 ICP_QAT_HW_AE_4 = 4, 13 ICP_QAT_HW_AE_5 = 5, 14 ICP_QAT_HW_AE_6 = 6, 15 ICP_QAT_HW_AE_7 = 7, 16 ICP_QAT_HW_AE_8 = 8, 17 ICP_QAT_HW_AE_9 = 9, 18 ICP_QAT_HW_AE_10 = 10, 19 ICP_QAT_HW_AE_11 = 11, 20 ICP_QAT_HW_AE_DELIMITER = 12 21 }; 22 23 enum icp_qat_hw_qat_id { 24 ICP_QAT_HW_QAT_0 = 0, 25 ICP_QAT_HW_QAT_1 = 1, 26 ICP_QAT_HW_QAT_2 = 2, 27 ICP_QAT_HW_QAT_3 = 3, 28 ICP_QAT_HW_QAT_4 = 4, 29 ICP_QAT_HW_QAT_5 = 5, 30 ICP_QAT_HW_QAT_DELIMITER = 6 31 }; 32 33 enum icp_qat_hw_auth_algo { 34 ICP_QAT_HW_AUTH_ALGO_NULL = 0, 35 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, 36 ICP_QAT_HW_AUTH_ALGO_MD5 = 2, 37 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, 38 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, 39 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, 40 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, 41 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, 42 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, 43 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, 44 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, 45 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, 46 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, 47 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, 48 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14, 49 ICP_QAT_HW_AUTH_RESERVED_1 = 15, 50 ICP_QAT_HW_AUTH_RESERVED_2 = 16, 51 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, 52 ICP_QAT_HW_AUTH_RESERVED_3 = 18, 53 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, 54 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20 55 }; 56 57 enum icp_qat_hw_auth_mode { 58 ICP_QAT_HW_AUTH_MODE0 = 0, 59 ICP_QAT_HW_AUTH_MODE1 = 1, 60 ICP_QAT_HW_AUTH_MODE2 = 2, 61 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 62 }; 63 64 struct icp_qat_hw_auth_config { 65 uint32_t config; 66 uint32_t reserved; 67 }; 68 69 #define QAT_AUTH_MODE_BITPOS 4 70 #define QAT_AUTH_MODE_MASK 0xF 71 #define QAT_AUTH_ALGO_BITPOS 0 72 #define QAT_AUTH_ALGO_MASK 0xF 73 #define QAT_AUTH_CMP_BITPOS 8 74 #define QAT_AUTH_CMP_MASK 0x7F 75 #define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16 76 #define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1 77 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17 78 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1 79 #define QAT_AUTH_ALGO_SHA3_BITPOS 22 80 #define QAT_AUTH_ALGO_SHA3_MASK 0x3 81 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16 82 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF 83 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24 84 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF 85 #define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0 86 #define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1 87 #define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0 88 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0 89 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1 90 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0 91 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0 92 93 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 94 ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \ 95 (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \ 96 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \ 97 << QAT_AUTH_ALGO_SHA3_BITPOS) | \ 98 (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \ 99 QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \ 100 << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \ 101 (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \ 102 QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \ 103 << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \ 104 (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS)) 105 106 #define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \ 107 ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \ 108 QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \ 109 << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \ 110 (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \ 111 QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \ 112 << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS)) 113 114 struct icp_qat_hw_auth_counter { 115 uint32_t counter; 116 uint32_t reserved; 117 }; 118 119 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF 120 #define QAT_AUTH_COUNT_BITPOS 0 121 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \ 122 (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS) 123 124 struct icp_qat_hw_auth_setup { 125 struct icp_qat_hw_auth_config auth_config; 126 struct icp_qat_hw_auth_counter auth_counter; 127 }; 128 129 #define QAT_HW_DEFAULT_ALIGNMENT 8 130 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1))) 131 #define ICP_QAT_HW_NULL_STATE1_SZ 32 132 #define ICP_QAT_HW_MD5_STATE1_SZ 16 133 #define ICP_QAT_HW_SHA1_STATE1_SZ 20 134 #define ICP_QAT_HW_SHA224_STATE1_SZ 32 135 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28 136 #define ICP_QAT_HW_SHA256_STATE1_SZ 32 137 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 138 #define ICP_QAT_HW_SHA384_STATE1_SZ 64 139 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48 140 #define ICP_QAT_HW_SHA512_STATE1_SZ 64 141 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 142 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16 143 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16 144 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32 145 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16 146 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16 147 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 148 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 149 150 #define ICP_QAT_HW_NULL_STATE2_SZ 32 151 #define ICP_QAT_HW_MD5_STATE2_SZ 16 152 #define ICP_QAT_HW_SHA1_STATE2_SZ 20 153 #define ICP_QAT_HW_SHA224_STATE2_SZ 32 154 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0 155 #define ICP_QAT_HW_SHA256_STATE2_SZ 32 156 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0 157 #define ICP_QAT_HW_SHA384_STATE2_SZ 64 158 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0 159 #define ICP_QAT_HW_SHA512_STATE2_SZ 64 160 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0 161 #define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48 162 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 163 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 164 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16 165 #define ICP_QAT_HW_F9_IK_SZ 16 166 #define ICP_QAT_HW_F9_FK_SZ 16 167 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \ 168 ICP_QAT_HW_F9_FK_SZ) 169 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ 170 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24 171 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32 172 #define ICP_QAT_HW_GALOIS_H_SZ 16 173 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8 174 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 175 176 struct icp_qat_hw_auth_sha512 { 177 struct icp_qat_hw_auth_setup inner_setup; 178 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ]; 179 struct icp_qat_hw_auth_setup outer_setup; 180 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ]; 181 }; 182 183 struct icp_qat_hw_auth_sha3_512 { 184 struct icp_qat_hw_auth_setup inner_setup; 185 uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ]; 186 struct icp_qat_hw_auth_setup outer_setup; 187 }; 188 189 struct icp_qat_hw_auth_algo_blk { 190 struct icp_qat_hw_auth_sha512 sha; 191 }; 192 193 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 194 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF 195 196 enum icp_qat_hw_cipher_algo { 197 ICP_QAT_HW_CIPHER_ALGO_NULL = 0, 198 ICP_QAT_HW_CIPHER_ALGO_DES = 1, 199 ICP_QAT_HW_CIPHER_ALGO_3DES = 2, 200 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, 201 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, 202 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, 203 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, 204 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, 205 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, 206 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, 207 ICP_QAT_HW_CIPHER_ALGO_SM4 = 10, 208 ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 11, 209 ICP_QAT_HW_CIPHER_DELIMITER = 12 210 }; 211 212 enum icp_qat_hw_cipher_mode { 213 ICP_QAT_HW_CIPHER_ECB_MODE = 0, 214 ICP_QAT_HW_CIPHER_CBC_MODE = 1, 215 ICP_QAT_HW_CIPHER_CTR_MODE = 2, 216 ICP_QAT_HW_CIPHER_F8_MODE = 3, 217 ICP_QAT_HW_CIPHER_AEAD_MODE = 4, 218 ICP_QAT_HW_CIPHER_XTS_MODE = 6, 219 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 220 }; 221 222 struct icp_qat_hw_cipher_config { 223 uint32_t val; 224 uint32_t reserved; 225 }; 226 227 enum icp_qat_hw_cipher_dir { 228 ICP_QAT_HW_CIPHER_ENCRYPT = 0, 229 ICP_QAT_HW_CIPHER_DECRYPT = 1, 230 }; 231 232 enum icp_qat_hw_auth_op { 233 ICP_QAT_HW_AUTH_VERIFY = 0, 234 ICP_QAT_HW_AUTH_GENERATE = 1, 235 }; 236 237 enum icp_qat_hw_cipher_convert { 238 ICP_QAT_HW_CIPHER_NO_CONVERT = 0, 239 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1, 240 }; 241 242 #define QAT_CIPHER_MODE_BITPOS 4 243 #define QAT_CIPHER_MODE_MASK 0xF 244 #define QAT_CIPHER_ALGO_BITPOS 0 245 #define QAT_CIPHER_ALGO_MASK 0xF 246 #define QAT_CIPHER_CONVERT_BITPOS 9 247 #define QAT_CIPHER_CONVERT_MASK 0x1 248 #define QAT_CIPHER_DIR_BITPOS 8 249 #define QAT_CIPHER_DIR_MASK 0x1 250 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10 251 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F 252 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 253 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 254 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \ 255 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \ 256 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \ 257 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \ 258 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS)) 259 260 #define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24 261 #define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8 262 #define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF 263 #define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F 264 #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16 265 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \ 266 ({ \ 267 typeof(aad_size) aad_size1 = aad_size; \ 268 (((((aad_size1) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \ 269 QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) << \ 270 QAT_CIPHER_AEAD_AAD_SIZE_BITPOS) | \ 271 (((aad_size1) & QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK) << \ 272 QAT_CIPHER_AEAD_AAD_LOWER_SHIFT)); \ 273 }) 274 275 #define ICP_QAT_HW_DES_BLK_SZ 8 276 #define ICP_QAT_HW_3DES_BLK_SZ 8 277 #define ICP_QAT_HW_NULL_BLK_SZ 8 278 #define ICP_QAT_HW_AES_BLK_SZ 16 279 #define ICP_QAT_HW_KASUMI_BLK_SZ 8 280 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8 281 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8 282 #define ICP_QAT_HW_NULL_KEY_SZ 256 283 #define ICP_QAT_HW_DES_KEY_SZ 8 284 #define ICP_QAT_HW_3DES_KEY_SZ 24 285 #define ICP_QAT_HW_AES_128_KEY_SZ 16 286 #define ICP_QAT_HW_AES_192_KEY_SZ 24 287 #define ICP_QAT_HW_AES_256_KEY_SZ 32 288 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \ 289 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 290 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \ 291 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 292 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \ 293 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 294 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \ 295 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 296 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \ 297 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 298 #define ICP_QAT_HW_KASUMI_KEY_SZ 16 299 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \ 300 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 301 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \ 302 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 303 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \ 304 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 305 #define ICP_QAT_HW_ARC4_KEY_SZ 256 306 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16 307 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16 308 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16 309 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16 310 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2 311 #define ICP_QAT_HW_CHACHAPOLY_KEY_SZ 32 312 #define ICP_QAT_HW_CHACHAPOLY_IV_SZ 12 313 #define ICP_QAT_HW_CHACHAPOLY_BLK_SZ 64 314 #define ICP_QAT_HW_SPC_CTR_SZ 16 315 #define ICP_QAT_HW_CHACHAPOLY_ICV_SZ 16 316 #define ICP_QAT_HW_CHACHAPOLY_AAD_MAX_LOG 14 317 318 #define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ 319 320 /* These defines describe position of the bit-fields 321 * in the flags byte in B0 322 */ 323 #define ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT 6 324 #define ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT 3 325 326 #define ICP_QAT_HW_CCM_BUILD_B0_FLAGS(Adata, t, q) \ 327 ((((Adata) > 0 ? 1 : 0) << ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT) \ 328 | ((((t) - 2) >> 1) << ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT) \ 329 | ((q) - 1)) 330 331 #define ICP_QAT_HW_CCM_NQ_CONST 15 332 #define ICP_QAT_HW_CCM_AAD_B0_LEN 16 333 #define ICP_QAT_HW_CCM_AAD_LEN_INFO 2 334 #define ICP_QAT_HW_CCM_AAD_DATA_OFFSET (ICP_QAT_HW_CCM_AAD_B0_LEN + \ 335 ICP_QAT_HW_CCM_AAD_LEN_INFO) 336 #define ICP_QAT_HW_CCM_AAD_ALIGNMENT 16 337 #define ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE 4 338 #define ICP_QAT_HW_CCM_NONCE_OFFSET 1 339 340 struct icp_qat_hw_cipher_algo_blk { 341 struct icp_qat_hw_cipher_config cipher_config; 342 uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ]; 343 } __rte_cache_aligned; 344 345 /* ========================================================================= */ 346 /* COMPRESSION SLICE */ 347 /* ========================================================================= */ 348 349 enum icp_qat_hw_compression_direction { 350 ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0, 351 ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1, 352 ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2 353 }; 354 355 enum icp_qat_hw_compression_delayed_match { 356 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0, 357 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1, 358 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2 359 }; 360 361 enum icp_qat_hw_compression_algo { 362 ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0, 363 ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1, 364 ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2 365 }; 366 367 368 enum icp_qat_hw_compression_depth { 369 ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0, 370 ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1, 371 ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2, 372 ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3, 373 ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4 374 }; 375 376 enum icp_qat_hw_compression_file_type { 377 ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0, 378 ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1, 379 ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2, 380 ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3, 381 ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4, 382 ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5 383 }; 384 385 struct icp_qat_hw_compression_config { 386 uint32_t val; 387 uint32_t reserved; 388 }; 389 390 #define QAT_COMPRESSION_DIR_BITPOS 4 391 #define QAT_COMPRESSION_DIR_MASK 0x7 392 #define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16 393 #define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1 394 #define QAT_COMPRESSION_ALGO_BITPOS 31 395 #define QAT_COMPRESSION_ALGO_MASK 0x1 396 #define QAT_COMPRESSION_DEPTH_BITPOS 28 397 #define QAT_COMPRESSION_DEPTH_MASK 0x7 398 #define QAT_COMPRESSION_FILE_TYPE_BITPOS 24 399 #define QAT_COMPRESSION_FILE_TYPE_MASK 0xF 400 401 #define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \ 402 dir, delayed, algo, depth, filetype) \ 403 ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \ 404 (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \ 405 << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \ 406 (((algo) & QAT_COMPRESSION_ALGO_MASK) \ 407 << QAT_COMPRESSION_ALGO_BITPOS) | \ 408 (((depth) & QAT_COMPRESSION_DEPTH_MASK) \ 409 << QAT_COMPRESSION_DEPTH_BITPOS) | \ 410 (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \ 411 << QAT_COMPRESSION_FILE_TYPE_BITPOS)) 412 413 #endif 414