1 //===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the checking of insns inside a bundle according to the
10 // packet constraint rules of the Hexagon ISA.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/HexagonMCChecker.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
16 #include "MCTargetDesc/HexagonMCInstrInfo.h"
17 #include "MCTargetDesc/HexagonMCShuffler.h"
18 #include "MCTargetDesc/HexagonMCTargetDesc.h"
19 
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include <cassert>
29 
30 using namespace llvm;
31 
32 static cl::opt<bool>
33     RelaxNVChecks("relax-nv-checks", cl::Hidden,
34                   cl::desc("Relax checks of new-value validity"));
35 
36 const HexagonMCChecker::PredSense
37     HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
38 
init()39 void HexagonMCChecker::init() {
40   // Initialize read-only registers set.
41   ReadOnly.insert(Hexagon::PC);
42   ReadOnly.insert(Hexagon::C9_8);
43 
44   // Figure out the loop-registers definitions.
45   if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
46     Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
47     Defs[Hexagon::LC0].insert(Unconditional);
48   }
49   if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
50     Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
51     Defs[Hexagon::LC1].insert(Unconditional);
52   }
53 
54   if (HexagonMCInstrInfo::isBundle(MCB))
55     // Unfurl a bundle.
56     for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
57       MCInst const &Inst = *I.getInst();
58       if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
59         init(*Inst.getOperand(0).getInst());
60         init(*Inst.getOperand(1).getInst());
61       } else
62         init(Inst);
63     }
64   else
65     init(MCB);
66 }
67 
initReg(MCInst const & MCI,unsigned R,unsigned & PredReg,bool & isTrue)68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
69                                bool &isTrue) {
70   if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
71       HexagonMCInstrInfo::isPredReg(RI, R)) {
72     // Note an used predicate register.
73     PredReg = R;
74     isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
75 
76     // Note use of new predicate register.
77     if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
78       NewPreds.insert(PredReg);
79   } else
80     // Note register use.  Super-registers are not tracked directly,
81     // but their components.
82     for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
83          SRI.isValid(); ++SRI)
84       if (!MCSubRegIterator(*SRI, &RI).isValid())
85         // Skip super-registers used indirectly.
86         Uses.insert(*SRI);
87 
88   if (HexagonMCInstrInfo::IsReverseVecRegPair(R))
89     ReversePairs.insert(R);
90 }
91 
init(MCInst const & MCI)92 void HexagonMCChecker::init(MCInst const &MCI) {
93   const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
94   unsigned PredReg = Hexagon::NoRegister;
95   bool isTrue = false;
96 
97   // Get used registers.
98   for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
99     if (MCI.getOperand(i).isReg())
100       initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
101   for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i)
102     initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
103 
104   const bool IgnoreTmpDst = (HexagonMCInstrInfo::hasTmpDst(MCII, MCI) ||
105                              HexagonMCInstrInfo::hasHvxTmp(MCII, MCI)) &&
106                             STI.getFeatureBits()[Hexagon::ArchV69];
107 
108   // Get implicit register definitions.
109   if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
110     for (; *ImpDef; ++ImpDef) {
111       unsigned R = *ImpDef;
112 
113       if (Hexagon::R31 != R && MCID.isCall())
114         // Any register other than the LR and the PC are actually volatile ones
115         // as defined by the ABI, not modified implicitly by the call insn.
116         continue;
117       if (Hexagon::PC == R)
118         // Branches are the only insns that can change the PC,
119         // otherwise a read-only register.
120         continue;
121 
122       if (Hexagon::USR_OVF == R)
123         // Many insns change the USR implicitly, but only one or another flag.
124         // The instruction table models the USR.OVF flag, which can be
125         // implicitly modified more than once, but cannot be modified in the
126         // same packet with an instruction that modifies is explicitly. Deal
127         // with such situations individually.
128         SoftDefs.insert(R);
129       else if (HexagonMCInstrInfo::isPredReg(RI, R) &&
130                HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
131         // Include implicit late predicates.
132         LatePreds.insert(R);
133       else if (!IgnoreTmpDst)
134         Defs[R].insert(PredSense(PredReg, isTrue));
135     }
136 
137   // Figure out explicit register definitions.
138   for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
139     unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
140     // USR has subregisters (while C8 does not for technical reasons), so
141     // reset R to USR, since we know how to handle multiple defs of USR,
142     // taking into account its subregisters.
143     if (R == Hexagon::C8)
144       R = Hexagon::USR;
145 
146     if (HexagonMCInstrInfo::IsReverseVecRegPair(R))
147       ReversePairs.insert(R);
148 
149     // Note register definitions, direct ones as well as indirect side-effects.
150     // Super-registers are not tracked directly, but their components.
151     for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
152          SRI.isValid(); ++SRI) {
153       if (MCSubRegIterator(*SRI, &RI).isValid())
154         // Skip super-registers defined indirectly.
155         continue;
156 
157       if (R == *SRI) {
158         if (S == R)
159           // Avoid scoring the defined register multiple times.
160           continue;
161         else
162           // Note that the defined register has already been scored.
163           S = R;
164       }
165 
166       if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
167         // P3:0 is a special case, since multiple predicate register definitions
168         // in a packet is allowed as the equivalent of their logical "and".
169         // Only an explicit definition of P3:0 is noted as such; if a
170         // side-effect, then note as a soft definition.
171         SoftDefs.insert(*SRI);
172       else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) &&
173                HexagonMCInstrInfo::isPredReg(RI, *SRI))
174         // Some insns produce predicates too late to be used in the same packet.
175         LatePreds.insert(*SRI);
176       else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) ==
177                              HexagonII::TypeCVI_VM_TMP_LD)
178         // Temporary loads should be used in the same packet, but don't commit
179         // results, so it should be disregarded if another insn changes the same
180         // register.
181         // TODO: relies on the impossibility of a current and a temporary loads
182         // in the same packet.
183         TmpDefs.insert(*SRI);
184       else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI))
185         // vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
186         // destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
187         Uses.insert(*SRI);
188       else if (!IgnoreTmpDst)
189         Defs[*SRI].insert(PredSense(PredReg, isTrue));
190     }
191   }
192 
193   // Figure out definitions of new predicate registers.
194   if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
195     for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
196       if (MCI.getOperand(i).isReg()) {
197         unsigned P = MCI.getOperand(i).getReg();
198 
199         if (HexagonMCInstrInfo::isPredReg(RI, P))
200           NewPreds.insert(P);
201       }
202 }
203 
HexagonMCChecker(MCContext & Context,MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst & mcb,MCRegisterInfo const & ri,bool ReportErrors)204 HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
205                                    MCSubtargetInfo const &STI, MCInst &mcb,
206                                    MCRegisterInfo const &ri, bool ReportErrors)
207     : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),
208       ReportErrors(ReportErrors) {
209   init();
210 }
211 
HexagonMCChecker(HexagonMCChecker const & Other,MCSubtargetInfo const & STI,bool CopyReportErrors)212 HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,
213                                    MCSubtargetInfo const &STI,
214                                    bool CopyReportErrors)
215     : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),
216       STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {
217   init();
218 }
219 
check(bool FullCheck)220 bool HexagonMCChecker::check(bool FullCheck) {
221   bool chkP = checkPredicates();
222   bool chkNV = checkNewValues();
223   bool chkR = checkRegisters();
224   bool chkRRO = checkRegistersReadOnly();
225   checkRegisterCurDefs();
226   bool chkS = checkSolo();
227   bool chkSh = true;
228   if (FullCheck)
229     chkSh = checkShuffle();
230   bool chkSl = true;
231   if (FullCheck)
232     chkSl = checkSlots();
233   bool chkAXOK = checkAXOK();
234   bool chkCofMax1 = checkCOFMax1();
235   bool chkHWLoop = checkHWLoop();
236   bool chkValidTmpDst = FullCheck ? checkValidTmpDst() : true;
237   bool chkLegalVecRegPair = checkLegalVecRegPair();
238   bool ChkHVXAccum = checkHVXAccum();
239   bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl &&
240              chkAXOK && chkCofMax1 && chkHWLoop && chkValidTmpDst &&
241              chkLegalVecRegPair && ChkHVXAccum;
242 
243   return chk;
244 }
245 
isDuplexAGroup(unsigned Opcode)246 static bool isDuplexAGroup(unsigned Opcode) {
247   switch (Opcode) {
248   case Hexagon::SA1_addi:
249   case Hexagon::SA1_addrx:
250   case Hexagon::SA1_addsp:
251   case Hexagon::SA1_and1:
252   case Hexagon::SA1_clrf:
253   case Hexagon::SA1_clrfnew:
254   case Hexagon::SA1_clrt:
255   case Hexagon::SA1_clrtnew:
256   case Hexagon::SA1_cmpeqi:
257   case Hexagon::SA1_combine0i:
258   case Hexagon::SA1_combine1i:
259   case Hexagon::SA1_combine2i:
260   case Hexagon::SA1_combine3i:
261   case Hexagon::SA1_combinerz:
262   case Hexagon::SA1_combinezr:
263   case Hexagon::SA1_dec:
264   case Hexagon::SA1_inc:
265   case Hexagon::SA1_seti:
266   case Hexagon::SA1_setin1:
267   case Hexagon::SA1_sxtb:
268   case Hexagon::SA1_sxth:
269   case Hexagon::SA1_tfr:
270   case Hexagon::SA1_zxtb:
271   case Hexagon::SA1_zxth:
272     return true;
273     break;
274   default:
275     return false;
276   }
277 }
278 
isNeitherAnorX(MCInstrInfo const & MCII,MCInst const & ID)279 static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
280   if (HexagonMCInstrInfo::isFloat(MCII, ID))
281     return true;
282   unsigned Type = HexagonMCInstrInfo::getType(MCII, ID);
283   switch (Type) {
284   case HexagonII::TypeALU32_2op:
285   case HexagonII::TypeALU32_3op:
286   case HexagonII::TypeALU32_ADDI:
287   case HexagonII::TypeS_2op:
288   case HexagonII::TypeS_3op:
289   case HexagonII::TypeEXTENDER:
290   case HexagonII::TypeM:
291   case HexagonII::TypeALU64:
292     return false;
293   case HexagonII::TypeSUBINSN: {
294     return !isDuplexAGroup(ID.getOpcode());
295   }
296   case HexagonII::TypeDUPLEX:
297     llvm_unreachable("unexpected duplex instruction");
298   default:
299     return true;
300   }
301 }
302 
checkAXOK()303 bool HexagonMCChecker::checkAXOK() {
304   MCInst const *HasSoloAXInst = nullptr;
305   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
306     if (HexagonMCInstrInfo::isSoloAX(MCII, I)) {
307       HasSoloAXInst = &I;
308     }
309   }
310   if (!HasSoloAXInst)
311     return true;
312   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
313     if (&I != HasSoloAXInst && isNeitherAnorX(MCII, I)) {
314       reportError(
315           HasSoloAXInst->getLoc(),
316           Twine("Instruction can only be in a packet with ALU or non-FPU XTYPE "
317                 "instructions"));
318       reportError(I.getLoc(),
319                   Twine("Not an ALU or non-FPU XTYPE instruction"));
320       return false;
321     }
322   }
323   return true;
324 }
325 
reportBranchErrors()326 void HexagonMCChecker::reportBranchErrors() {
327   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
328     if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I))
329       reportNote(I.getLoc(), "Branching instruction");
330   }
331 }
332 
checkHWLoop()333 bool HexagonMCChecker::checkHWLoop() {
334   if (!HexagonMCInstrInfo::isInnerLoop(MCB) &&
335       !HexagonMCInstrInfo::isOuterLoop(MCB))
336     return true;
337   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
338     if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I)) {
339       reportError(MCB.getLoc(),
340                   "Branches cannot be in a packet with hardware loops");
341       reportBranchErrors();
342       return false;
343     }
344   }
345   return true;
346 }
347 
checkCOFMax1()348 bool HexagonMCChecker::checkCOFMax1() {
349   SmallVector<MCInst const *, 2> BranchLocations;
350   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
351     if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I))
352       BranchLocations.push_back(&I);
353   }
354   for (unsigned J = 0, N = BranchLocations.size(); J < N; ++J) {
355     MCInst const &I = *BranchLocations[J];
356     if (HexagonMCInstrInfo::isCofMax1(MCII, I)) {
357       bool Relax1 = HexagonMCInstrInfo::isCofRelax1(MCII, I);
358       bool Relax2 = HexagonMCInstrInfo::isCofRelax2(MCII, I);
359       if (N > 1 && !Relax1 && !Relax2) {
360         reportError(I.getLoc(),
361                     "Instruction may not be in a packet with other branches");
362         reportBranchErrors();
363         return false;
364       }
365       if (N > 1 && J == 0 && !Relax1) {
366         reportError(I.getLoc(),
367                     "Instruction may not be the first branch in packet");
368         reportBranchErrors();
369         return false;
370       }
371       if (N > 1 && J == 1 && !Relax2) {
372         reportError(I.getLoc(),
373                     "Instruction may not be the second branch in packet");
374         reportBranchErrors();
375         return false;
376       }
377     }
378   }
379   return true;
380 }
381 
checkSlots()382 bool HexagonMCChecker::checkSlots() {
383   if (HexagonMCInstrInfo::slotsConsumed(MCII, STI, MCB) >
384       HexagonMCInstrInfo::packetSizeSlots(STI)) {
385     reportError("invalid instruction packet: out of slots");
386     return false;
387   }
388   return true;
389 }
390 
391 // Check legal use of predicate registers.
checkPredicates()392 bool HexagonMCChecker::checkPredicates() {
393   // Check for proper use of new predicate registers.
394   for (const auto &I : NewPreds) {
395     unsigned P = I;
396 
397     if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) {
398       // Error out if the new predicate register is not defined,
399       // or defined "late"
400       // (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").
401       reportErrorNewValue(P);
402       return false;
403     }
404   }
405 
406   // Check for proper use of auto-anded of predicate registers.
407   for (const auto &I : LatePreds) {
408     unsigned P = I;
409 
410     if (LatePreds.count(P) > 1 || Defs.count(P)) {
411       // Error out if predicate register defined "late" multiple times or
412       // defined late and regularly defined
413       // (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".
414       reportErrorRegisters(P);
415       return false;
416     }
417   }
418 
419   return true;
420 }
421 
422 // Check legal use of new values.
checkNewValues()423 bool HexagonMCChecker::checkNewValues() {
424   for (auto const &ConsumerInst :
425        HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
426     if (!HexagonMCInstrInfo::isNewValue(MCII, ConsumerInst))
427       continue;
428 
429     const HexagonMCInstrInfo::PredicateInfo ConsumerPredInfo =
430         HexagonMCInstrInfo::predicateInfo(MCII, ConsumerInst);
431 
432     bool Branch = HexagonMCInstrInfo::getDesc(MCII, ConsumerInst).isBranch();
433     MCOperand const &Op =
434         HexagonMCInstrInfo::getNewValueOperand(MCII, ConsumerInst);
435     assert(Op.isReg());
436 
437     auto Producer = registerProducer(Op.getReg(), ConsumerPredInfo);
438     const MCInst *const ProducerInst = std::get<0>(Producer);
439     const HexagonMCInstrInfo::PredicateInfo ProducerPredInfo =
440         std::get<2>(Producer);
441 
442     if (ProducerInst == nullptr) {
443       reportError(ConsumerInst.getLoc(),
444                   "New value register consumer has no producer");
445       return false;
446     }
447     if (!RelaxNVChecks) {
448       // Checks that statically prove correct new value consumption
449       if (ProducerPredInfo.isPredicated() &&
450           (!ConsumerPredInfo.isPredicated() ||
451            llvm::HexagonMCInstrInfo::getType(MCII, ConsumerInst) ==
452                HexagonII::TypeNCJ)) {
453         reportNote(
454             ProducerInst->getLoc(),
455             "Register producer is predicated and consumer is unconditional");
456         reportError(ConsumerInst.getLoc(),
457                     "Instruction does not have a valid new register producer");
458         return false;
459       }
460       if (ProducerPredInfo.Register != Hexagon::NoRegister &&
461           ProducerPredInfo.Register != ConsumerPredInfo.Register) {
462         reportNote(ProducerInst->getLoc(),
463                    "Register producer does not use the same predicate "
464                    "register as the consumer");
465         reportError(ConsumerInst.getLoc(),
466                     "Instruction does not have a valid new register producer");
467         return false;
468       }
469     }
470     if (ProducerPredInfo.Register == ConsumerPredInfo.Register &&
471         ConsumerPredInfo.PredicatedTrue != ProducerPredInfo.PredicatedTrue) {
472       reportNote(
473           ProducerInst->getLoc(),
474           "Register producer has the opposite predicate sense as consumer");
475       reportError(ConsumerInst.getLoc(),
476                   "Instruction does not have a valid new register producer");
477       return false;
478     }
479 
480     MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst);
481     const unsigned ProducerOpIndex = std::get<1>(Producer);
482 
483     if (Desc.OpInfo[ProducerOpIndex].RegClass ==
484         Hexagon::DoubleRegsRegClassID) {
485       reportNote(ProducerInst->getLoc(),
486                  "Double registers cannot be new-value producers");
487       reportError(ConsumerInst.getLoc(),
488                   "Instruction does not have a valid new register producer");
489       return false;
490     }
491 
492     // The ProducerOpIsMemIndex logic checks for the index of the producer
493     // register operand.  Z-reg load instructions have an implicit operand
494     // that's not encoded, so the producer won't appear as the 1-th def, it
495     // will be at the 0-th.
496     const unsigned ProducerOpSearchIndex =
497         (HexagonMCInstrInfo::getType(MCII, *ProducerInst) ==
498          HexagonII::TypeCVI_ZW)
499             ? 0
500             : 1;
501 
502     const bool ProducerOpIsMemIndex =
503         ((Desc.mayLoad() && ProducerOpIndex == ProducerOpSearchIndex) ||
504          (Desc.mayStore() && ProducerOpIndex == 0));
505 
506     if (ProducerOpIsMemIndex) {
507       unsigned Mode = HexagonMCInstrInfo::getAddrMode(MCII, *ProducerInst);
508 
509       StringRef ModeError;
510       if (Mode == HexagonII::AbsoluteSet)
511         ModeError = "Absolute-set";
512       if (Mode == HexagonII::PostInc)
513         ModeError = "Auto-increment";
514       if (!ModeError.empty()) {
515         reportNote(ProducerInst->getLoc(),
516                    ModeError + " registers cannot be a new-value "
517                                "producer");
518         reportError(ConsumerInst.getLoc(),
519                     "Instruction does not have a valid new register producer");
520         return false;
521       }
522     }
523     if (Branch && HexagonMCInstrInfo::isFloat(MCII, *ProducerInst)) {
524       reportNote(ProducerInst->getLoc(),
525                  "FPU instructions cannot be new-value producers for jumps");
526       reportError(ConsumerInst.getLoc(),
527                   "Instruction does not have a valid new register producer");
528       return false;
529     }
530   }
531   return true;
532 }
533 
checkRegistersReadOnly()534 bool HexagonMCChecker::checkRegistersReadOnly() {
535   for (auto I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
536     MCInst const &Inst = *I.getInst();
537     unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
538     for (unsigned j = 0; j < Defs; ++j) {
539       MCOperand const &Operand = Inst.getOperand(j);
540       assert(Operand.isReg() && "Def is not a register");
541       unsigned Register = Operand.getReg();
542       if (ReadOnly.find(Register) != ReadOnly.end()) {
543         reportError(Inst.getLoc(), "Cannot write to read-only register `" +
544                                        Twine(RI.getName(Register)) + "'");
545         return false;
546       }
547     }
548   }
549   return true;
550 }
551 
registerUsed(unsigned Register)552 bool HexagonMCChecker::registerUsed(unsigned Register) {
553   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
554     for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
555                   n = I.getNumOperands();
556          j < n; ++j) {
557       MCOperand const &Operand = I.getOperand(j);
558       if (Operand.isReg() && Operand.getReg() == Register)
559         return true;
560     }
561   return false;
562 }
563 
564 std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
registerProducer(unsigned Register,HexagonMCInstrInfo::PredicateInfo ConsumerPredicate)565 HexagonMCChecker::registerProducer(
566     unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
567   std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
568       WrongSense;
569 
570   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
571     MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
572     auto ProducerPredicate = HexagonMCInstrInfo::predicateInfo(MCII, I);
573 
574     for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J)
575       for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true);
576            K.isValid(); ++K)
577         if (*K == Register) {
578           if (RelaxNVChecks ||
579               (ProducerPredicate.Register == ConsumerPredicate.Register &&
580                (ProducerPredicate.Register == Hexagon::NoRegister ||
581                 ProducerPredicate.PredicatedTrue ==
582                     ConsumerPredicate.PredicatedTrue)))
583             return std::make_tuple(&I, J, ProducerPredicate);
584           std::get<0>(WrongSense) = &I;
585           std::get<1>(WrongSense) = J;
586           std::get<2>(WrongSense) = ProducerPredicate;
587         }
588     if (Register == Hexagon::VTMP && HexagonMCInstrInfo::hasTmpDst(MCII, I))
589       return std::make_tuple(&I, 0, HexagonMCInstrInfo::PredicateInfo());
590   }
591   return WrongSense;
592 }
593 
checkRegisterCurDefs()594 void HexagonMCChecker::checkRegisterCurDefs() {
595   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
596     if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
597         HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) {
598       const unsigned RegDef = I.getOperand(0).getReg();
599 
600       bool HasRegDefUse = false;
601       for (MCRegAliasIterator Alias(RegDef, &RI, true); Alias.isValid();
602            ++Alias)
603         HasRegDefUse = HasRegDefUse || registerUsed(*Alias);
604 
605       if (!HasRegDefUse)
606         reportWarning("Register `" + Twine(RI.getName(RegDef)) +
607                       "' used with `.cur' "
608                       "but not used in the same packet");
609     }
610   }
611 }
612 
613 // Check for legal register uses and definitions.
checkRegisters()614 bool HexagonMCChecker::checkRegisters() {
615   // Check for proper register definitions.
616   for (const auto &I : Defs) {
617     unsigned R = I.first;
618 
619     if (isLoopRegister(R) && Defs.count(R) > 1 &&
620         (HexagonMCInstrInfo::isInnerLoop(MCB) ||
621          HexagonMCInstrInfo::isOuterLoop(MCB))) {
622       // Error out for definitions of loop registers at the end of a loop.
623       reportError("loop-setup and some branch instructions "
624                   "cannot be in the same packet");
625       return false;
626     }
627     if (SoftDefs.count(R)) {
628       // Error out for explicit changes to registers also weakly defined
629       // (e.g., "{ usr = r0; r0 = sfadd(...) }").
630       unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
631       unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
632       reportErrorRegisters(BadR);
633       return false;
634     }
635     if (!HexagonMCInstrInfo::isPredReg(RI, R) && Defs[R].size() > 1) {
636       // Check for multiple register definitions.
637       PredSet &PM = Defs[R];
638 
639       // Check for multiple unconditional register definitions.
640       if (PM.count(Unconditional)) {
641         // Error out on an unconditional change when there are any other
642         // changes, conditional or not.
643         unsigned UsrR = Hexagon::USR;
644         unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
645         reportErrorRegisters(BadR);
646         return false;
647       }
648       // Check for multiple conditional register definitions.
649       for (const auto &J : PM) {
650         PredSense P = J;
651 
652         // Check for multiple uses of the same condition.
653         if (PM.count(P) > 1) {
654           // Error out on conditional changes based on the same predicate
655           // (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").
656           reportErrorRegisters(R);
657           return false;
658         }
659         // Check for the use of the complementary condition.
660         P.second = !P.second;
661         if (PM.count(P) && PM.size() > 2) {
662           // Error out on conditional changes based on the same predicate
663           // multiple times
664           // (e.g., "if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =...").
665           reportErrorRegisters(R);
666           return false;
667         }
668       }
669     }
670   }
671 
672   // Check for use of temporary definitions.
673   for (const auto &I : TmpDefs) {
674     unsigned R = I;
675 
676     if (!Uses.count(R)) {
677       // special case for vhist
678       bool vHistFound = false;
679       for (auto const &HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
680         if (HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) ==
681             HexagonII::TypeCVI_HIST) {
682           vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
683           break;
684         }
685       }
686       // Warn on an unused temporary definition.
687       if (!vHistFound) {
688         reportWarning("register `" + Twine(RI.getName(R)) +
689                       "' used with `.tmp' but not used in the same packet");
690         return true;
691       }
692     }
693   }
694 
695   return true;
696 }
697 
698 // Check for legal use of solo insns.
checkSolo()699 bool HexagonMCChecker::checkSolo() {
700   if (HexagonMCInstrInfo::bundleSize(MCB) > 1)
701     for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
702       if (HexagonMCInstrInfo::isSolo(MCII, I)) {
703         reportError(I.getLoc(), "Instruction is marked `isSolo' and "
704                                 "cannot have other instructions in "
705                                 "the same packet");
706         return false;
707       }
708     }
709 
710   return true;
711 }
712 
checkShuffle()713 bool HexagonMCChecker::checkShuffle() {
714   HexagonMCShuffler MCSDX(Context, ReportErrors, MCII, STI, MCB);
715   return MCSDX.check();
716 }
717 
checkValidTmpDst()718 bool HexagonMCChecker::checkValidTmpDst() {
719   if (!STI.getFeatureBits()[Hexagon::ArchV69]) {
720     return true;
721   }
722   auto HasTmp = [&](MCInst const &I) {
723     return HexagonMCInstrInfo::hasTmpDst(MCII, I) ||
724            HexagonMCInstrInfo::hasHvxTmp(MCII, I);
725   };
726   unsigned HasTmpCount =
727       llvm::count_if(HexagonMCInstrInfo::bundleInstructions(MCII, MCB), HasTmp);
728 
729   if (HasTmpCount > 1) {
730     reportError(
731         MCB.getLoc(),
732         "this packet has more than one HVX vtmp/.tmp destination instruction");
733 
734     for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
735       if (HasTmp(I))
736         reportNote(I.getLoc(),
737                    "this is an HVX vtmp/.tmp destination instruction");
738 
739     return false;
740   }
741   return true;
742 }
743 
compoundRegisterMap(unsigned & Register)744 void HexagonMCChecker::compoundRegisterMap(unsigned &Register) {
745   switch (Register) {
746   default:
747     break;
748   case Hexagon::R15:
749     Register = Hexagon::R23;
750     break;
751   case Hexagon::R14:
752     Register = Hexagon::R22;
753     break;
754   case Hexagon::R13:
755     Register = Hexagon::R21;
756     break;
757   case Hexagon::R12:
758     Register = Hexagon::R20;
759     break;
760   case Hexagon::R11:
761     Register = Hexagon::R19;
762     break;
763   case Hexagon::R10:
764     Register = Hexagon::R18;
765     break;
766   case Hexagon::R9:
767     Register = Hexagon::R17;
768     break;
769   case Hexagon::R8:
770     Register = Hexagon::R16;
771     break;
772   }
773 }
774 
reportErrorRegisters(unsigned Register)775 void HexagonMCChecker::reportErrorRegisters(unsigned Register) {
776   reportError("register `" + Twine(RI.getName(Register)) +
777               "' modified more than once");
778 }
779 
reportErrorNewValue(unsigned Register)780 void HexagonMCChecker::reportErrorNewValue(unsigned Register) {
781   reportError("register `" + Twine(RI.getName(Register)) +
782               "' used with `.new' "
783               "but not validly modified in the same packet");
784 }
785 
reportError(Twine const & Msg)786 void HexagonMCChecker::reportError(Twine const &Msg) {
787   reportError(MCB.getLoc(), Msg);
788 }
789 
reportError(SMLoc Loc,Twine const & Msg)790 void HexagonMCChecker::reportError(SMLoc Loc, Twine const &Msg) {
791   if (ReportErrors)
792     Context.reportError(Loc, Msg);
793 }
794 
reportNote(SMLoc Loc,llvm::Twine const & Msg)795 void HexagonMCChecker::reportNote(SMLoc Loc, llvm::Twine const &Msg) {
796   if (ReportErrors) {
797     auto SM = Context.getSourceManager();
798     if (SM)
799       SM->PrintMessage(Loc, SourceMgr::DK_Note, Msg);
800   }
801 }
802 
reportWarning(Twine const & Msg)803 void HexagonMCChecker::reportWarning(Twine const &Msg) {
804   if (ReportErrors)
805     Context.reportWarning(MCB.getLoc(), Msg);
806 }
807 
checkLegalVecRegPair()808 bool HexagonMCChecker::checkLegalVecRegPair() {
809   const bool IsPermitted = STI.getFeatureBits()[Hexagon::ArchV67];
810   const bool HasReversePairs = ReversePairs.size() != 0;
811 
812   if (!IsPermitted && HasReversePairs) {
813     for (auto R : ReversePairs)
814       reportError("register pair `" + Twine(RI.getName(R)) +
815                   "' is not permitted for this architecture");
816     return false;
817   }
818   return true;
819 }
820 
821 // Vd.tmp can't be accumulated
checkHVXAccum()822 bool HexagonMCChecker::checkHVXAccum()
823 {
824   for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
825     bool IsTarget =
826         HexagonMCInstrInfo::isAccumulator(MCII, I) && I.getOperand(0).isReg();
827     if (!IsTarget)
828       continue;
829     unsigned int R = I.getOperand(0).getReg();
830     TmpDefsIterator It = TmpDefs.find(R);
831     if (It != TmpDefs.end()) {
832       reportError("register `" + Twine(RI.getName(R)) + ".tmp" +
833                   "' is accumulated in this packet");
834       return false;
835     }
836   }
837   return true;
838 }
839