1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=4 -mvscale-max=4 -fallow-half-arguments-and-returns -S -O1 -emit-llvm -o - %s | FileCheck %s
3 
4 // REQUIRES: aarch64-registered-target
5 
6 #include <arm_sve.h>
7 
8 #define N __ARM_FEATURE_SVE_BITS
9 
10 typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
11 typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
12 typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
13 
14 //===----------------------------------------------------------------------===//
15 // Test caller/callee with VLST <-> VLAT
16 //===----------------------------------------------------------------------===//
17 
18 // CHECK-LABEL: @sizeless_callee(
19 // CHECK-NEXT:  entry:
20 // CHECK-NEXT:    ret <vscale x 4 x i32> [[X:%.*]]
21 //
sizeless_callee(svint32_t x)22 svint32_t sizeless_callee(svint32_t x) {
23   return x;
24 }
25 
26 // CHECK-LABEL: @fixed_caller(
27 // CHECK-NEXT:  entry:
28 // CHECK-NEXT:    ret <vscale x 4 x i32> [[X_COERCE:%.*]]
29 //
fixed_caller(fixed_int32_t x)30 fixed_int32_t fixed_caller(fixed_int32_t x) {
31   return sizeless_callee(x);
32 }
33 
34 // CHECK-LABEL: @fixed_callee(
35 // CHECK-NEXT:  entry:
36 // CHECK-NEXT:    ret <vscale x 4 x i32> [[X_COERCE:%.*]]
37 //
fixed_callee(fixed_int32_t x)38 fixed_int32_t fixed_callee(fixed_int32_t x) {
39   return x;
40 }
41 
42 // CHECK-LABEL: @sizeless_caller(
43 // CHECK-NEXT:  entry:
44 // CHECK-NEXT:    [[COERCE1:%.*]] = alloca <16 x i32>, align 16
45 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i32>* [[COERCE1]] to <vscale x 4 x i32>*
46 // CHECK-NEXT:    store <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32>* [[TMP0]], align 16
47 // CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[COERCE1]], align 16, !tbaa [[TBAA6:![0-9]+]]
48 // CHECK-NEXT:    [[CASTSCALABLESVE2:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP1]], i64 0)
49 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CASTSCALABLESVE2]]
50 //
sizeless_caller(svint32_t x)51 svint32_t sizeless_caller(svint32_t x) {
52   return fixed_callee(x);
53 }
54 
55 //===----------------------------------------------------------------------===//
56 // fixed, fixed
57 //===----------------------------------------------------------------------===//
58 
59 // CHECK-LABEL: @call_int32_ff(
60 // CHECK-NEXT:  entry:
61 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
62 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1_COERCE:%.*]], <vscale x 4 x i32> [[OP2_COERCE:%.*]]
63 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
64 //
call_int32_ff(svbool_t pg,fixed_int32_t op1,fixed_int32_t op2)65 fixed_int32_t call_int32_ff(svbool_t pg, fixed_int32_t op1, fixed_int32_t op2) {
66   return svsel(pg, op1, op2);
67 }
68 
69 // CHECK-LABEL: @call_float64_ff(
70 // CHECK-NEXT:  entry:
71 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
72 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1_COERCE:%.*]], <vscale x 2 x double> [[OP2_COERCE:%.*]]
73 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
74 //
call_float64_ff(svbool_t pg,fixed_float64_t op1,fixed_float64_t op2)75 fixed_float64_t call_float64_ff(svbool_t pg, fixed_float64_t op1, fixed_float64_t op2) {
76   return svsel(pg, op1, op2);
77 }
78 
79 // CHECK-LABEL: @call_bool_ff(
80 // CHECK-NEXT:  entry:
81 // CHECK-NEXT:    [[TMP2:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[TMP1:%.*]]
82 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP2]]
83 //
call_bool_ff(svbool_t pg,fixed_bool_t op1,fixed_bool_t op2)84 fixed_bool_t call_bool_ff(svbool_t pg, fixed_bool_t op1, fixed_bool_t op2) {
85   return svsel(pg, op1, op2);
86 }
87 
88 //===----------------------------------------------------------------------===//
89 // fixed, scalable
90 //===----------------------------------------------------------------------===//
91 
92 // CHECK-LABEL: @call_int32_fs(
93 // CHECK-NEXT:  entry:
94 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
95 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1_COERCE:%.*]], <vscale x 4 x i32> [[OP2:%.*]]
96 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
97 //
call_int32_fs(svbool_t pg,fixed_int32_t op1,svint32_t op2)98 fixed_int32_t call_int32_fs(svbool_t pg, fixed_int32_t op1, svint32_t op2) {
99   return svsel(pg, op1, op2);
100 }
101 
102 // CHECK-LABEL: @call_float64_fs(
103 // CHECK-NEXT:  entry:
104 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
105 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1_COERCE:%.*]], <vscale x 2 x double> [[OP2:%.*]]
106 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
107 //
call_float64_fs(svbool_t pg,fixed_float64_t op1,svfloat64_t op2)108 fixed_float64_t call_float64_fs(svbool_t pg, fixed_float64_t op1, svfloat64_t op2) {
109   return svsel(pg, op1, op2);
110 }
111 
112 // CHECK-LABEL: @call_bool_fs(
113 // CHECK-NEXT:  entry:
114 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[OP2:%.*]]
115 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
116 //
call_bool_fs(svbool_t pg,fixed_bool_t op1,svbool_t op2)117 fixed_bool_t call_bool_fs(svbool_t pg, fixed_bool_t op1, svbool_t op2) {
118   return svsel(pg, op1, op2);
119 }
120 
121 //===----------------------------------------------------------------------===//
122 // scalable, scalable
123 //===----------------------------------------------------------------------===//
124 
125 // CHECK-LABEL: @call_int32_ss(
126 // CHECK-NEXT:  entry:
127 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
128 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]
129 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
130 //
call_int32_ss(svbool_t pg,svint32_t op1,svint32_t op2)131 fixed_int32_t call_int32_ss(svbool_t pg, svint32_t op1, svint32_t op2) {
132   return svsel(pg, op1, op2);
133 }
134 
135 // CHECK-LABEL: @call_float64_ss(
136 // CHECK-NEXT:  entry:
137 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
138 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]]
139 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
140 //
call_float64_ss(svbool_t pg,svfloat64_t op1,svfloat64_t op2)141 fixed_float64_t call_float64_ss(svbool_t pg, svfloat64_t op1, svfloat64_t op2) {
142   return svsel(pg, op1, op2);
143 }
144 
145 // CHECK-LABEL: @call_bool_ss(
146 // CHECK-NEXT:  entry:
147 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]]
148 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
149 //
call_bool_ss(svbool_t pg,svbool_t op1,svbool_t op2)150 fixed_bool_t call_bool_ss(svbool_t pg, svbool_t op1, svbool_t op2) {
151   return svsel(pg, op1, op2);
152 }
153