1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2020 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef ULP_TEMPLATE_DB_H_ 7 #define ULP_TEMPLATE_DB_H_ 8 9 #define BNXT_ULP_REGFILE_MAX_SZ 19 10 #define BNXT_ULP_MAX_NUM_DEVICES 4 11 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 12 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4 13 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048 14 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 217 15 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919 16 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 17 #define BNXT_ULP_CLASS_HID_SHFTR 32 18 #define BNXT_ULP_CLASS_HID_SHFTL 31 19 #define BNXT_ULP_CLASS_HID_MASK 2047 20 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 4096 21 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 83 22 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 23 #define BNXT_ULP_ACT_HID_HIGH_PRIME 4721 24 #define BNXT_ULP_ACT_HID_SHFTR 23 25 #define BNXT_ULP_ACT_HID_SHFTL 23 26 #define BNXT_ULP_ACT_HID_MASK 4095 27 #define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2 28 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 29 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 30 31 enum bnxt_ulp_action_bit { 32 BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001, 33 BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002, 34 BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004, 35 BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008, 36 BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010, 37 BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000020, 38 BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000040, 39 BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000080, 40 BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000100, 41 BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000000200, 42 BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000000400, 43 BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000000800, 44 BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000001000, 45 BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000002000, 46 BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000004000, 47 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000008000, 48 BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000010000, 49 BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000020000, 50 BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000040000, 51 BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000080000, 52 BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000100000, 53 BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000000200000, 54 BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000000400000, 55 BNXT_ULP_ACTION_BIT_JUMP = 0x0000000000800000, 56 BNXT_ULP_ACTION_BIT_LAST = 0x0000000001000000 57 }; 58 59 enum bnxt_ulp_hdr_bit { 60 BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001, 61 BNXT_ULP_HDR_BIT_OO_VLAN = 0x0000000000000002, 62 BNXT_ULP_HDR_BIT_OI_VLAN = 0x0000000000000004, 63 BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000008, 64 BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000010, 65 BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000020, 66 BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000040, 67 BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000080, 68 BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000100, 69 BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000200, 70 BNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000000400, 71 BNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000000800, 72 BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000001000, 73 BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000002000, 74 BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000004000, 75 BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000008000, 76 BNXT_ULP_HDR_BIT_F1 = 0x0000000000010000, 77 BNXT_ULP_HDR_BIT_LAST = 0x0000000000020000 78 }; 79 80 enum bnxt_ulp_act_type { 81 BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0, 82 BNXT_ULP_ACT_TYPE_SUPPORTED = 1, 83 BNXT_ULP_ACT_TYPE_END = 2, 84 BNXT_ULP_ACT_TYPE_LAST = 3 85 }; 86 87 enum bnxt_ulp_byte_order { 88 BNXT_ULP_BYTE_ORDER_BE = 0, 89 BNXT_ULP_BYTE_ORDER_LE = 1, 90 BNXT_ULP_BYTE_ORDER_LAST = 2 91 }; 92 93 enum bnxt_ulp_cf_idx { 94 BNXT_ULP_CF_IDX_NOT_USED = 0, 95 BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1, 96 BNXT_ULP_CF_IDX_O_VTAG_NUM = 2, 97 BNXT_ULP_CF_IDX_O_NO_VTAG = 3, 98 BNXT_ULP_CF_IDX_O_ONE_VTAG = 4, 99 BNXT_ULP_CF_IDX_O_TWO_VTAGS = 5, 100 BNXT_ULP_CF_IDX_I_VTAG_NUM = 6, 101 BNXT_ULP_CF_IDX_I_NO_VTAG = 7, 102 BNXT_ULP_CF_IDX_I_ONE_VTAG = 8, 103 BNXT_ULP_CF_IDX_I_TWO_VTAGS = 9, 104 BNXT_ULP_CF_IDX_INCOMING_IF = 10, 105 BNXT_ULP_CF_IDX_DIRECTION = 11, 106 BNXT_ULP_CF_IDX_SVIF_FLAG = 12, 107 BNXT_ULP_CF_IDX_O_L3 = 13, 108 BNXT_ULP_CF_IDX_I_L3 = 14, 109 BNXT_ULP_CF_IDX_O_L4 = 15, 110 BNXT_ULP_CF_IDX_I_L4 = 16, 111 BNXT_ULP_CF_IDX_DEV_PORT_ID = 17, 112 BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 18, 113 BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 19, 114 BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 20, 115 BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 21, 116 BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 22, 117 BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 23, 118 BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 24, 119 BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 25, 120 BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 26, 121 BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 27, 122 BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 28, 123 BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 29, 124 BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 30, 125 BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 31, 126 BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 32, 127 BNXT_ULP_CF_IDX_ACT_DEC_TTL = 33, 128 BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 34, 129 BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 35, 130 BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 36, 131 BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 37, 132 BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 38, 133 BNXT_ULP_CF_IDX_VF_TO_VF = 39, 134 BNXT_ULP_CF_IDX_L3_HDR_CNT = 40, 135 BNXT_ULP_CF_IDX_L4_HDR_CNT = 41, 136 BNXT_ULP_CF_IDX_VFR_MODE = 42, 137 BNXT_ULP_CF_IDX_LOOPBACK_PARIF = 43, 138 BNXT_ULP_CF_IDX_L3_TUN = 44, 139 BNXT_ULP_CF_IDX_L3_TUN_DECAP = 45, 140 BNXT_ULP_CF_IDX_LAST = 46 141 }; 142 143 enum bnxt_ulp_cond_opcode { 144 BNXT_ULP_COND_OPCODE_NOP = 0, 145 BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET = 1, 146 BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET = 2, 147 BNXT_ULP_COND_OPCODE_HDR_BIT_IS_SET = 3, 148 BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET = 4, 149 BNXT_ULP_COND_OPCODE_ACTION_BIT_NOT_SET = 5, 150 BNXT_ULP_COND_OPCODE_HDR_BIT_NOT_SET = 6, 151 BNXT_ULP_COND_OPCODE_LAST = 7 152 }; 153 154 enum bnxt_ulp_critical_resource { 155 BNXT_ULP_CRITICAL_RESOURCE_NO = 0, 156 BNXT_ULP_CRITICAL_RESOURCE_YES = 1, 157 BNXT_ULP_CRITICAL_RESOURCE_LAST = 2 158 }; 159 160 enum bnxt_ulp_device_id { 161 BNXT_ULP_DEVICE_ID_WH_PLUS = 0, 162 BNXT_ULP_DEVICE_ID_THOR = 1, 163 BNXT_ULP_DEVICE_ID_STINGRAY = 2, 164 BNXT_ULP_DEVICE_ID_STINGRAY2 = 3, 165 BNXT_ULP_DEVICE_ID_LAST = 4 166 }; 167 168 enum bnxt_ulp_df_param_type { 169 BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID = 0, 170 BNXT_ULP_DF_PARAM_TYPE_LAST = 1 171 }; 172 173 enum bnxt_ulp_direction { 174 BNXT_ULP_DIRECTION_INGRESS = 0, 175 BNXT_ULP_DIRECTION_EGRESS = 1, 176 BNXT_ULP_DIRECTION_LAST = 2 177 }; 178 179 enum bnxt_ulp_flow_mem_type { 180 BNXT_ULP_FLOW_MEM_TYPE_INT = 0, 181 BNXT_ULP_FLOW_MEM_TYPE_EXT = 1, 182 BNXT_ULP_FLOW_MEM_TYPE_BOTH = 2, 183 BNXT_ULP_FLOW_MEM_TYPE_LAST = 3 184 }; 185 186 enum bnxt_ulp_glb_regfile_index { 187 BNXT_ULP_GLB_REGFILE_INDEX_NOT_USED = 0, 188 BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 1, 189 BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR = 2, 190 BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID = 3, 191 BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID = 4, 192 BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR = 5, 193 BNXT_ULP_GLB_REGFILE_INDEX_LAST = 6 194 }; 195 196 enum bnxt_ulp_hdr_type { 197 BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0, 198 BNXT_ULP_HDR_TYPE_SUPPORTED = 1, 199 BNXT_ULP_HDR_TYPE_END = 2, 200 BNXT_ULP_HDR_TYPE_LAST = 3 201 }; 202 203 enum bnxt_ulp_index_opcode { 204 BNXT_ULP_INDEX_OPCODE_NOT_USED = 0, 205 BNXT_ULP_INDEX_OPCODE_ALLOCATE = 1, 206 BNXT_ULP_INDEX_OPCODE_GLOBAL = 2, 207 BNXT_ULP_INDEX_OPCODE_COMP_FIELD = 3, 208 BNXT_ULP_INDEX_OPCODE_CONSTANT = 4, 209 BNXT_ULP_INDEX_OPCODE_LAST = 5 210 }; 211 212 enum bnxt_ulp_mapper_opc { 213 BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT = 0, 214 BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD = 1, 215 BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD = 2, 216 BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE = 3, 217 BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE = 4, 218 BNXT_ULP_MAPPER_OPC_SET_TO_ZERO = 5, 219 BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT = 6, 220 BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP = 7, 221 BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8, 222 BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9, 223 BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10, 224 BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11, 225 BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12, 226 BNXT_ULP_MAPPER_OPC_LAST = 13 227 }; 228 229 enum bnxt_ulp_mark_db_opcode { 230 BNXT_ULP_MARK_DB_OPCODE_NOP = 0, 231 BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION = 1, 232 BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG = 2, 233 BNXT_ULP_MARK_DB_OPCODE_LAST = 3 234 }; 235 236 enum bnxt_ulp_match_type { 237 BNXT_ULP_MATCH_TYPE_EM = 0, 238 BNXT_ULP_MATCH_TYPE_WM = 1, 239 BNXT_ULP_MATCH_TYPE_LAST = 2 240 }; 241 242 enum bnxt_ulp_mem_type_opcode { 243 BNXT_ULP_MEM_TYPE_OPCODE_NOP = 0, 244 BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT = 1, 245 BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT = 2, 246 BNXT_ULP_MEM_TYPE_OPCODE_LAST = 3 247 }; 248 249 enum bnxt_ulp_priority { 250 BNXT_ULP_PRIORITY_LEVEL_0 = 0, 251 BNXT_ULP_PRIORITY_LEVEL_1 = 1, 252 BNXT_ULP_PRIORITY_LEVEL_2 = 2, 253 BNXT_ULP_PRIORITY_LEVEL_3 = 3, 254 BNXT_ULP_PRIORITY_LEVEL_4 = 4, 255 BNXT_ULP_PRIORITY_LEVEL_5 = 5, 256 BNXT_ULP_PRIORITY_LEVEL_6 = 6, 257 BNXT_ULP_PRIORITY_LEVEL_7 = 7, 258 BNXT_ULP_PRIORITY_NOT_USED = 8, 259 BNXT_ULP_PRIORITY_LAST = 9 260 }; 261 262 enum bnxt_ulp_regfile_index { 263 BNXT_ULP_REGFILE_INDEX_NOT_USED = 0, 264 BNXT_ULP_REGFILE_INDEX_CLASS_TID = 1, 265 BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 2, 266 BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 3, 267 BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 4, 268 BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 5, 269 BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 6, 270 BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 7, 271 BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 8, 272 BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 9, 273 BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 10, 274 BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 11, 275 BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 12, 276 BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 13, 277 BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 14, 278 BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 15, 279 BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 16, 280 BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 = 17, 281 BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 = 18, 282 BNXT_ULP_REGFILE_INDEX_LAST = 19 283 }; 284 285 enum bnxt_ulp_search_before_alloc { 286 BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0, 287 BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP = 1, 288 BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE = 2, 289 BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 3 290 }; 291 292 enum bnxt_ulp_template_type { 293 BNXT_ULP_TEMPLATE_TYPE_CLASS = 0, 294 BNXT_ULP_TEMPLATE_TYPE_ACTION = 1, 295 BNXT_ULP_TEMPLATE_TYPE_LAST = 2 296 }; 297 298 enum bnxt_ulp_fdb_resource_flags { 299 BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00, 300 BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01 301 }; 302 303 enum bnxt_ulp_fdb_type { 304 BNXT_ULP_FDB_TYPE_REGULAR = 0, 305 BNXT_ULP_FDB_TYPE_DEFAULT = 1 306 }; 307 308 enum bnxt_ulp_flow_dir_bitmask { 309 BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000, 310 BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000 311 }; 312 313 enum bnxt_ulp_match_type_bitmask { 314 BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000, 315 BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001 316 }; 317 318 enum bnxt_ulp_resource_func { 319 BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00, 320 BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE = 0x20, 321 BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE = 0x40, 322 BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60, 323 BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80, 324 BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81, 325 BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82, 326 BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83, 327 BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84, 328 BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85, 329 BNXT_ULP_RESOURCE_FUNC_SHARED_TABLE = 0x86, 330 BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x87, 331 BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x88 332 }; 333 334 enum bnxt_ulp_resource_sub_type { 335 BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0, 336 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0, 337 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1, 338 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2, 339 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC = 3, 340 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 4, 341 BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0, 342 BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1 343 }; 344 345 enum bnxt_ulp_sym { 346 BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0, 347 BNXT_ULP_SYM_PKT_TYPE_L2 = 0, 348 BNXT_ULP_SYM_PKT_TYPE_0_IGNORE = 0, 349 BNXT_ULP_SYM_PKT_TYPE_0_L2 = 0, 350 BNXT_ULP_SYM_PKT_TYPE_1_IGNORE = 0, 351 BNXT_ULP_SYM_PKT_TYPE_1_L2 = 0, 352 BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0, 353 BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0, 354 BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1, 355 BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2, 356 BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3, 357 BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0, 358 BNXT_ULP_SYM_AGG_ERROR_NO = 0, 359 BNXT_ULP_SYM_AGG_ERROR_YES = 1, 360 BNXT_ULP_SYM_RESERVED_IGNORE = 0, 361 BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0, 362 BNXT_ULP_SYM_HREC_NEXT_NO = 0, 363 BNXT_ULP_SYM_HREC_NEXT_YES = 1, 364 BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0, 365 BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0, 366 BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1, 367 BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0, 368 BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0, 369 BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0, 370 BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0, 371 BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2, 372 BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3, 373 BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0, 374 BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0, 375 BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1, 376 BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0, 377 BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0, 378 BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1, 379 BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0, 380 BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0, 381 BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1, 382 BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0, 383 BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0, 384 BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1, 385 BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0, 386 BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0, 387 BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1, 388 BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0, 389 BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0, 390 BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1, 391 BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, 392 BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0, 393 BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1, 394 BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, 395 BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0, 396 BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1, 397 BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0, 398 BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0, 399 BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1, 400 BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0, 401 BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0, 402 BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1, 403 BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, 404 BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, 405 BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, 406 BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0, 407 BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0, 408 BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1, 409 BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0, 410 BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0, 411 BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1, 412 BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0, 413 BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0, 414 BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1, 415 BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0, 416 BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0, 417 BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1, 418 BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2, 419 BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3, 420 BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4, 421 BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5, 422 BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6, 423 BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7, 424 BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8, 425 BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9, 426 BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15, 427 BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0, 428 BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0, 429 BNXT_ULP_SYM_L2_HDR_VALID_NO = 0, 430 BNXT_ULP_SYM_L2_HDR_VALID_YES = 1, 431 BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0, 432 BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0, 433 BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1, 434 BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0, 435 BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0, 436 BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1, 437 BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2, 438 BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0, 439 BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0, 440 BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2, 441 BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3, 442 BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0, 443 BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0, 444 BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1, 445 BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0, 446 BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0, 447 BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1, 448 BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0, 449 BNXT_ULP_SYM_L3_HDR_VALID_NO = 0, 450 BNXT_ULP_SYM_L3_HDR_VALID_YES = 1, 451 BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0, 452 BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0, 453 BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1, 454 BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0, 455 BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0, 456 BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1, 457 BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2, 458 BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3, 459 BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4, 460 BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5, 461 BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6, 462 BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7, 463 BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8, 464 BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0, 465 BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0, 466 BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1, 467 BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, 468 BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0, 469 BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1, 470 BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0, 471 BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0, 472 BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1, 473 BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0, 474 BNXT_ULP_SYM_L4_HDR_VALID_NO = 0, 475 BNXT_ULP_SYM_L4_HDR_VALID_YES = 1, 476 BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0, 477 BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0, 478 BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1, 479 BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0, 480 BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0, 481 BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1, 482 BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2, 483 BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3, 484 BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4, 485 BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5, 486 BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, 487 BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0, 488 BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1, 489 BNXT_ULP_SYM_POP_VLAN_NO = 0, 490 BNXT_ULP_SYM_POP_VLAN_YES = 1, 491 BNXT_ULP_SYM_DECAP_FUNC_NONE = 0, 492 BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3, 493 BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8, 494 BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9, 495 BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10, 496 BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11, 497 BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12, 498 BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13, 499 BNXT_ULP_SYM_ECV_VALID_NO = 0, 500 BNXT_ULP_SYM_ECV_VALID_YES = 1, 501 BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0, 502 BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1, 503 BNXT_ULP_SYM_ECV_L2_EN_NO = 0, 504 BNXT_ULP_SYM_ECV_L2_EN_YES = 1, 505 BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0, 506 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, 507 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, 508 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, 509 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, 510 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, 511 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, 512 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, 513 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, 514 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, 515 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, 516 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, 517 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, 518 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, 519 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, 520 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, 521 BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0, 522 BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4, 523 BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5, 524 BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6, 525 BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7, 526 BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0, 527 BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4, 528 BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5, 529 BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, 530 BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, 531 BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0, 532 BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1, 533 BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2, 534 BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3, 535 BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4, 536 BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5, 537 BNXT_ULP_SYM_WH_PLUS_INT_ACT_REC = 1, 538 BNXT_ULP_SYM_WH_PLUS_EXT_ACT_REC = 0, 539 BNXT_ULP_SYM_WH_PLUS_UC_ACT_REC = 0, 540 BNXT_ULP_SYM_WH_PLUS_MC_ACT_REC = 1, 541 BNXT_ULP_SYM_ACT_REC_DROP_YES = 1, 542 BNXT_ULP_SYM_ACT_REC_DROP_NO = 0, 543 BNXT_ULP_SYM_ACT_REC_POP_VLAN_YES = 1, 544 BNXT_ULP_SYM_ACT_REC_POP_VLAN_NO = 0, 545 BNXT_ULP_SYM_ACT_REC_METER_EN_YES = 1, 546 BNXT_ULP_SYM_ACT_REC_METER_EN_NO = 0, 547 BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 4, 548 BNXT_ULP_SYM_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448, 549 BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 16, 550 BNXT_ULP_SYM_STINGRAY_EXT_EM_MAX_KEY_SIZE = 448, 551 BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3, 552 BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3, 553 BNXT_ULP_SYM_MATCH_TYPE_EM = 0, 554 BNXT_ULP_SYM_MATCH_TYPE_WM = 1, 555 BNXT_ULP_SYM_IP_PROTO_ICMP = 1, 556 BNXT_ULP_SYM_IP_PROTO_IGMP = 2, 557 BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4, 558 BNXT_ULP_SYM_IP_PROTO_TCP = 6, 559 BNXT_ULP_SYM_IP_PROTO_UDP = 17, 560 BNXT_ULP_SYM_VF_FUNC_PARIF = 15, 561 BNXT_ULP_SYM_NO = 0, 562 BNXT_ULP_SYM_YES = 1, 563 BNXT_ULP_SYM_RECYCLE_DST = 0x800 564 }; 565 566 enum bnxt_ulp_wh_plus { 567 BNXT_ULP_WH_PLUS_LOOPBACK_PORT = 4, 568 BNXT_ULP_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448 569 }; 570 571 enum bnxt_ulp_act_prop_sz { 572 BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4, 573 BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4, 574 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4, 575 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4, 576 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4, 577 BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4, 578 BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4, 579 BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4, 580 BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4, 581 BNXT_ULP_ACT_PROP_SZ_VNIC = 4, 582 BNXT_ULP_ACT_PROP_SZ_VPORT = 4, 583 BNXT_ULP_ACT_PROP_SZ_MARK = 4, 584 BNXT_ULP_ACT_PROP_SZ_COUNT = 4, 585 BNXT_ULP_ACT_PROP_SZ_METER = 4, 586 BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8, 587 BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8, 588 BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN = 2, 589 BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP = 1, 590 BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID = 2, 591 BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4, 592 BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4, 593 BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16, 594 BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16, 595 BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 2, 596 BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 2, 597 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4, 598 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4, 599 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4, 600 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4, 601 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4, 602 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4, 603 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4, 604 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4, 605 BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6, 606 BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6, 607 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8, 608 BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32, 609 BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16, 610 BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4, 611 BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32, 612 BNXT_ULP_ACT_PROP_SZ_JUMP = 4, 613 BNXT_ULP_ACT_PROP_SZ_LAST = 4 614 }; 615 616 enum bnxt_ulp_act_prop_idx { 617 BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0, 618 BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4, 619 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8, 620 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12, 621 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16, 622 BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20, 623 BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24, 624 BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28, 625 BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32, 626 BNXT_ULP_ACT_PROP_IDX_VNIC = 36, 627 BNXT_ULP_ACT_PROP_IDX_VPORT = 40, 628 BNXT_ULP_ACT_PROP_IDX_MARK = 44, 629 BNXT_ULP_ACT_PROP_IDX_COUNT = 48, 630 BNXT_ULP_ACT_PROP_IDX_METER = 52, 631 BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56, 632 BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64, 633 BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN = 72, 634 BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP = 74, 635 BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID = 75, 636 BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 77, 637 BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 81, 638 BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 85, 639 BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 101, 640 BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 117, 641 BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 119, 642 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 121, 643 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 125, 644 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 129, 645 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 133, 646 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 137, 647 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 141, 648 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 145, 649 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 149, 650 BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 153, 651 BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 159, 652 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 165, 653 BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 173, 654 BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205, 655 BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221, 656 BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225, 657 BNXT_ULP_ACT_PROP_IDX_JUMP = 257, 658 BNXT_ULP_ACT_PROP_IDX_LAST = 261 659 }; 660 661 enum bnxt_ulp_class_hid { 662 BNXT_ULP_CLASS_HID_0138 = 0x0138, 663 BNXT_ULP_CLASS_HID_03f0 = 0x03f0, 664 BNXT_ULP_CLASS_HID_0139 = 0x0139, 665 BNXT_ULP_CLASS_HID_03f1 = 0x03f1, 666 BNXT_ULP_CLASS_HID_068b = 0x068b, 667 BNXT_ULP_CLASS_HID_0143 = 0x0143, 668 BNXT_ULP_CLASS_HID_0118 = 0x0118, 669 BNXT_ULP_CLASS_HID_03d0 = 0x03d0, 670 BNXT_ULP_CLASS_HID_0119 = 0x0119, 671 BNXT_ULP_CLASS_HID_03d1 = 0x03d1, 672 BNXT_ULP_CLASS_HID_06ab = 0x06ab, 673 BNXT_ULP_CLASS_HID_0163 = 0x0163, 674 BNXT_ULP_CLASS_HID_0128 = 0x0128, 675 BNXT_ULP_CLASS_HID_03e0 = 0x03e0, 676 BNXT_ULP_CLASS_HID_0129 = 0x0129, 677 BNXT_ULP_CLASS_HID_03e1 = 0x03e1, 678 BNXT_ULP_CLASS_HID_069b = 0x069b, 679 BNXT_ULP_CLASS_HID_0153 = 0x0153, 680 BNXT_ULP_CLASS_HID_0134 = 0x0134, 681 BNXT_ULP_CLASS_HID_03fc = 0x03fc, 682 BNXT_ULP_CLASS_HID_0135 = 0x0135, 683 BNXT_ULP_CLASS_HID_03fd = 0x03fd, 684 BNXT_ULP_CLASS_HID_0687 = 0x0687, 685 BNXT_ULP_CLASS_HID_014f = 0x014f, 686 BNXT_ULP_CLASS_HID_0114 = 0x0114, 687 BNXT_ULP_CLASS_HID_03dc = 0x03dc, 688 BNXT_ULP_CLASS_HID_0115 = 0x0115, 689 BNXT_ULP_CLASS_HID_03dd = 0x03dd, 690 BNXT_ULP_CLASS_HID_06a7 = 0x06a7, 691 BNXT_ULP_CLASS_HID_016f = 0x016f, 692 BNXT_ULP_CLASS_HID_0124 = 0x0124, 693 BNXT_ULP_CLASS_HID_03ec = 0x03ec, 694 BNXT_ULP_CLASS_HID_0125 = 0x0125, 695 BNXT_ULP_CLASS_HID_03ed = 0x03ed, 696 BNXT_ULP_CLASS_HID_0697 = 0x0697, 697 BNXT_ULP_CLASS_HID_015f = 0x015f, 698 BNXT_ULP_CLASS_HID_0452 = 0x0452, 699 BNXT_ULP_CLASS_HID_0528 = 0x0528, 700 BNXT_ULP_CLASS_HID_0790 = 0x0790, 701 BNXT_ULP_CLASS_HID_046e = 0x046e, 702 BNXT_ULP_CLASS_HID_0462 = 0x0462, 703 BNXT_ULP_CLASS_HID_0518 = 0x0518, 704 BNXT_ULP_CLASS_HID_07a0 = 0x07a0, 705 BNXT_ULP_CLASS_HID_045e = 0x045e, 706 BNXT_ULP_CLASS_HID_0228 = 0x0228, 707 BNXT_ULP_CLASS_HID_06d0 = 0x06d0, 708 BNXT_ULP_CLASS_HID_02be = 0x02be, 709 BNXT_ULP_CLASS_HID_07a6 = 0x07a6, 710 BNXT_ULP_CLASS_HID_0218 = 0x0218, 711 BNXT_ULP_CLASS_HID_06e0 = 0x06e0, 712 BNXT_ULP_CLASS_HID_028e = 0x028e, 713 BNXT_ULP_CLASS_HID_0796 = 0x0796, 714 BNXT_ULP_CLASS_HID_079c = 0x079c, 715 BNXT_ULP_CLASS_HID_0654 = 0x0654, 716 BNXT_ULP_CLASS_HID_06d2 = 0x06d2, 717 BNXT_ULP_CLASS_HID_058a = 0x058a, 718 BNXT_ULP_CLASS_HID_052f = 0x052f, 719 BNXT_ULP_CLASS_HID_07e7 = 0x07e7, 720 BNXT_ULP_CLASS_HID_079d = 0x079d, 721 BNXT_ULP_CLASS_HID_0655 = 0x0655, 722 BNXT_ULP_CLASS_HID_046d = 0x046d, 723 BNXT_ULP_CLASS_HID_0725 = 0x0725, 724 BNXT_ULP_CLASS_HID_06d3 = 0x06d3, 725 BNXT_ULP_CLASS_HID_058b = 0x058b, 726 BNXT_ULP_CLASS_HID_07ac = 0x07ac, 727 BNXT_ULP_CLASS_HID_0664 = 0x0664, 728 BNXT_ULP_CLASS_HID_06e2 = 0x06e2, 729 BNXT_ULP_CLASS_HID_05ba = 0x05ba, 730 BNXT_ULP_CLASS_HID_051f = 0x051f, 731 BNXT_ULP_CLASS_HID_07d7 = 0x07d7, 732 BNXT_ULP_CLASS_HID_07ad = 0x07ad, 733 BNXT_ULP_CLASS_HID_0665 = 0x0665, 734 BNXT_ULP_CLASS_HID_045d = 0x045d, 735 BNXT_ULP_CLASS_HID_0715 = 0x0715, 736 BNXT_ULP_CLASS_HID_06e3 = 0x06e3, 737 BNXT_ULP_CLASS_HID_05bb = 0x05bb, 738 BNXT_ULP_CLASS_HID_016a = 0x016a, 739 BNXT_ULP_CLASS_HID_03d2 = 0x03d2, 740 BNXT_ULP_CLASS_HID_0612 = 0x0612, 741 BNXT_ULP_CLASS_HID_00da = 0x00da, 742 BNXT_ULP_CLASS_HID_06bd = 0x06bd, 743 BNXT_ULP_CLASS_HID_0165 = 0x0165, 744 BNXT_ULP_CLASS_HID_016b = 0x016b, 745 BNXT_ULP_CLASS_HID_03d3 = 0x03d3, 746 BNXT_ULP_CLASS_HID_03a5 = 0x03a5, 747 BNXT_ULP_CLASS_HID_066d = 0x066d, 748 BNXT_ULP_CLASS_HID_0613 = 0x0613, 749 BNXT_ULP_CLASS_HID_00db = 0x00db, 750 BNXT_ULP_CLASS_HID_015a = 0x015a, 751 BNXT_ULP_CLASS_HID_03e2 = 0x03e2, 752 BNXT_ULP_CLASS_HID_0622 = 0x0622, 753 BNXT_ULP_CLASS_HID_00ea = 0x00ea, 754 BNXT_ULP_CLASS_HID_068d = 0x068d, 755 BNXT_ULP_CLASS_HID_0155 = 0x0155, 756 BNXT_ULP_CLASS_HID_015b = 0x015b, 757 BNXT_ULP_CLASS_HID_03e3 = 0x03e3, 758 BNXT_ULP_CLASS_HID_0395 = 0x0395, 759 BNXT_ULP_CLASS_HID_065d = 0x065d, 760 BNXT_ULP_CLASS_HID_0623 = 0x0623, 761 BNXT_ULP_CLASS_HID_00eb = 0x00eb, 762 BNXT_ULP_CLASS_HID_04bc = 0x04bc, 763 BNXT_ULP_CLASS_HID_0442 = 0x0442, 764 BNXT_ULP_CLASS_HID_050a = 0x050a, 765 BNXT_ULP_CLASS_HID_06ba = 0x06ba, 766 BNXT_ULP_CLASS_HID_0472 = 0x0472, 767 BNXT_ULP_CLASS_HID_0700 = 0x0700, 768 BNXT_ULP_CLASS_HID_04c8 = 0x04c8, 769 BNXT_ULP_CLASS_HID_0678 = 0x0678, 770 BNXT_ULP_CLASS_HID_061f = 0x061f, 771 BNXT_ULP_CLASS_HID_05ad = 0x05ad, 772 BNXT_ULP_CLASS_HID_06a5 = 0x06a5, 773 BNXT_ULP_CLASS_HID_0455 = 0x0455, 774 BNXT_ULP_CLASS_HID_05dd = 0x05dd, 775 BNXT_ULP_CLASS_HID_0563 = 0x0563, 776 BNXT_ULP_CLASS_HID_059b = 0x059b, 777 BNXT_ULP_CLASS_HID_070b = 0x070b, 778 BNXT_ULP_CLASS_HID_04bd = 0x04bd, 779 BNXT_ULP_CLASS_HID_0443 = 0x0443, 780 BNXT_ULP_CLASS_HID_050b = 0x050b, 781 BNXT_ULP_CLASS_HID_06bb = 0x06bb, 782 BNXT_ULP_CLASS_HID_0473 = 0x0473, 783 BNXT_ULP_CLASS_HID_0701 = 0x0701, 784 BNXT_ULP_CLASS_HID_04c9 = 0x04c9, 785 BNXT_ULP_CLASS_HID_0679 = 0x0679, 786 BNXT_ULP_CLASS_HID_05e2 = 0x05e2, 787 BNXT_ULP_CLASS_HID_00b0 = 0x00b0, 788 BNXT_ULP_CLASS_HID_0648 = 0x0648, 789 BNXT_ULP_CLASS_HID_03f8 = 0x03f8, 790 BNXT_ULP_CLASS_HID_02ea = 0x02ea, 791 BNXT_ULP_CLASS_HID_05b8 = 0x05b8, 792 BNXT_ULP_CLASS_HID_0370 = 0x0370, 793 BNXT_ULP_CLASS_HID_00e0 = 0x00e0, 794 BNXT_ULP_CLASS_HID_0745 = 0x0745, 795 BNXT_ULP_CLASS_HID_0213 = 0x0213, 796 BNXT_ULP_CLASS_HID_031b = 0x031b, 797 BNXT_ULP_CLASS_HID_008b = 0x008b, 798 BNXT_ULP_CLASS_HID_044d = 0x044d, 799 BNXT_ULP_CLASS_HID_071b = 0x071b, 800 BNXT_ULP_CLASS_HID_0003 = 0x0003, 801 BNXT_ULP_CLASS_HID_05b3 = 0x05b3, 802 BNXT_ULP_CLASS_HID_05e3 = 0x05e3, 803 BNXT_ULP_CLASS_HID_00b1 = 0x00b1, 804 BNXT_ULP_CLASS_HID_0649 = 0x0649, 805 BNXT_ULP_CLASS_HID_03f9 = 0x03f9, 806 BNXT_ULP_CLASS_HID_02eb = 0x02eb, 807 BNXT_ULP_CLASS_HID_05b9 = 0x05b9, 808 BNXT_ULP_CLASS_HID_0371 = 0x0371, 809 BNXT_ULP_CLASS_HID_00e1 = 0x00e1, 810 BNXT_ULP_CLASS_HID_0000 = 0x0000, 811 BNXT_ULP_CLASS_HID_00ce = 0x00ce, 812 BNXT_ULP_CLASS_HID_01b6 = 0x01b6, 813 BNXT_ULP_CLASS_HID_0074 = 0x0074, 814 BNXT_ULP_CLASS_HID_00fe = 0x00fe, 815 BNXT_ULP_CLASS_HID_03bc = 0x03bc, 816 BNXT_ULP_CLASS_HID_0206 = 0x0206, 817 BNXT_ULP_CLASS_HID_02c4 = 0x02c4, 818 BNXT_ULP_CLASS_HID_055a = 0x055a, 819 BNXT_ULP_CLASS_HID_045a = 0x045a, 820 BNXT_ULP_CLASS_HID_061a = 0x061a, 821 BNXT_ULP_CLASS_HID_051a = 0x051a, 822 BNXT_ULP_CLASS_HID_074a = 0x074a, 823 BNXT_ULP_CLASS_HID_004e = 0x004e, 824 BNXT_ULP_CLASS_HID_040a = 0x040a, 825 BNXT_ULP_CLASS_HID_010e = 0x010e, 826 BNXT_ULP_CLASS_HID_048b = 0x048b, 827 BNXT_ULP_CLASS_HID_0749 = 0x0749, 828 BNXT_ULP_CLASS_HID_05f1 = 0x05f1, 829 BNXT_ULP_CLASS_HID_04b7 = 0x04b7, 830 BNXT_ULP_CLASS_HID_049b = 0x049b, 831 BNXT_ULP_CLASS_HID_0759 = 0x0759, 832 BNXT_ULP_CLASS_HID_05e1 = 0x05e1, 833 BNXT_ULP_CLASS_HID_04a7 = 0x04a7, 834 BNXT_ULP_CLASS_HID_0301 = 0x0301, 835 BNXT_ULP_CLASS_HID_07f9 = 0x07f9, 836 BNXT_ULP_CLASS_HID_0397 = 0x0397, 837 BNXT_ULP_CLASS_HID_068f = 0x068f, 838 BNXT_ULP_CLASS_HID_02f1 = 0x02f1, 839 BNXT_ULP_CLASS_HID_0609 = 0x0609, 840 BNXT_ULP_CLASS_HID_0267 = 0x0267, 841 BNXT_ULP_CLASS_HID_077f = 0x077f, 842 BNXT_ULP_CLASS_HID_01e1 = 0x01e1, 843 BNXT_ULP_CLASS_HID_0329 = 0x0329, 844 BNXT_ULP_CLASS_HID_01c1 = 0x01c1, 845 BNXT_ULP_CLASS_HID_0309 = 0x0309, 846 BNXT_ULP_CLASS_HID_01d1 = 0x01d1, 847 BNXT_ULP_CLASS_HID_0319 = 0x0319, 848 BNXT_ULP_CLASS_HID_01e2 = 0x01e2, 849 BNXT_ULP_CLASS_HID_032a = 0x032a, 850 BNXT_ULP_CLASS_HID_0650 = 0x0650, 851 BNXT_ULP_CLASS_HID_0198 = 0x0198, 852 BNXT_ULP_CLASS_HID_01c2 = 0x01c2, 853 BNXT_ULP_CLASS_HID_030a = 0x030a, 854 BNXT_ULP_CLASS_HID_0670 = 0x0670, 855 BNXT_ULP_CLASS_HID_01b8 = 0x01b8, 856 BNXT_ULP_CLASS_HID_01d2 = 0x01d2, 857 BNXT_ULP_CLASS_HID_031a = 0x031a, 858 BNXT_ULP_CLASS_HID_0660 = 0x0660, 859 BNXT_ULP_CLASS_HID_01a8 = 0x01a8, 860 BNXT_ULP_CLASS_HID_01dd = 0x01dd, 861 BNXT_ULP_CLASS_HID_0315 = 0x0315, 862 BNXT_ULP_CLASS_HID_003d = 0x003d, 863 BNXT_ULP_CLASS_HID_02f5 = 0x02f5, 864 BNXT_ULP_CLASS_HID_01cd = 0x01cd, 865 BNXT_ULP_CLASS_HID_0305 = 0x0305, 866 BNXT_ULP_CLASS_HID_01de = 0x01de, 867 BNXT_ULP_CLASS_HID_0316 = 0x0316, 868 BNXT_ULP_CLASS_HID_066c = 0x066c, 869 BNXT_ULP_CLASS_HID_01a4 = 0x01a4, 870 BNXT_ULP_CLASS_HID_003e = 0x003e, 871 BNXT_ULP_CLASS_HID_02f6 = 0x02f6, 872 BNXT_ULP_CLASS_HID_078c = 0x078c, 873 BNXT_ULP_CLASS_HID_0044 = 0x0044, 874 BNXT_ULP_CLASS_HID_01ce = 0x01ce, 875 BNXT_ULP_CLASS_HID_0306 = 0x0306, 876 BNXT_ULP_CLASS_HID_067c = 0x067c, 877 BNXT_ULP_CLASS_HID_01b4 = 0x01b4 878 }; 879 880 enum bnxt_ulp_act_hid { 881 BNXT_ULP_ACT_HID_015a = 0x015a, 882 BNXT_ULP_ACT_HID_00eb = 0x00eb, 883 BNXT_ULP_ACT_HID_0043 = 0x0043, 884 BNXT_ULP_ACT_HID_03d8 = 0x03d8, 885 BNXT_ULP_ACT_HID_02c1 = 0x02c1, 886 BNXT_ULP_ACT_HID_015e = 0x015e, 887 BNXT_ULP_ACT_HID_00ef = 0x00ef, 888 BNXT_ULP_ACT_HID_0047 = 0x0047, 889 BNXT_ULP_ACT_HID_03dc = 0x03dc, 890 BNXT_ULP_ACT_HID_02c5 = 0x02c5, 891 BNXT_ULP_ACT_HID_025b = 0x025b, 892 BNXT_ULP_ACT_HID_01ec = 0x01ec, 893 BNXT_ULP_ACT_HID_0144 = 0x0144, 894 BNXT_ULP_ACT_HID_04d9 = 0x04d9, 895 BNXT_ULP_ACT_HID_03c2 = 0x03c2, 896 BNXT_ULP_ACT_HID_025f = 0x025f, 897 BNXT_ULP_ACT_HID_01f0 = 0x01f0, 898 BNXT_ULP_ACT_HID_0148 = 0x0148, 899 BNXT_ULP_ACT_HID_04dd = 0x04dd, 900 BNXT_ULP_ACT_HID_03c6 = 0x03c6, 901 BNXT_ULP_ACT_HID_0000 = 0x0000, 902 BNXT_ULP_ACT_HID_0002 = 0x0002, 903 BNXT_ULP_ACT_HID_0800 = 0x0800, 904 BNXT_ULP_ACT_HID_0101 = 0x0101, 905 BNXT_ULP_ACT_HID_0020 = 0x0020, 906 BNXT_ULP_ACT_HID_0901 = 0x0901, 907 BNXT_ULP_ACT_HID_0121 = 0x0121, 908 BNXT_ULP_ACT_HID_0004 = 0x0004, 909 BNXT_ULP_ACT_HID_0006 = 0x0006, 910 BNXT_ULP_ACT_HID_0804 = 0x0804, 911 BNXT_ULP_ACT_HID_0105 = 0x0105, 912 BNXT_ULP_ACT_HID_0024 = 0x0024, 913 BNXT_ULP_ACT_HID_0905 = 0x0905, 914 BNXT_ULP_ACT_HID_0125 = 0x0125, 915 BNXT_ULP_ACT_HID_0001 = 0x0001, 916 BNXT_ULP_ACT_HID_0005 = 0x0005, 917 BNXT_ULP_ACT_HID_0009 = 0x0009, 918 BNXT_ULP_ACT_HID_000d = 0x000d, 919 BNXT_ULP_ACT_HID_0021 = 0x0021, 920 BNXT_ULP_ACT_HID_0029 = 0x0029, 921 BNXT_ULP_ACT_HID_0025 = 0x0025, 922 BNXT_ULP_ACT_HID_002d = 0x002d, 923 BNXT_ULP_ACT_HID_0801 = 0x0801, 924 BNXT_ULP_ACT_HID_0809 = 0x0809, 925 BNXT_ULP_ACT_HID_0805 = 0x0805, 926 BNXT_ULP_ACT_HID_080d = 0x080d, 927 BNXT_ULP_ACT_HID_0c15 = 0x0c15, 928 BNXT_ULP_ACT_HID_0c19 = 0x0c19, 929 BNXT_ULP_ACT_HID_02f6 = 0x02f6, 930 BNXT_ULP_ACT_HID_04f8 = 0x04f8, 931 BNXT_ULP_ACT_HID_01df = 0x01df, 932 BNXT_ULP_ACT_HID_07e5 = 0x07e5, 933 BNXT_ULP_ACT_HID_06ce = 0x06ce, 934 BNXT_ULP_ACT_HID_02fa = 0x02fa, 935 BNXT_ULP_ACT_HID_04fc = 0x04fc, 936 BNXT_ULP_ACT_HID_01e3 = 0x01e3, 937 BNXT_ULP_ACT_HID_07e9 = 0x07e9, 938 BNXT_ULP_ACT_HID_06d2 = 0x06d2, 939 BNXT_ULP_ACT_HID_03f7 = 0x03f7, 940 BNXT_ULP_ACT_HID_05f9 = 0x05f9, 941 BNXT_ULP_ACT_HID_02e0 = 0x02e0, 942 BNXT_ULP_ACT_HID_08e6 = 0x08e6, 943 BNXT_ULP_ACT_HID_07cf = 0x07cf, 944 BNXT_ULP_ACT_HID_03fb = 0x03fb, 945 BNXT_ULP_ACT_HID_05fd = 0x05fd, 946 BNXT_ULP_ACT_HID_02e4 = 0x02e4, 947 BNXT_ULP_ACT_HID_08ea = 0x08ea, 948 BNXT_ULP_ACT_HID_07d3 = 0x07d3, 949 BNXT_ULP_ACT_HID_040d = 0x040d, 950 BNXT_ULP_ACT_HID_040f = 0x040f, 951 BNXT_ULP_ACT_HID_0413 = 0x0413, 952 BNXT_ULP_ACT_HID_0567 = 0x0567, 953 BNXT_ULP_ACT_HID_0a49 = 0x0a49, 954 BNXT_ULP_ACT_HID_050e = 0x050e, 955 BNXT_ULP_ACT_HID_0668 = 0x0668, 956 BNXT_ULP_ACT_HID_0b4a = 0x0b4a, 957 BNXT_ULP_ACT_HID_0411 = 0x0411, 958 BNXT_ULP_ACT_HID_056b = 0x056b, 959 BNXT_ULP_ACT_HID_0a4d = 0x0a4d, 960 BNXT_ULP_ACT_HID_0512 = 0x0512, 961 BNXT_ULP_ACT_HID_066c = 0x066c, 962 BNXT_ULP_ACT_HID_0b4e = 0x0b4e 963 }; 964 965 enum bnxt_ulp_df_tpl { 966 BNXT_ULP_DF_TPL_PORT_TO_VS = 1, 967 BNXT_ULP_DF_TPL_VS_TO_PORT = 2, 968 BNXT_ULP_DF_TPL_VFREP_TO_VF = 3, 969 BNXT_ULP_DF_TPL_VF_TO_VFREP = 4, 970 BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 5 971 }; 972 973 #endif 974