1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2000
5 * Bill Paul <[email protected]>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37
38 /*
39 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/bus.h>
48 #include <sys/taskqueue.h>
49
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/ethernet.h>
53 #include <net/if_media.h>
54
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
57 #include "miidevs.h"
58
59 #include <dev/mii/brgphyreg.h>
60 #include <net/if_arp.h>
61 #include <machine/bus.h>
62 #include <dev/bge/if_bgereg.h>
63 #include <dev/bce/if_bcereg.h>
64
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
67
68 #include "miibus_if.h"
69
70 static int brgphy_probe(device_t);
71 static int brgphy_attach(device_t);
72
73 struct brgphy_softc {
74 struct mii_softc mii_sc;
75 int serdes_flags; /* Keeps track of the serdes type used */
76 #define BRGPHY_5706S 0x0001
77 #define BRGPHY_5708S 0x0002
78 #define BRGPHY_NOANWAIT 0x0004
79 #define BRGPHY_5709S 0x0008
80 int bce_phy_flags; /* PHY flags transferred from the MAC driver */
81 };
82
83 static device_method_t brgphy_methods[] = {
84 /* device interface */
85 DEVMETHOD(device_probe, brgphy_probe),
86 DEVMETHOD(device_attach, brgphy_attach),
87 DEVMETHOD(device_detach, mii_phy_detach),
88 DEVMETHOD(device_shutdown, bus_generic_shutdown),
89 DEVMETHOD_END
90 };
91
92 static devclass_t brgphy_devclass;
93
94 static driver_t brgphy_driver = {
95 "brgphy",
96 brgphy_methods,
97 sizeof(struct brgphy_softc)
98 };
99
100 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
101
102 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
103 static void brgphy_setmedia(struct mii_softc *, int);
104 static void brgphy_status(struct mii_softc *);
105 static void brgphy_mii_phy_auto(struct mii_softc *, int);
106 static void brgphy_reset(struct mii_softc *);
107 static void brgphy_enable_loopback(struct mii_softc *);
108 static void bcm5401_load_dspcode(struct mii_softc *);
109 static void bcm5411_load_dspcode(struct mii_softc *);
110 static void bcm54k2_load_dspcode(struct mii_softc *);
111 static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
112 static void brgphy_fixup_adc_bug(struct mii_softc *);
113 static void brgphy_fixup_adjust_trim(struct mii_softc *);
114 static void brgphy_fixup_ber_bug(struct mii_softc *);
115 static void brgphy_fixup_crc_bug(struct mii_softc *);
116 static void brgphy_fixup_jitter_bug(struct mii_softc *);
117 static void brgphy_ethernet_wirespeed(struct mii_softc *);
118 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
119
120 static const struct mii_phydesc brgphys[] = {
121 MII_PHY_DESC(BROADCOM, BCM5400),
122 MII_PHY_DESC(BROADCOM, BCM5401),
123 MII_PHY_DESC(BROADCOM, BCM5402),
124 MII_PHY_DESC(BROADCOM, BCM5411),
125 MII_PHY_DESC(BROADCOM, BCM5404),
126 MII_PHY_DESC(BROADCOM, BCM5424),
127 MII_PHY_DESC(BROADCOM, BCM54K2),
128 MII_PHY_DESC(BROADCOM, BCM5701),
129 MII_PHY_DESC(BROADCOM, BCM5703),
130 MII_PHY_DESC(BROADCOM, BCM5704),
131 MII_PHY_DESC(BROADCOM, BCM5705),
132 MII_PHY_DESC(BROADCOM, BCM5706),
133 MII_PHY_DESC(BROADCOM, BCM5714),
134 MII_PHY_DESC(BROADCOM, BCM5421),
135 MII_PHY_DESC(BROADCOM, BCM5750),
136 MII_PHY_DESC(BROADCOM, BCM5752),
137 MII_PHY_DESC(BROADCOM, BCM5780),
138 MII_PHY_DESC(BROADCOM, BCM5708C),
139 MII_PHY_DESC(BROADCOM, BCM5466),
140 MII_PHY_DESC(BROADCOM2, BCM5478),
141 MII_PHY_DESC(BROADCOM2, BCM5488),
142 MII_PHY_DESC(BROADCOM2, BCM5482),
143 MII_PHY_DESC(BROADCOM2, BCM5708S),
144 MII_PHY_DESC(BROADCOM2, BCM5709C),
145 MII_PHY_DESC(BROADCOM2, BCM5709S),
146 MII_PHY_DESC(BROADCOM2, BCM5709CAX),
147 MII_PHY_DESC(BROADCOM2, BCM5722),
148 MII_PHY_DESC(BROADCOM2, BCM5755),
149 MII_PHY_DESC(BROADCOM2, BCM5754),
150 MII_PHY_DESC(BROADCOM2, BCM5761),
151 MII_PHY_DESC(BROADCOM2, BCM5784),
152 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */
153 MII_PHY_DESC(BROADCOM2, BCM5785),
154 #endif
155 MII_PHY_DESC(BROADCOM3, BCM5717C),
156 MII_PHY_DESC(BROADCOM3, BCM5719C),
157 MII_PHY_DESC(BROADCOM3, BCM5720C),
158 MII_PHY_DESC(BROADCOM3, BCM57765),
159 MII_PHY_DESC(BROADCOM3, BCM57780),
160 MII_PHY_DESC(BROADCOM4, BCM5725C),
161 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
162 MII_PHY_END
163 };
164
165 static const struct mii_phy_funcs brgphy_funcs = {
166 brgphy_service,
167 brgphy_status,
168 brgphy_reset
169 };
170
171 static const struct hs21_type {
172 const uint32_t id;
173 const char *prod;
174 } hs21_type_lists[] = {
175 { 0x57081021, "IBM eServer BladeCenter HS21" },
176 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
177 };
178
179 static int
detect_hs21(struct bce_softc * bce_sc)180 detect_hs21(struct bce_softc *bce_sc)
181 {
182 char *sysenv;
183 int found, i;
184
185 found = 0;
186 sysenv = kern_getenv("smbios.system.product");
187 if (sysenv == NULL)
188 return (found);
189 for (i = 0; i < nitems(hs21_type_lists); i++) {
190 if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
191 strncmp(sysenv, hs21_type_lists[i].prod,
192 strlen(hs21_type_lists[i].prod)) == 0) {
193 found++;
194 break;
195 }
196 }
197 freeenv(sysenv);
198 return (found);
199 }
200
201 /* Search for our PHY in the list of known PHYs */
202 static int
brgphy_probe(device_t dev)203 brgphy_probe(device_t dev)
204 {
205
206 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
207 }
208
209 /* Attach the PHY to the MII bus */
210 static int
brgphy_attach(device_t dev)211 brgphy_attach(device_t dev)
212 {
213 struct brgphy_softc *bsc;
214 struct bge_softc *bge_sc = NULL;
215 struct bce_softc *bce_sc = NULL;
216 struct mii_softc *sc;
217
218 bsc = device_get_softc(dev);
219 sc = &bsc->mii_sc;
220
221 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
222 &brgphy_funcs, 0);
223
224 bsc->serdes_flags = 0;
225
226 /* Find the MAC driver associated with this PHY. */
227 if (mii_dev_mac_match(dev, "bge"))
228 bge_sc = mii_dev_mac_softc(dev);
229 else if (mii_dev_mac_match(dev, "bce"))
230 bce_sc = mii_dev_mac_softc(dev);
231
232 /* Handle any special cases based on the PHY ID */
233 switch (sc->mii_mpd_oui) {
234 case MII_OUI_BROADCOM:
235 switch (sc->mii_mpd_model) {
236 case MII_MODEL_BROADCOM_BCM5706:
237 case MII_MODEL_BROADCOM_BCM5714:
238 /*
239 * The 5464 PHY used in the 5706 supports both copper
240 * and fiber interfaces over GMII. Need to check the
241 * shadow registers to see which mode is actually
242 * in effect, and therefore whether we have 5706C or
243 * 5706S.
244 */
245 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
246 BRGPHY_SHADOW_1C_MODE_CTRL);
247 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
248 BRGPHY_SHADOW_1C_ENA_1000X) {
249 bsc->serdes_flags |= BRGPHY_5706S;
250 sc->mii_flags |= MIIF_HAVEFIBER;
251 }
252 break;
253 }
254 break;
255 case MII_OUI_BROADCOM2:
256 switch (sc->mii_mpd_model) {
257 case MII_MODEL_BROADCOM2_BCM5708S:
258 bsc->serdes_flags |= BRGPHY_5708S;
259 sc->mii_flags |= MIIF_HAVEFIBER;
260 break;
261 case MII_MODEL_BROADCOM2_BCM5709S:
262 /*
263 * XXX
264 * 5720S and 5709S shares the same PHY id.
265 * Assume 5720S PHY if parent device is bge(4).
266 */
267 if (bge_sc != NULL)
268 bsc->serdes_flags |= BRGPHY_5708S;
269 else
270 bsc->serdes_flags |= BRGPHY_5709S;
271 sc->mii_flags |= MIIF_HAVEFIBER;
272 break;
273 }
274 break;
275 }
276
277 PHY_RESET(sc);
278
279 /* Read the PHY's capabilities. */
280 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
281 if (sc->mii_capabilities & BMSR_EXTSTAT)
282 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
283 device_printf(dev, " ");
284
285 /* Add the supported media types */
286 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
287 mii_phy_add_media(sc);
288 printf("\n");
289 } else {
290 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
291 ifmedia_add(&sc->mii_pdata->mii_media,
292 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
293 0, NULL);
294 printf("1000baseSX-FDX, ");
295 /*
296 * 2.5G support is a software enabled feature
297 * on the 5708S and 5709S.
298 */
299 if (bce_sc && (bce_sc->bce_phy_flags &
300 BCE_PHY_2_5G_CAPABLE_FLAG)) {
301 ifmedia_add(&sc->mii_pdata->mii_media,
302 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
303 sc->mii_inst), 0, NULL);
304 printf("2500baseSX-FDX, ");
305 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
306 (detect_hs21(bce_sc) != 0)) {
307 /*
308 * There appears to be certain silicon revision
309 * in IBM HS21 blades that is having issues with
310 * this driver wating for the auto-negotiation to
311 * complete. This happens with a specific chip id
312 * only and when the 1000baseSX-FDX is the only
313 * mode. Workaround this issue since it's unlikely
314 * to be ever addressed.
315 */
316 printf("auto-neg workaround, ");
317 bsc->serdes_flags |= BRGPHY_NOANWAIT;
318 }
319 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
320 IFM_AUTO, 0, sc->mii_inst), 0, NULL);
321 printf("auto\n");
322 }
323
324 MIIBUS_MEDIAINIT(sc->mii_dev);
325 return (0);
326 }
327
328 static int
brgphy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)329 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
330 {
331 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
332 int val;
333
334 switch (cmd) {
335 case MII_POLLSTAT:
336 break;
337 case MII_MEDIACHG:
338 /* Todo: Why is this here? Is it really needed? */
339 PHY_RESET(sc); /* XXX hardware bug work-around */
340
341 switch (IFM_SUBTYPE(ife->ifm_media)) {
342 case IFM_AUTO:
343 brgphy_mii_phy_auto(sc, ife->ifm_media);
344 break;
345 case IFM_2500_SX:
346 case IFM_1000_SX:
347 case IFM_1000_T:
348 case IFM_100_TX:
349 case IFM_10_T:
350 brgphy_setmedia(sc, ife->ifm_media);
351 break;
352 default:
353 return (EINVAL);
354 }
355 break;
356 case MII_TICK:
357 /* Bail if autoneg isn't in process. */
358 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
359 sc->mii_ticks = 0;
360 break;
361 }
362
363 /*
364 * Check to see if we have link. If we do, we don't
365 * need to restart the autonegotiation process.
366 */
367 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
368 if (val & BMSR_LINK) {
369 sc->mii_ticks = 0; /* Reset autoneg timer. */
370 break;
371 }
372
373 /* Announce link loss right after it happens. */
374 if (sc->mii_ticks++ == 0)
375 break;
376
377 /* Only retry autonegotiation every mii_anegticks seconds. */
378 if (sc->mii_ticks <= sc->mii_anegticks)
379 break;
380
381
382 /* Retry autonegotiation */
383 sc->mii_ticks = 0;
384 brgphy_mii_phy_auto(sc, ife->ifm_media);
385 break;
386 }
387
388 /* Update the media status. */
389 PHY_STATUS(sc);
390
391 /*
392 * Callback if something changed. Note that we need to poke
393 * the DSP on the Broadcom PHYs if the media changes.
394 */
395 if (sc->mii_media_active != mii->mii_media_active ||
396 sc->mii_media_status != mii->mii_media_status ||
397 cmd == MII_MEDIACHG) {
398 switch (sc->mii_mpd_oui) {
399 case MII_OUI_BROADCOM:
400 switch (sc->mii_mpd_model) {
401 case MII_MODEL_BROADCOM_BCM5400:
402 bcm5401_load_dspcode(sc);
403 break;
404 case MII_MODEL_BROADCOM_BCM5401:
405 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
406 bcm5401_load_dspcode(sc);
407 break;
408 case MII_MODEL_BROADCOM_BCM5411:
409 bcm5411_load_dspcode(sc);
410 break;
411 case MII_MODEL_BROADCOM_BCM54K2:
412 bcm54k2_load_dspcode(sc);
413 break;
414 }
415 break;
416 }
417 }
418 mii_phy_update(sc, cmd);
419 return (0);
420 }
421
422 /****************************************************************************/
423 /* Sets the PHY link speed. */
424 /* */
425 /* Returns: */
426 /* None */
427 /****************************************************************************/
428 static void
brgphy_setmedia(struct mii_softc * sc,int media)429 brgphy_setmedia(struct mii_softc *sc, int media)
430 {
431 int bmcr = 0, gig;
432
433 switch (IFM_SUBTYPE(media)) {
434 case IFM_2500_SX:
435 break;
436 case IFM_1000_SX:
437 case IFM_1000_T:
438 bmcr = BRGPHY_S1000;
439 break;
440 case IFM_100_TX:
441 bmcr = BRGPHY_S100;
442 break;
443 case IFM_10_T:
444 default:
445 bmcr = BRGPHY_S10;
446 break;
447 }
448
449 if ((media & IFM_FDX) != 0) {
450 bmcr |= BRGPHY_BMCR_FDX;
451 gig = BRGPHY_1000CTL_AFD;
452 } else {
453 gig = BRGPHY_1000CTL_AHD;
454 }
455
456 /* Force loopback to disconnect PHY from Ethernet medium. */
457 brgphy_enable_loopback(sc);
458
459 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
460 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
461
462 if (IFM_SUBTYPE(media) != IFM_1000_T &&
463 IFM_SUBTYPE(media) != IFM_1000_SX) {
464 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
465 return;
466 }
467
468 if (IFM_SUBTYPE(media) == IFM_1000_T) {
469 gig |= BRGPHY_1000CTL_MSE;
470 if ((media & IFM_ETH_MASTER) != 0)
471 gig |= BRGPHY_1000CTL_MSC;
472 }
473 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
474 PHY_WRITE(sc, BRGPHY_MII_BMCR,
475 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
476 }
477
478 /****************************************************************************/
479 /* Set the media status based on the PHY settings. */
480 /* */
481 /* Returns: */
482 /* None */
483 /****************************************************************************/
484 static void
brgphy_status(struct mii_softc * sc)485 brgphy_status(struct mii_softc *sc)
486 {
487 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
488 struct mii_data *mii = sc->mii_pdata;
489 int aux, bmcr, bmsr, val, xstat;
490 u_int flowstat;
491
492 mii->mii_media_status = IFM_AVALID;
493 mii->mii_media_active = IFM_ETHER;
494
495 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
496 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
497
498 if (bmcr & BRGPHY_BMCR_LOOP) {
499 mii->mii_media_active |= IFM_LOOP;
500 }
501
502 if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
503 (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
504 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
505 /* Erg, still trying, I guess... */
506 mii->mii_media_active |= IFM_NONE;
507 return;
508 }
509
510 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
511 /*
512 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
513 * wedges at least the PHY of BCM5704 (but not others).
514 */
515 flowstat = mii_phy_flowstatus(sc);
516 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
517 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
518
519 /* If copper link is up, get the negotiated speed/duplex. */
520 if (aux & BRGPHY_AUXSTS_LINK) {
521 mii->mii_media_status |= IFM_ACTIVE;
522 switch (aux & BRGPHY_AUXSTS_AN_RES) {
523 case BRGPHY_RES_1000FD:
524 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
525 case BRGPHY_RES_1000HD:
526 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
527 case BRGPHY_RES_100FD:
528 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
529 case BRGPHY_RES_100T4:
530 mii->mii_media_active |= IFM_100_T4; break;
531 case BRGPHY_RES_100HD:
532 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
533 case BRGPHY_RES_10FD:
534 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
535 case BRGPHY_RES_10HD:
536 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
537 default:
538 mii->mii_media_active |= IFM_NONE; break;
539 }
540
541 if ((mii->mii_media_active & IFM_FDX) != 0)
542 mii->mii_media_active |= flowstat;
543
544 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
545 (xstat & BRGPHY_1000STS_MSR) != 0)
546 mii->mii_media_active |= IFM_ETH_MASTER;
547 }
548 } else {
549 /* Todo: Add support for flow control. */
550 /* If serdes link is up, get the negotiated speed/duplex. */
551 if (bmsr & BRGPHY_BMSR_LINK) {
552 mii->mii_media_status |= IFM_ACTIVE;
553 }
554
555 /* Check the link speed/duplex based on the PHY type. */
556 if (bsc->serdes_flags & BRGPHY_5706S) {
557 mii->mii_media_active |= IFM_1000_SX;
558
559 /* If autoneg enabled, read negotiated duplex settings */
560 if (bmcr & BRGPHY_BMCR_AUTOEN) {
561 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
562 if (val & BRGPHY_SERDES_ANAR_FDX)
563 mii->mii_media_active |= IFM_FDX;
564 else
565 mii->mii_media_active |= IFM_HDX;
566 }
567 } else if (bsc->serdes_flags & BRGPHY_5708S) {
568 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
569 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
570
571 /* Check for MRBE auto-negotiated speed results. */
572 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
573 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
574 mii->mii_media_active |= IFM_10_FL; break;
575 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
576 mii->mii_media_active |= IFM_100_FX; break;
577 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
578 mii->mii_media_active |= IFM_1000_SX; break;
579 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
580 mii->mii_media_active |= IFM_2500_SX; break;
581 }
582
583 /* Check for MRBE auto-negotiated duplex results. */
584 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
585 mii->mii_media_active |= IFM_FDX;
586 else
587 mii->mii_media_active |= IFM_HDX;
588 } else if (bsc->serdes_flags & BRGPHY_5709S) {
589 /* Select GP Status Block of the AN MMD, get autoneg results. */
590 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
591 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
592
593 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
594 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
595
596 /* Check for MRBE auto-negotiated speed results. */
597 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
598 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
599 mii->mii_media_active |= IFM_10_FL; break;
600 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
601 mii->mii_media_active |= IFM_100_FX; break;
602 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
603 mii->mii_media_active |= IFM_1000_SX; break;
604 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
605 mii->mii_media_active |= IFM_2500_SX; break;
606 }
607
608 /* Check for MRBE auto-negotiated duplex results. */
609 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
610 mii->mii_media_active |= IFM_FDX;
611 else
612 mii->mii_media_active |= IFM_HDX;
613 }
614 }
615 }
616
617 static void
brgphy_mii_phy_auto(struct mii_softc * sc,int media)618 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
619 {
620 int anar, ktcr = 0;
621
622 PHY_RESET(sc);
623
624 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
625 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
626 if ((media & IFM_FLOW) != 0 ||
627 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
628 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
629 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
630 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
631 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
632 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
633 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
634 PHY_READ(sc, BRGPHY_MII_1000CTL);
635 } else {
636 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
637 if ((media & IFM_FLOW) != 0 ||
638 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
639 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
640 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
641 }
642
643 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
644 BRGPHY_BMCR_STARTNEG);
645 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
646 }
647
648 /* Enable loopback to force the link down. */
649 static void
brgphy_enable_loopback(struct mii_softc * sc)650 brgphy_enable_loopback(struct mii_softc *sc)
651 {
652 int i;
653
654 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
655 for (i = 0; i < 15000; i++) {
656 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
657 break;
658 DELAY(10);
659 }
660 }
661
662 /* Turn off tap power management on 5401. */
663 static void
bcm5401_load_dspcode(struct mii_softc * sc)664 bcm5401_load_dspcode(struct mii_softc *sc)
665 {
666 static const struct {
667 int reg;
668 uint16_t val;
669 } dspcode[] = {
670 { BRGPHY_MII_AUXCTL, 0x0c20 },
671 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
672 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
673 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
674 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
675 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
676 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
677 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
678 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
679 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
680 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
681 { 0, 0 },
682 };
683 int i;
684
685 for (i = 0; dspcode[i].reg != 0; i++)
686 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
687 DELAY(40);
688 }
689
690 static void
bcm5411_load_dspcode(struct mii_softc * sc)691 bcm5411_load_dspcode(struct mii_softc *sc)
692 {
693 static const struct {
694 int reg;
695 uint16_t val;
696 } dspcode[] = {
697 { 0x1c, 0x8c23 },
698 { 0x1c, 0x8ca3 },
699 { 0x1c, 0x8c23 },
700 { 0, 0 },
701 };
702 int i;
703
704 for (i = 0; dspcode[i].reg != 0; i++)
705 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
706 }
707
708 void
bcm54k2_load_dspcode(struct mii_softc * sc)709 bcm54k2_load_dspcode(struct mii_softc *sc)
710 {
711 static const struct {
712 int reg;
713 uint16_t val;
714 } dspcode[] = {
715 { 4, 0x01e1 },
716 { 9, 0x0300 },
717 { 0, 0 },
718 };
719 int i;
720
721 for (i = 0; dspcode[i].reg != 0; i++)
722 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
723
724 }
725
726 static void
brgphy_fixup_5704_a0_bug(struct mii_softc * sc)727 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
728 {
729 static const struct {
730 int reg;
731 uint16_t val;
732 } dspcode[] = {
733 { 0x1c, 0x8d68 },
734 { 0x1c, 0x8d68 },
735 { 0, 0 },
736 };
737 int i;
738
739 for (i = 0; dspcode[i].reg != 0; i++)
740 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
741 }
742
743 static void
brgphy_fixup_adc_bug(struct mii_softc * sc)744 brgphy_fixup_adc_bug(struct mii_softc *sc)
745 {
746 static const struct {
747 int reg;
748 uint16_t val;
749 } dspcode[] = {
750 { BRGPHY_MII_AUXCTL, 0x0c00 },
751 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
752 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
753 { 0, 0 },
754 };
755 int i;
756
757 for (i = 0; dspcode[i].reg != 0; i++)
758 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
759 }
760
761 static void
brgphy_fixup_adjust_trim(struct mii_softc * sc)762 brgphy_fixup_adjust_trim(struct mii_softc *sc)
763 {
764 static const struct {
765 int reg;
766 uint16_t val;
767 } dspcode[] = {
768 { BRGPHY_MII_AUXCTL, 0x0c00 },
769 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
770 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
771 { BRGPHY_MII_TEST1, 0x0014 },
772 { BRGPHY_MII_AUXCTL, 0x0400 },
773 { 0, 0 },
774 };
775 int i;
776
777 for (i = 0; dspcode[i].reg != 0; i++)
778 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
779 }
780
781 static void
brgphy_fixup_ber_bug(struct mii_softc * sc)782 brgphy_fixup_ber_bug(struct mii_softc *sc)
783 {
784 static const struct {
785 int reg;
786 uint16_t val;
787 } dspcode[] = {
788 { BRGPHY_MII_AUXCTL, 0x0c00 },
789 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
790 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
791 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
792 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
793 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
794 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
795 { BRGPHY_MII_AUXCTL, 0x0400 },
796 { 0, 0 },
797 };
798 int i;
799
800 for (i = 0; dspcode[i].reg != 0; i++)
801 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
802 }
803
804 static void
brgphy_fixup_crc_bug(struct mii_softc * sc)805 brgphy_fixup_crc_bug(struct mii_softc *sc)
806 {
807 static const struct {
808 int reg;
809 uint16_t val;
810 } dspcode[] = {
811 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
812 { 0x1c, 0x8c68 },
813 { 0x1c, 0x8d68 },
814 { 0x1c, 0x8c68 },
815 { 0, 0 },
816 };
817 int i;
818
819 for (i = 0; dspcode[i].reg != 0; i++)
820 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
821 }
822
823 static void
brgphy_fixup_jitter_bug(struct mii_softc * sc)824 brgphy_fixup_jitter_bug(struct mii_softc *sc)
825 {
826 static const struct {
827 int reg;
828 uint16_t val;
829 } dspcode[] = {
830 { BRGPHY_MII_AUXCTL, 0x0c00 },
831 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
832 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
833 { BRGPHY_MII_AUXCTL, 0x0400 },
834 { 0, 0 },
835 };
836 int i;
837
838 for (i = 0; dspcode[i].reg != 0; i++)
839 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
840 }
841
842 static void
brgphy_fixup_disable_early_dac(struct mii_softc * sc)843 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
844 {
845 uint32_t val;
846
847 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
848 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
849 val &= ~(1 << 8);
850 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
851
852 }
853
854 static void
brgphy_ethernet_wirespeed(struct mii_softc * sc)855 brgphy_ethernet_wirespeed(struct mii_softc *sc)
856 {
857 uint32_t val;
858
859 /* Enable Ethernet@WireSpeed. */
860 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
861 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
862 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
863 }
864
865 static void
brgphy_jumbo_settings(struct mii_softc * sc,u_long mtu)866 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
867 {
868 uint32_t val;
869
870 /* Set or clear jumbo frame settings in the PHY. */
871 if (mtu > ETHER_MAX_LEN) {
872 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
873 /* BCM5401 PHY cannot read-modify-write. */
874 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
875 } else {
876 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
877 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
878 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
879 val | BRGPHY_AUXCTL_LONG_PKT);
880 }
881
882 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
883 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
884 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
885 } else {
886 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
887 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
888 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
889 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
890
891 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
892 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
893 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
894 }
895 }
896
897 static void
brgphy_reset(struct mii_softc * sc)898 brgphy_reset(struct mii_softc *sc)
899 {
900 struct bge_softc *bge_sc = NULL;
901 struct bce_softc *bce_sc = NULL;
902 if_t ifp;
903 int i, val;
904
905 /*
906 * Perform a reset. Note that at least some Broadcom PHYs default to
907 * being powered down as well as isolated after a reset but don't work
908 * if one or both of these bits are cleared. However, they just work
909 * fine if both bits remain set, so we don't use mii_phy_reset() here.
910 */
911 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
912
913 /* Wait 100ms for it to complete. */
914 for (i = 0; i < 100; i++) {
915 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
916 break;
917 DELAY(1000);
918 }
919
920 /* Handle any PHY specific procedures following the reset. */
921 switch (sc->mii_mpd_oui) {
922 case MII_OUI_BROADCOM:
923 switch (sc->mii_mpd_model) {
924 case MII_MODEL_BROADCOM_BCM5400:
925 bcm5401_load_dspcode(sc);
926 break;
927 case MII_MODEL_BROADCOM_BCM5401:
928 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
929 bcm5401_load_dspcode(sc);
930 break;
931 case MII_MODEL_BROADCOM_BCM5411:
932 bcm5411_load_dspcode(sc);
933 break;
934 case MII_MODEL_BROADCOM_BCM54K2:
935 bcm54k2_load_dspcode(sc);
936 break;
937 }
938 break;
939 case MII_OUI_BROADCOM3:
940 switch (sc->mii_mpd_model) {
941 case MII_MODEL_BROADCOM3_BCM5717C:
942 case MII_MODEL_BROADCOM3_BCM5719C:
943 case MII_MODEL_BROADCOM3_BCM5720C:
944 case MII_MODEL_BROADCOM3_BCM57765:
945 return;
946 }
947 break;
948 case MII_OUI_BROADCOM4:
949 return;
950 }
951
952 ifp = sc->mii_pdata->mii_ifp;
953
954 /* Find the driver associated with this PHY. */
955 if (mii_phy_mac_match(sc, "bge"))
956 bge_sc = mii_phy_mac_softc(sc);
957 else if (mii_phy_mac_match(sc, "bce"))
958 bce_sc = mii_phy_mac_softc(sc);
959
960 if (bge_sc) {
961 /* Fix up various bugs */
962 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
963 brgphy_fixup_5704_a0_bug(sc);
964 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
965 brgphy_fixup_adc_bug(sc);
966 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
967 brgphy_fixup_adjust_trim(sc);
968 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
969 brgphy_fixup_ber_bug(sc);
970 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
971 brgphy_fixup_crc_bug(sc);
972 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
973 brgphy_fixup_jitter_bug(sc);
974
975 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
976 brgphy_jumbo_settings(sc, if_getmtu(ifp));
977
978 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
979 brgphy_ethernet_wirespeed(sc);
980
981 /* Enable Link LED on Dell boxes */
982 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
983 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
984 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
985 ~BRGPHY_PHY_EXTCTL_3_LED);
986 }
987
988 /* Adjust output voltage (From Linux driver) */
989 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
990 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
991 } else if (bce_sc) {
992 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
993 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
994
995 /* Store autoneg capabilities/results in digital block (Page 0) */
996 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
997 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
998 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
999 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
1000
1001 /* Enable fiber mode and autodetection */
1002 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1003 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1004 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1005 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1006
1007 /* Enable parallel detection */
1008 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1009 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1010 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1011
1012 /* Advertise 2.5G support through next page during autoneg */
1013 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1014 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1015 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1016 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1017
1018 /* Increase TX signal amplitude */
1019 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1020 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1021 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1022 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1023 BRGPHY_5708S_TX_MISC_PG5);
1024 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1025 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1026 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1027 BRGPHY_5708S_DIG_PG0);
1028 }
1029
1030 /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1031 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1032 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1033 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1034 BRGPHY_5708S_TX_MISC_PG5);
1035 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1036 bce_sc->bce_port_hw_cfg &
1037 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1038 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1039 BRGPHY_5708S_DIG_PG0);
1040 }
1041 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1042 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1043
1044 /* Select the SerDes Digital block of the AN MMD. */
1045 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1046 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1047 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1048 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1049 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1050
1051 /* Select the Over 1G block of the AN MMD. */
1052 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1053
1054 /* Enable autoneg "Next Page" to advertise 2.5G support. */
1055 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1056 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1057 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1058 else
1059 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1060 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1061
1062 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1063 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1064
1065 /* Enable MRBE speed autoneg. */
1066 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1067 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1068 BRGPHY_MRBE_MSG_PG5_NP_T2;
1069 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1070
1071 /* Select the Clause 73 User B0 block of the AN MMD. */
1072 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1073
1074 /* Enable MRBE speed autoneg. */
1075 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1076 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1077 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1078 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1079
1080 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1081 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1082 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1083 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1084 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1085 brgphy_fixup_disable_early_dac(sc);
1086
1087 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1088 brgphy_ethernet_wirespeed(sc);
1089 } else {
1090 brgphy_fixup_ber_bug(sc);
1091 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1092 brgphy_ethernet_wirespeed(sc);
1093 }
1094 }
1095 }
1096