1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 Intel Corporation 3 */ 4 5 #ifndef _IDXD_INTERNAL_H_ 6 #define _IDXD_INTERNAL_H_ 7 8 #include <rte_dmadev_pmd.h> 9 #include <rte_spinlock.h> 10 11 #include "idxd_hw_defs.h" 12 13 /** 14 * @file idxd_internal.h 15 * 16 * Internal data structures for the idxd/DSA driver for dmadev 17 * 18 * @warning 19 * @b EXPERIMENTAL: these structures and APIs may change without prior notice 20 */ 21 22 extern int idxd_pmd_logtype; 23 24 #define IDXD_PMD_LOG(level, fmt, args...) rte_log(RTE_LOG_ ## level, \ 25 idxd_pmd_logtype, "IDXD: %s(): " fmt "\n", __func__, ##args) 26 27 #define IDXD_PMD_DEBUG(fmt, args...) IDXD_PMD_LOG(DEBUG, fmt, ## args) 28 #define IDXD_PMD_INFO(fmt, args...) IDXD_PMD_LOG(INFO, fmt, ## args) 29 #define IDXD_PMD_ERR(fmt, args...) IDXD_PMD_LOG(ERR, fmt, ## args) 30 #define IDXD_PMD_WARN(fmt, args...) IDXD_PMD_LOG(WARNING, fmt, ## args) 31 32 struct idxd_pci_common { 33 rte_spinlock_t lk; 34 35 uint8_t wq_cfg_sz; 36 volatile struct rte_idxd_bar0 *regs; 37 volatile uint32_t *wq_regs_base; 38 volatile struct rte_idxd_grpcfg *grp_regs; 39 volatile void *portals; 40 }; 41 42 struct idxd_dmadev { 43 struct idxd_hw_desc *desc_ring; 44 45 /* counters to track the batches */ 46 unsigned short max_batches; 47 unsigned short batch_idx_read; 48 unsigned short batch_idx_write; 49 50 /* track descriptors and handles */ 51 unsigned short desc_ring_mask; 52 unsigned short ids_avail; /* handles for ops completed */ 53 unsigned short ids_returned; /* the read pointer for hdls/desc rings */ 54 unsigned short batch_start; /* start+size == write pointer for hdls/desc */ 55 unsigned short batch_size; 56 57 void *portal; /* address to write the batch descriptor */ 58 59 struct idxd_completion *batch_comp_ring; 60 unsigned short *batch_idx_ring; /* store where each batch ends */ 61 62 struct rte_dma_stats stats; 63 64 rte_iova_t batch_iova; /* base address of the batch comp ring */ 65 rte_iova_t desc_iova; /* base address of desc ring, needed for completions */ 66 67 unsigned short max_batch_size; 68 69 struct rte_dma_dev *dmadev; 70 struct rte_dma_vchan_conf qcfg; 71 uint8_t sva_support; 72 uint8_t qid; 73 74 union { 75 struct { 76 unsigned int dsa_id; 77 } bus; 78 79 struct idxd_pci_common *pci; 80 } u; 81 }; 82 83 int idxd_dmadev_create(const char *name, struct rte_device *dev, 84 const struct idxd_dmadev *base_idxd, const struct rte_dma_dev_ops *ops); 85 int idxd_dump(const struct rte_dma_dev *dev, FILE *f); 86 int idxd_configure(struct rte_dma_dev *dev, const struct rte_dma_conf *dev_conf, 87 uint32_t conf_sz); 88 int idxd_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, 89 const struct rte_dma_vchan_conf *qconf, uint32_t qconf_sz); 90 int idxd_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_info, 91 uint32_t size); 92 int idxd_enqueue_copy(void *dev_private, uint16_t qid, rte_iova_t src, 93 rte_iova_t dst, unsigned int length, uint64_t flags); 94 int idxd_enqueue_fill(void *dev_private, uint16_t qid, uint64_t pattern, 95 rte_iova_t dst, unsigned int length, uint64_t flags); 96 int idxd_submit(void *dev_private, uint16_t qid); 97 uint16_t idxd_completed(void *dev_private, uint16_t qid, uint16_t max_ops, 98 uint16_t *last_idx, bool *has_error); 99 uint16_t idxd_completed_status(void *dev_private, uint16_t qid __rte_unused, 100 uint16_t max_ops, uint16_t *last_idx, 101 enum rte_dma_status_code *status); 102 int idxd_stats_get(const struct rte_dma_dev *dev, uint16_t vchan, 103 struct rte_dma_stats *stats, uint32_t stats_sz); 104 int idxd_stats_reset(struct rte_dma_dev *dev, uint16_t vchan); 105 int idxd_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan, 106 enum rte_dma_vchan_status *status); 107 uint16_t idxd_burst_capacity(const void *dev_private, uint16_t vchan); 108 109 #endif /* _IDXD_INTERNAL_H_ */ 110