1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2013-2015 Intel Corporation
3 */
4
5 #ifndef _FM10K_H_
6 #define _FM10K_H_
7
8 #include <stdint.h>
9 #include <rte_mbuf.h>
10 #include <rte_mempool.h>
11 #include <rte_malloc.h>
12 #include <rte_spinlock.h>
13 #include "fm10k_logs.h"
14 #include "base/fm10k_type.h"
15
16 /* descriptor ring base addresses must be aligned to the following */
17 #define FM10K_ALIGN_RX_DESC 128
18 #define FM10K_ALIGN_TX_DESC 128
19
20 /* The maximum packet size that FM10K supports */
21 #define FM10K_MAX_PKT_SIZE (15 * 1024)
22
23 /* Minimum size of RX buffer FM10K supported */
24 #define FM10K_MIN_RX_BUF_SIZE 256
25
26 /* The maximum of SRIOV VFs per port supported */
27 #define FM10K_MAX_VF_NUM 64
28
29 /* number of descriptors must be a multiple of the following */
30 #define FM10K_MULT_RX_DESC FM10K_REQ_RX_DESCRIPTOR_MULTIPLE
31 #define FM10K_MULT_TX_DESC FM10K_REQ_TX_DESCRIPTOR_MULTIPLE
32
33 /* maximum size of descriptor rings */
34 #define FM10K_MAX_RX_RING_SZ (512 * 1024)
35 #define FM10K_MAX_TX_RING_SZ (512 * 1024)
36
37 /* minimum and maximum number of descriptors in a ring */
38 #define FM10K_MIN_RX_DESC 32
39 #define FM10K_MIN_TX_DESC 32
40 #define FM10K_MAX_RX_DESC (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))
41 #define FM10K_MAX_TX_DESC (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))
42
43 #define FM10K_TX_MAX_SEG UINT8_MAX
44 #define FM10K_TX_MAX_MTU_SEG UINT8_MAX
45
46 /*
47 * byte alignment for HW RX data buffer
48 * Datasheet requires RX buffer addresses shall either be 512-byte aligned or
49 * be 8-byte aligned but without crossing host memory pages (4KB alignment
50 * boundaries). Satisfy first option.
51 */
52 #define FM10K_RX_DATABUF_ALIGN 512
53
54 /*
55 * threshold default, min, max, and divisor constraints
56 * the configured values must satisfy the following:
57 * MIN <= value <= MAX
58 * DIV % value == 0
59 */
60 #define FM10K_RX_FREE_THRESH_DEFAULT(rxq) 32
61 #define FM10K_RX_FREE_THRESH_MIN(rxq) 1
62 #define FM10K_RX_FREE_THRESH_MAX(rxq) ((rxq)->nb_desc - 1)
63 #define FM10K_RX_FREE_THRESH_DIV(rxq) ((rxq)->nb_desc)
64
65 #define FM10K_TX_FREE_THRESH_DEFAULT(txq) 32
66 #define FM10K_TX_FREE_THRESH_MIN(txq) 1
67 #define FM10K_TX_FREE_THRESH_MAX(txq) ((txq)->nb_desc - 3)
68 #define FM10K_TX_FREE_THRESH_DIV(txq) 0
69
70 #define FM10K_DEFAULT_RX_PTHRESH 8
71 #define FM10K_DEFAULT_RX_HTHRESH 8
72 #define FM10K_DEFAULT_RX_WTHRESH 0
73
74 #define FM10K_DEFAULT_TX_PTHRESH 32
75 #define FM10K_DEFAULT_TX_HTHRESH 0
76 #define FM10K_DEFAULT_TX_WTHRESH 0
77
78 #define FM10K_TX_RS_THRESH_DEFAULT(txq) 32
79 #define FM10K_TX_RS_THRESH_MIN(txq) 1
80 #define FM10K_TX_RS_THRESH_MAX(txq) \
81 RTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)
82 #define FM10K_TX_RS_THRESH_DIV(txq) ((txq)->nb_desc)
83
84 /* Maximum number of MAC addresses per PF/VF */
85 #define FM10K_MAX_MACADDR_NUM 64
86
87 #define FM10K_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
88 #define FM10K_VFTA_SIZE (4096 / FM10K_UINT32_BIT_SIZE)
89
90 /* vlan_id is a 12 bit number.
91 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
92 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
93 * The higher 7 bit val specifies VFTA array index.
94 */
95 #define FM10K_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
96 #define FM10K_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
97
98 #define RTE_FM10K_RXQ_REARM_THRESH 32
99 #define RTE_FM10K_VPMD_TX_BURST 32
100 #define RTE_FM10K_MAX_RX_BURST RTE_FM10K_RXQ_REARM_THRESH
101 #define RTE_FM10K_TX_MAX_FREE_BUF_SZ 64
102 #define RTE_FM10K_DESCS_PER_LOOP 4
103
104 #define FM10K_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
105 #define FM10K_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
106
107 struct fm10k_macvlan_filter_info {
108 uint16_t vlan_num; /* Total VLAN number */
109 uint16_t mac_num; /* Total mac number */
110 uint16_t nb_queue_pools; /* Active queue pools number */
111 /* VMDQ ID for each MAC address */
112 uint8_t mac_vmdq_id[FM10K_MAX_MACADDR_NUM];
113 uint32_t vfta[FM10K_VFTA_SIZE]; /* VLAN bitmap */
114 };
115
116 struct fm10k_dev_info {
117 volatile uint32_t enable;
118 volatile uint32_t glort;
119 /* Protect the mailbox to avoid race condition */
120 rte_spinlock_t mbx_lock;
121 struct fm10k_macvlan_filter_info macvlan;
122 /* Flag to indicate if RX vector conditions satisfied */
123 bool rx_vec_allowed;
124 bool sm_down;
125 };
126
127 /*
128 * Structure to store private data for each driver instance.
129 */
130 struct fm10k_adapter {
131 struct fm10k_hw hw;
132 struct fm10k_hw_stats stats;
133 struct fm10k_dev_info info;
134 };
135
136 #define FM10K_DEV_PRIVATE_TO_HW(adapter) \
137 (&((struct fm10k_adapter *)adapter)->hw)
138
139 #define FM10K_DEV_PRIVATE_TO_STATS(adapter) \
140 (&((struct fm10k_adapter *)adapter)->stats)
141
142 #define FM10K_DEV_PRIVATE_TO_INFO(adapter) \
143 (&((struct fm10k_adapter *)adapter)->info)
144
145 #define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \
146 (&(((struct fm10k_adapter *)adapter)->info.mbx_lock))
147
148 #define FM10K_DEV_PRIVATE_TO_MACVLAN(adapter) \
149 (&(((struct fm10k_adapter *)adapter)->info.macvlan))
150
151 struct fm10k_rx_queue {
152 struct rte_mempool *mp;
153 struct rte_mbuf **sw_ring;
154 volatile union fm10k_rx_desc *hw_ring;
155 struct rte_mbuf *pkt_first_seg; /* First segment of current packet. */
156 struct rte_mbuf *pkt_last_seg; /* Last segment of current packet. */
157 uint64_t hw_ring_phys_addr;
158 uint64_t mbuf_initializer; /* value to init mbufs */
159 /* need to alloc dummy mbuf, for wraparound when scanning hw ring */
160 struct rte_mbuf fake_mbuf;
161 uint16_t next_dd;
162 uint16_t next_alloc;
163 uint16_t next_trigger;
164 uint16_t alloc_thresh;
165 volatile uint32_t *tail_ptr;
166 uint16_t nb_desc;
167 /* Number of faked desc added at the tail for Vector RX function */
168 uint16_t nb_fake_desc;
169 uint16_t queue_id;
170 /* Below 2 fields only valid in case vPMD is applied. */
171 uint16_t rxrearm_nb; /* number of remaining to be re-armed */
172 uint16_t rxrearm_start; /* the idx we start the re-arming from */
173 uint16_t rx_using_sse; /* indicates that vector RX is in use */
174 uint16_t port_id;
175 uint8_t drop_en;
176 uint8_t rx_deferred_start; /* don't start this queue in dev start. */
177 uint16_t rx_ftag_en; /* indicates FTAG RX supported */
178 uint64_t offloads; /* offloads of RTE_ETH_RX_OFFLOAD_* */
179 };
180
181 /*
182 * a FIFO is used to track which descriptors have their RS bit set for Tx
183 * queues which are configured to allow multiple descriptors per packet
184 */
185 struct fifo {
186 uint16_t *list;
187 uint16_t *head;
188 uint16_t *tail;
189 uint16_t *endp;
190 };
191
192 struct fm10k_txq_ops;
193
194 struct fm10k_tx_queue {
195 struct rte_mbuf **sw_ring;
196 struct fm10k_tx_desc *hw_ring;
197 uint64_t hw_ring_phys_addr;
198 struct fifo rs_tracker;
199 const struct fm10k_txq_ops *ops; /* txq ops */
200 uint16_t last_free;
201 uint16_t next_free;
202 uint16_t nb_free;
203 uint16_t nb_used;
204 uint16_t free_thresh;
205 uint16_t rs_thresh;
206 /* Below 2 fields only valid in case vPMD is applied. */
207 uint16_t next_rs; /* Next pos to set RS flag */
208 uint16_t next_dd; /* Next pos to check DD flag */
209 volatile uint32_t *tail_ptr;
210 uint64_t offloads; /* Offloads of RTE_ETH_TX_OFFLOAD_* */
211 uint16_t nb_desc;
212 uint16_t port_id;
213 uint8_t tx_deferred_start; /** don't start this queue in dev start. */
214 uint16_t queue_id;
215 uint16_t tx_ftag_en; /* indicates FTAG TX supported */
216 };
217
218 struct fm10k_txq_ops {
219 void (*reset)(struct fm10k_tx_queue *txq);
220 };
221
222 #define MBUF_DMA_ADDR(mb) \
223 ((uint64_t) ((mb)->buf_iova + (mb)->data_off))
224
225 /* enforce 512B alignment on default Rx DMA addresses */
226 #define MBUF_DMA_ADDR_DEFAULT(mb) \
227 ((uint64_t) RTE_ALIGN(((mb)->buf_iova + RTE_PKTMBUF_HEADROOM),\
228 FM10K_RX_DATABUF_ALIGN))
229
fifo_reset(struct fifo * fifo,uint32_t len)230 static inline void fifo_reset(struct fifo *fifo, uint32_t len)
231 {
232 fifo->head = fifo->tail = fifo->list;
233 fifo->endp = fifo->list + len;
234 }
235
fifo_insert(struct fifo * fifo,uint16_t val)236 static inline void fifo_insert(struct fifo *fifo, uint16_t val)
237 {
238 *fifo->head = val;
239 if (++fifo->head == fifo->endp)
240 fifo->head = fifo->list;
241 }
242
243 /* do not worry about list being empty since we only check it once we know
244 * we have used enough descriptors to set the RS bit at least once */
fifo_peek(struct fifo * fifo)245 static inline uint16_t fifo_peek(struct fifo *fifo)
246 {
247 return *fifo->tail;
248 }
249
fifo_remove(struct fifo * fifo)250 static inline uint16_t fifo_remove(struct fifo *fifo)
251 {
252 uint16_t val;
253 val = *fifo->tail;
254 if (++fifo->tail == fifo->endp)
255 fifo->tail = fifo->list;
256 return val;
257 }
258
259 static inline void
fm10k_pktmbuf_reset(struct rte_mbuf * mb,uint16_t in_port)260 fm10k_pktmbuf_reset(struct rte_mbuf *mb, uint16_t in_port)
261 {
262 rte_mbuf_refcnt_set(mb, 1);
263 mb->next = NULL;
264 mb->nb_segs = 1;
265
266 /* enforce 512B alignment on default Rx virtual addresses */
267 mb->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb->buf_addr +
268 RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
269 - (char *)mb->buf_addr);
270 mb->port = in_port;
271 }
272
273 /*
274 * Verify Rx packet buffer alignment is valid.
275 *
276 * Hardware requires specific alignment for Rx packet buffers. At
277 * least one of the following two conditions must be satisfied.
278 * 1. Address is 512B aligned
279 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
280 *
281 * Return 1 if buffer alignment satisfies at least one condition,
282 * otherwise return 0.
283 *
284 * Note: Alignment is checked by the driver when the Rx queue is reset. It
285 * is assumed that if an entire descriptor ring can be filled with
286 * buffers containing valid alignment, then all buffers in that mempool
287 * have valid address alignment. It is the responsibility of the user
288 * to ensure all buffers have valid alignment, as it is the user who
289 * creates the mempool.
290 * Note: It is assumed the buffer needs only to store a maximum size Ethernet
291 * frame.
292 */
293 static inline int
fm10k_addr_alignment_valid(struct rte_mbuf * mb)294 fm10k_addr_alignment_valid(struct rte_mbuf *mb)
295 {
296 uint64_t addr = MBUF_DMA_ADDR_DEFAULT(mb);
297 uint64_t boundary1, boundary2;
298
299 /* 512B aligned? */
300 if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr)
301 return 1;
302
303 /* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */
304 if (RTE_ALIGN(addr, 8) == addr) {
305 boundary1 = RTE_ALIGN_FLOOR(addr, 4096);
306 boundary2 = RTE_ALIGN_FLOOR(addr + RTE_ETHER_MAX_VLAN_FRAME_LEN,
307 4096);
308 if (boundary1 == boundary2)
309 return 1;
310 }
311
312 PMD_INIT_LOG(ERR, "Error: Invalid buffer alignment!");
313
314 return 0;
315 }
316
317 /* Rx and Tx prototypes */
318 uint16_t fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
319 uint16_t nb_pkts);
320
321 uint16_t fm10k_recv_scattered_pkts(void *rx_queue,
322 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
323
324 uint32_t
325 fm10k_dev_rx_queue_count(void *rx_queue);
326
327 int
328 fm10k_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
329
330 int
331 fm10k_dev_tx_descriptor_status(void *rx_queue, uint16_t offset);
332
333
334 uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
335 uint16_t nb_pkts);
336
337 uint16_t fm10k_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
338 uint16_t nb_pkts);
339
340 int fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq);
341 int fm10k_rx_vec_condition_check(struct rte_eth_dev *);
342 void fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq);
343 uint16_t fm10k_recv_pkts_vec(void *, struct rte_mbuf **, uint16_t);
344 uint16_t fm10k_recv_scattered_pkts_vec(void *, struct rte_mbuf **,
345 uint16_t);
346 uint16_t fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
347 uint16_t nb_pkts);
348 void fm10k_txq_vec_setup(struct fm10k_tx_queue *txq);
349 int fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq);
350
351 #endif
352