1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 #define ICE_MAX_VSI 768 13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 15 16 struct ice_aqc_generic { 17 __le32 param0; 18 __le32 param1; 19 __le32 addr_high; 20 __le32 addr_low; 21 }; 22 23 /* Get version (direct 0x0001) */ 24 struct ice_aqc_get_ver { 25 __le32 rom_ver; 26 __le32 fw_build; 27 u8 fw_branch; 28 u8 fw_major; 29 u8 fw_minor; 30 u8 fw_patch; 31 u8 api_branch; 32 u8 api_major; 33 u8 api_minor; 34 u8 api_patch; 35 }; 36 37 /* Send driver version (indirect 0x0002) */ 38 struct ice_aqc_driver_ver { 39 u8 major_ver; 40 u8 minor_ver; 41 u8 build_ver; 42 u8 subbuild_ver; 43 u8 reserved[4]; 44 __le32 addr_high; 45 __le32 addr_low; 46 }; 47 48 /* Queue Shutdown (direct 0x0003) */ 49 struct ice_aqc_q_shutdown { 50 u8 driver_unloading; 51 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 52 u8 reserved[15]; 53 }; 54 55 /* Request resource ownership (direct 0x0008) 56 * Release resource ownership (direct 0x0009) 57 */ 58 struct ice_aqc_req_res { 59 __le16 res_id; 60 #define ICE_AQC_RES_ID_NVM 1 61 #define ICE_AQC_RES_ID_SDP 2 62 #define ICE_AQC_RES_ID_CHNG_LOCK 3 63 #define ICE_AQC_RES_ID_GLBL_LOCK 4 64 __le16 access_type; 65 #define ICE_AQC_RES_ACCESS_READ 1 66 #define ICE_AQC_RES_ACCESS_WRITE 2 67 68 /* Upon successful completion, FW writes this value and driver is 69 * expected to release resource before timeout. This value is provided 70 * in milliseconds. 71 */ 72 __le32 timeout; 73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 77 /* For SDP: pin ID of the SDP */ 78 __le32 res_number; 79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 80 __le16 status; 81 #define ICE_AQ_RES_GLBL_SUCCESS 0 82 #define ICE_AQ_RES_GLBL_IN_PROG 1 83 #define ICE_AQ_RES_GLBL_DONE 2 84 u8 reserved[2]; 85 }; 86 87 /* Get function capabilities (indirect 0x000A) 88 * Get device capabilities (indirect 0x000B) 89 */ 90 struct ice_aqc_list_caps { 91 u8 cmd_flags; 92 u8 pf_index; 93 u8 reserved[2]; 94 __le32 count; 95 __le32 addr_high; 96 __le32 addr_low; 97 }; 98 99 /* Device/Function buffer entry, repeated per reported capability */ 100 struct ice_aqc_list_caps_elem { 101 __le16 cap; 102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_1588 0x0046 112 #define ICE_AQC_CAPS_MAX_MTU 0x0047 113 #define ICE_AQC_CAPS_IWARP 0x0051 114 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 115 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 116 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 117 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 118 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 119 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 120 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 121 122 u8 major_ver; 123 u8 minor_ver; 124 /* Number of resources described by this capability */ 125 __le32 number; 126 /* Only meaningful for some types of resources */ 127 __le32 logical_id; 128 /* Only meaningful for some types of resources */ 129 __le32 phys_id; 130 __le64 rsvd1; 131 __le64 rsvd2; 132 }; 133 134 /* Manage MAC address, read command - indirect (0x0107) 135 * This struct is also used for the response 136 */ 137 struct ice_aqc_manage_mac_read { 138 __le16 flags; /* Zeroed by device driver */ 139 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 140 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 141 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 142 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 143 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 144 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 145 #define ICE_AQC_MAN_MAC_READ_S 4 146 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 147 u8 rsvd[2]; 148 u8 num_addr; /* Used in response */ 149 u8 rsvd1[3]; 150 __le32 addr_high; 151 __le32 addr_low; 152 }; 153 154 /* Response buffer format for manage MAC read command */ 155 struct ice_aqc_manage_mac_read_resp { 156 u8 lport_num; 157 u8 addr_type; 158 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 159 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 160 u8 mac_addr[ETH_ALEN]; 161 }; 162 163 /* Manage MAC address, write command - direct (0x0108) */ 164 struct ice_aqc_manage_mac_write { 165 u8 rsvd; 166 u8 flags; 167 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 168 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 169 #define ICE_AQC_MAN_MAC_WR_S 6 170 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 171 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 172 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 173 /* byte stream in network order */ 174 u8 mac_addr[ETH_ALEN]; 175 __le32 addr_high; 176 __le32 addr_low; 177 }; 178 179 /* Clear PXE Command and response (direct 0x0110) */ 180 struct ice_aqc_clear_pxe { 181 u8 rx_cnt; 182 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 183 u8 reserved[15]; 184 }; 185 186 /* Configure No-Drop Policy Command (direct 0x0112) */ 187 struct ice_aqc_config_no_drop_policy { 188 u8 opts; 189 #define ICE_AQC_FORCE_NO_DROP BIT(0) 190 u8 rsvd[15]; 191 }; 192 193 /* Get switch configuration (0x0200) */ 194 struct ice_aqc_get_sw_cfg { 195 /* Reserved for command and copy of request flags for response */ 196 __le16 flags; 197 /* First desc in case of command and next_elem in case of response 198 * In case of response, if it is not zero, means all the configuration 199 * was not returned and new command shall be sent with this value in 200 * the 'first desc' field 201 */ 202 __le16 element; 203 /* Reserved for command, only used for response */ 204 __le16 num_elems; 205 __le16 rsvd; 206 __le32 addr_high; 207 __le32 addr_low; 208 }; 209 210 /* Each entry in the response buffer is of the following type: */ 211 struct ice_aqc_get_sw_cfg_resp_elem { 212 /* VSI/Port Number */ 213 __le16 vsi_port_num; 214 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 215 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 216 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 217 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 218 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 219 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 220 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 221 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 222 223 /* SWID VSI/Port belongs to */ 224 __le16 swid; 225 226 /* Bit 14..0 : PF/VF number VSI belongs to 227 * Bit 15 : VF indication bit 228 */ 229 __le16 pf_vf_num; 230 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 231 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 232 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 233 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 234 }; 235 236 /* Set Port parameters, (direct, 0x0203) */ 237 struct ice_aqc_set_port_params { 238 __le16 cmd_flags; 239 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 240 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 241 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 242 __le16 bad_frame_vsi; 243 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 244 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 245 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 246 __le16 swid; 247 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 248 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 249 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 250 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 251 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 252 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 253 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 254 u8 reserved[10]; 255 }; 256 257 /* These resource type defines are used for all switch resource 258 * commands where a resource type is required, such as: 259 * Get Resource Allocation command (indirect 0x0204) 260 * Allocate Resources command (indirect 0x0208) 261 * Free Resources command (indirect 0x0209) 262 * Get Allocated Resource Descriptors Command (indirect 0x020A) 263 */ 264 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 265 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 266 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 267 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 268 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 269 #define ICE_AQC_RES_TYPE_RECIPE 0x05 270 #define ICE_AQC_RES_TYPE_PROFILE 0x06 271 #define ICE_AQC_RES_TYPE_SWID 0x07 272 #define ICE_AQC_RES_TYPE_VSI 0x08 273 #define ICE_AQC_RES_TYPE_FLU 0x09 274 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 275 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 276 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 277 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 278 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 279 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 280 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 281 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 282 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 283 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 284 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 285 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 286 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 287 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 288 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 289 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 290 /* Resource types 0x62-67 are reserved for Hash profile builder */ 291 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 292 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 293 294 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 295 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 296 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 297 298 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 299 300 #define ICE_AQC_RES_TYPE_S 0 301 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 302 303 /* Get Resource Allocation command (indirect 0x0204) */ 304 struct ice_aqc_get_res_alloc { 305 __le16 resp_elem_num; /* Used in response, reserved in command */ 306 u8 reserved[6]; 307 __le32 addr_high; 308 __le32 addr_low; 309 }; 310 311 /* Get Resource Allocation Response Buffer per response */ 312 struct ice_aqc_get_res_resp_elem { 313 __le16 res_type; /* Types defined above cmd 0x0204 */ 314 __le16 total_capacity; /* Resources available to all PF's */ 315 __le16 total_function; /* Resources allocated for a PF */ 316 __le16 total_shared; /* Resources allocated as shared */ 317 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 318 }; 319 320 /* Allocate Resources command (indirect 0x0208) 321 * Free Resources command (indirect 0x0209) 322 */ 323 struct ice_aqc_alloc_free_res_cmd { 324 __le16 num_entries; /* Number of Resource entries */ 325 u8 reserved[6]; 326 __le32 addr_high; 327 __le32 addr_low; 328 }; 329 330 /* Resource descriptor */ 331 struct ice_aqc_res_elem { 332 union { 333 __le16 sw_resp; 334 __le16 flu_resp; 335 } e; 336 }; 337 338 /* Buffer for Allocate/Free Resources commands */ 339 struct ice_aqc_alloc_free_res_elem { 340 __le16 res_type; /* Types defined above cmd 0x0204 */ 341 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 342 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 343 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 344 __le16 num_elems; 345 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 346 }; 347 348 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 349 struct ice_aqc_get_allocd_res_desc { 350 union { 351 struct { 352 __le16 res; /* Types defined above cmd 0x0204 */ 353 __le16 first_desc; 354 __le32 reserved; 355 } cmd; 356 struct { 357 __le16 res; 358 __le16 next_desc; 359 __le16 num_desc; 360 __le16 reserved; 361 } resp; 362 } ops; 363 __le32 addr_high; 364 __le32 addr_low; 365 }; 366 367 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 368 struct ice_aqc_set_vlan_mode { 369 u8 reserved; 370 u8 l2tag_prio_tagging; 371 #define ICE_AQ_VLAN_PRIO_TAG_S 0 372 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 373 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 374 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 375 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 376 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 377 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 378 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 379 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 380 u8 l2tag_reserved[64]; 381 u8 rdma_packet; 382 #define ICE_AQ_VLAN_RDMA_TAG_S 0 383 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 384 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 385 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 386 u8 rdma_reserved[2]; 387 u8 mng_vlan_prot_id; 388 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 389 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 390 u8 prot_id_reserved[30]; 391 }; 392 393 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 394 struct ice_aqc_get_vlan_mode { 395 u8 vlan_mode; 396 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 397 u8 l2tag_prio_tagging; 398 u8 reserved[98]; 399 }; 400 401 /* Add VSI (indirect 0x0210) 402 * Update VSI (indirect 0x0211) 403 * Get VSI (indirect 0x0212) 404 * Free VSI (indirect 0x0213) 405 */ 406 struct ice_aqc_add_get_update_free_vsi { 407 __le16 vsi_num; 408 #define ICE_AQ_VSI_NUM_S 0 409 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 410 #define ICE_AQ_VSI_IS_VALID BIT(15) 411 __le16 cmd_flags; 412 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 413 u8 vf_id; 414 u8 reserved; 415 __le16 vsi_flags; 416 #define ICE_AQ_VSI_TYPE_S 0 417 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 418 #define ICE_AQ_VSI_TYPE_VF 0x0 419 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 420 #define ICE_AQ_VSI_TYPE_PF 0x2 421 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 422 __le32 addr_high; 423 __le32 addr_low; 424 }; 425 426 /* Response descriptor for: 427 * Add VSI (indirect 0x0210) 428 * Update VSI (indirect 0x0211) 429 * Free VSI (indirect 0x0213) 430 */ 431 struct ice_aqc_add_update_free_vsi_resp { 432 __le16 vsi_num; 433 __le16 ext_status; 434 __le16 vsi_used; 435 __le16 vsi_free; 436 __le32 addr_high; 437 __le32 addr_low; 438 }; 439 440 struct ice_aqc_get_vsi_resp { 441 __le16 vsi_num; 442 u8 vf_id; 443 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 444 * These are found above in struct ice_aqc_add_get_update_free_vsi. 445 */ 446 u8 vsi_flags; 447 __le16 vsi_used; 448 __le16 vsi_free; 449 __le32 addr_high; 450 __le32 addr_low; 451 }; 452 453 struct ice_aqc_vsi_props { 454 __le16 valid_sections; 455 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 456 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 457 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 458 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 459 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 460 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 461 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 462 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 463 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 464 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10) 465 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 466 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 467 /* switch section */ 468 u8 sw_id; 469 u8 sw_flags; 470 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 471 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 472 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 473 u8 sw_flags2; 474 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 475 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 476 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 477 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 478 u8 veb_stat_id; 479 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 480 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 481 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 482 /* security section */ 483 u8 sec_flags; 484 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 485 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 486 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 487 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 488 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 489 u8 sec_reserved; 490 /* VLAN section */ 491 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 492 u8 inner_vlan_reserved[2]; 493 u8 inner_vlan_flags; 494 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 495 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 496 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 497 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 498 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 499 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 500 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 501 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 502 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 503 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 504 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 505 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 506 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 507 u8 inner_vlan_reserved2[3]; 508 /* ingress egress up sections */ 509 __le32 ingress_table; /* bitmap, 3 bits per up */ 510 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 511 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 512 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 513 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 514 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 515 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 516 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 517 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 518 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 519 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 520 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 521 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 522 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 523 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 524 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 525 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 526 __le32 egress_table; /* same defines as for ingress table */ 527 /* outer tags section */ 528 __le16 port_based_outer_vlan; 529 u8 outer_vlan_flags; 530 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 531 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 532 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 533 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 534 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 535 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 536 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 537 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 538 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 539 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 540 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 541 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 542 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 543 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(6) 544 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 545 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 546 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 547 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 548 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 549 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 550 u8 outer_vlan_reserved; 551 /* queue mapping section */ 552 __le16 mapping_flags; 553 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 554 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 555 __le16 q_mapping[16]; 556 #define ICE_AQ_VSI_Q_S 0 557 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 558 __le16 tc_mapping[8]; 559 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 560 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 561 #define ICE_AQ_VSI_TC_Q_NUM_S 11 562 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 563 /* queueing option section */ 564 u8 q_opt_rss; 565 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 566 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 567 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 568 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 569 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 570 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 571 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 572 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 573 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 574 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 575 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 576 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 577 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 578 u8 q_opt_tc; 579 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 580 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 581 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 582 u8 q_opt_flags; 583 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 584 u8 q_opt_reserved[3]; 585 /* outer up section */ 586 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 587 /* ACL section */ 588 __le16 acl_def_act; 589 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0 590 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S) 591 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4 592 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S) 593 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8 594 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S) 595 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12 596 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S) 597 /* flow director section */ 598 __le16 fd_options; 599 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 600 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 601 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 602 __le16 max_fd_fltr_dedicated; 603 __le16 max_fd_fltr_shared; 604 __le16 fd_def_q; 605 #define ICE_AQ_VSI_FD_DEF_Q_S 0 606 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 607 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 608 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 609 __le16 fd_report_opt; 610 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 611 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 612 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 613 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 614 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 615 /* PASID section */ 616 __le32 pasid_id; 617 #define ICE_AQ_VSI_PASID_ID_S 0 618 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 619 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 620 u8 reserved[24]; 621 }; 622 623 /* Add/update mirror rule - direct (0x0260) */ 624 #define ICE_AQC_RULE_ID_VALID_S 7 625 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 626 #define ICE_AQC_RULE_ID_S 0 627 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 628 629 /* Following defines to be used while processing caller specified mirror list 630 * of VSI indexes. 631 */ 632 /* Action: Byte.bit (1.7) 633 * 0 = Remove VSI from mirror rule 634 * 1 = Add VSI to mirror rule 635 */ 636 #define ICE_AQC_RULE_ACT_S 15 637 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 638 /* Action: 1.2:0.0 = Mirrored VSI */ 639 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 640 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 641 642 /* This is to be used by add/update mirror rule Admin Queue command. 643 * In case of add mirror rule - if rule ID is specified as 644 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 645 * If specified rule_id is valid, then it is used. If specified rule_id 646 * is in use then new mirroring rule is added. 647 */ 648 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 649 650 struct ice_aqc_add_update_mir_rule { 651 __le16 rule_id; 652 653 __le16 rule_type; 654 #define ICE_AQC_RULE_TYPE_S 0 655 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 656 /* VPORT ingress/egress */ 657 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 658 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 659 /* Physical port ingress mirroring. 660 * All traffic received by this port 661 */ 662 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 663 /* Physical port egress mirroring. All traffic sent by this port */ 664 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 665 666 /* Number of mirrored entries. 667 * The values are in the command buffer 668 */ 669 __le16 num_entries; 670 671 /* Destination VSI */ 672 __le16 dest; 673 __le32 addr_high; 674 __le32 addr_low; 675 }; 676 677 /* Delete mirror rule - direct(0x0261) */ 678 struct ice_aqc_delete_mir_rule { 679 __le16 rule_id; 680 __le16 rsvd; 681 682 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 683 * the PF allocated resources, otherwise it is returned to the 684 * shared pool 685 */ 686 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 687 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 688 __le16 flags; 689 690 u8 reserved[10]; 691 }; 692 693 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 694 /* This structure holds get storm configuration response and same structure 695 * is used to perform set_storm_cfg 696 */ 697 struct ice_aqc_storm_cfg { 698 __le32 bcast_thresh_size; 699 __le32 mcast_thresh_size; 700 /* Bit 18:0 - Traffic upper threshold size 701 * Bit 31:19 - Reserved 702 */ 703 #define ICE_AQ_THRESHOLD_S 0 704 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 705 706 __le32 storm_ctrl_ctrl; 707 /* Bit 0: MDIPW - Drop Multicast packets in previous window 708 * Bit 1: MDICW - Drop multicast packets in current window 709 * Bit 2: BDIPW - Drop broadcast packets in previous window 710 * Bit 3: BDICW - Drop broadcast packets in current window 711 */ 712 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 713 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 714 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 715 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 716 /* Bit 7:5 : Reserved */ 717 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 718 * interval size for applying ingress broadcast or multicast storm 719 * control. 720 */ 721 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 722 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 723 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 724 __le32 reserved; 725 }; 726 727 #define ICE_MAX_NUM_RECIPES 64 728 729 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 730 struct ice_aqc_add_get_recipe { 731 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 732 __le16 return_index; /* Input, used for Get cmd only */ 733 u8 reserved[4]; 734 __le32 addr_high; 735 __le32 addr_low; 736 }; 737 738 struct ice_aqc_recipe_content { 739 u8 rid; 740 #define ICE_AQ_RECIPE_ID_S 0 741 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 742 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 743 #define ICE_AQ_SW_ID_LKUP_IDX 0 744 u8 lkup_indx[5]; 745 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 746 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 747 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 748 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 749 __le16 mask[5]; 750 u8 result_indx; 751 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 752 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 753 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 754 u8 rsvd0[3]; 755 u8 act_ctrl_join_priority; 756 u8 act_ctrl_fwd_priority; 757 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 758 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 759 u8 act_ctrl; 760 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 761 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 762 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 763 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 764 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 765 u8 rsvd1; 766 __le32 dflt_act; 767 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 768 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 769 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 770 }; 771 772 struct ice_aqc_recipe_data_elem { 773 u8 recipe_indx; 774 u8 resp_bits; 775 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 776 u8 rsvd0[2]; 777 u8 recipe_bitmap[8]; 778 u8 rsvd1[4]; 779 struct ice_aqc_recipe_content content; 780 u8 rsvd2[20]; 781 }; 782 783 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 784 struct ice_aqc_recipe_to_profile { 785 __le16 profile_id; 786 u8 rsvd[6]; 787 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES); 788 }; 789 790 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 791 */ 792 struct ice_aqc_sw_rules { 793 /* ops: add switch rules, referring the number of rules. 794 * ops: update switch rules, referring the number of filters 795 * ops: remove switch rules, referring the entry index. 796 * ops: get switch rules, referring to the number of filters. 797 */ 798 __le16 num_rules_fltr_entry_index; 799 u8 reserved[6]; 800 __le32 addr_high; 801 __le32 addr_low; 802 }; 803 804 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 805 * This structures describes the lookup rules and associated actions. "index" 806 * is returned as part of a response to a successful Add command, and can be 807 * used to identify the rule for Update/Get/Remove commands. 808 */ 809 struct ice_sw_rule_lkup_rx_tx { 810 __le16 recipe_id; 811 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 812 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 813 __le16 src; 814 __le32 act; 815 816 /* Bit 0:1 - Action type */ 817 #define ICE_SINGLE_ACT_TYPE_S 0x00 818 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 819 820 /* Bit 2 - Loop back enable 821 * Bit 3 - LAN enable 822 */ 823 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 824 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 825 826 /* Action type = 0 - Forward to VSI or VSI list */ 827 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 828 829 #define ICE_SINGLE_ACT_VSI_ID_S 4 830 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 831 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 832 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 833 /* This bit needs to be set if action is forward to VSI list */ 834 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 835 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 836 #define ICE_SINGLE_ACT_DROP BIT(18) 837 838 /* Action type = 1 - Forward to Queue of Queue group */ 839 #define ICE_SINGLE_ACT_TO_Q 0x1 840 #define ICE_SINGLE_ACT_Q_INDEX_S 4 841 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 842 #define ICE_SINGLE_ACT_Q_REGION_S 15 843 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 844 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 845 846 /* Action type = 2 - Prune */ 847 #define ICE_SINGLE_ACT_PRUNE 0x2 848 #define ICE_SINGLE_ACT_EGRESS BIT(15) 849 #define ICE_SINGLE_ACT_INGRESS BIT(16) 850 #define ICE_SINGLE_ACT_PRUNET BIT(17) 851 /* Bit 18 should be set to 0 for this action */ 852 853 /* Action type = 2 - Pointer */ 854 #define ICE_SINGLE_ACT_PTR 0x2 855 #define ICE_SINGLE_ACT_PTR_VAL_S 4 856 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 857 /* Bit 18 should be set to 1 */ 858 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 859 860 /* Action type = 3 - Other actions. Last two bits 861 * are other action identifier 862 */ 863 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 864 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 865 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 866 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 867 868 /* Bit 17:18 - Defines other actions */ 869 /* Other action = 0 - Mirror VSI */ 870 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 871 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 872 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 873 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 874 875 /* Other action = 3 - Set Stat count */ 876 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 877 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 878 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 879 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 880 881 __le16 index; /* The index of the rule in the lookup table */ 882 /* Length and values of the header to be matched per recipe or 883 * lookup-type 884 */ 885 __le16 hdr_len; 886 u8 hdr[STRUCT_HACK_VAR_LEN]; 887 }; 888 889 /* Add/Update/Remove large action command/response entry 890 * "index" is returned as part of a response to a successful Add command, and 891 * can be used to identify the action for Update/Get/Remove commands. 892 */ 893 struct ice_sw_rule_lg_act { 894 __le16 index; /* Index in large action table */ 895 __le16 size; 896 /* Max number of large actions */ 897 #define ICE_MAX_LG_ACT 4 898 /* Bit 0:1 - Action type */ 899 #define ICE_LG_ACT_TYPE_S 0 900 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 901 902 /* Action type = 0 - Forward to VSI or VSI list */ 903 #define ICE_LG_ACT_VSI_FORWARDING 0 904 #define ICE_LG_ACT_VSI_ID_S 3 905 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 906 #define ICE_LG_ACT_VSI_LIST_ID_S 3 907 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 908 /* This bit needs to be set if action is forward to VSI list */ 909 #define ICE_LG_ACT_VSI_LIST BIT(13) 910 911 #define ICE_LG_ACT_VALID_BIT BIT(16) 912 913 /* Action type = 1 - Forward to Queue of Queue group */ 914 #define ICE_LG_ACT_TO_Q 0x1 915 #define ICE_LG_ACT_Q_INDEX_S 3 916 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 917 #define ICE_LG_ACT_Q_REGION_S 14 918 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 919 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 920 921 /* Action type = 2 - Prune */ 922 #define ICE_LG_ACT_PRUNE 0x2 923 #define ICE_LG_ACT_EGRESS BIT(14) 924 #define ICE_LG_ACT_INGRESS BIT(15) 925 #define ICE_LG_ACT_PRUNET BIT(16) 926 927 /* Action type = 3 - Mirror VSI */ 928 #define ICE_LG_OTHER_ACT_MIRROR 0x3 929 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 930 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 931 932 /* Action type = 5 - Generic Value */ 933 #define ICE_LG_ACT_GENERIC 0x5 934 #define ICE_LG_ACT_GENERIC_VALUE_S 3 935 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 936 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 937 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 938 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 939 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 940 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 941 942 /* Action = 7 - Set Stat count */ 943 #define ICE_LG_ACT_STAT_COUNT 0x7 944 #define ICE_LG_ACT_STAT_COUNT_S 3 945 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 946 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 947 }; 948 949 /* Add/Update/Remove VSI list command/response entry 950 * "index" is returned as part of a response to a successful Add command, and 951 * can be used to identify the VSI list for Update/Get/Remove commands. 952 */ 953 struct ice_sw_rule_vsi_list { 954 __le16 index; /* Index of VSI/Prune list */ 955 __le16 number_vsi; 956 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 957 }; 958 959 #pragma pack(1) 960 /* Query VSI list command/response entry */ 961 struct ice_sw_rule_vsi_list_query { 962 __le16 index; 963 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 964 }; 965 #pragma pack() 966 967 #pragma pack(1) 968 /* Add switch rule response: 969 * Content of return buffer is same as the input buffer. The status field and 970 * LUT index are updated as part of the response 971 */ 972 struct ice_aqc_sw_rules_elem { 973 __le16 type; /* Switch rule type, one of T_... */ 974 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 975 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 976 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 977 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 978 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 979 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 980 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 981 __le16 status; 982 union { 983 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 984 struct ice_sw_rule_lg_act lg_act; 985 struct ice_sw_rule_vsi_list vsi_list; 986 struct ice_sw_rule_vsi_list_query vsi_list_query; 987 } pdata; 988 }; 989 990 #pragma pack() 991 992 /* PFC Ignore (direct 0x0301) 993 * The command and response use the same descriptor structure 994 */ 995 struct ice_aqc_pfc_ignore { 996 u8 tc_bitmap; 997 u8 cmd_flags; /* unused in response */ 998 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 999 #define ICE_AQC_PFC_IGNORE_CLEAR 0 1000 u8 reserved[14]; 1001 }; 1002 1003 /* Set PFC Mode (direct 0x0303) 1004 * Query PFC Mode (direct 0x0302) 1005 */ 1006 struct ice_aqc_set_query_pfc_mode { 1007 u8 pfc_mode; 1008 /* For Set Command response, reserved in all other cases */ 1009 #define ICE_AQC_PFC_NOT_CONFIGURED 0 1010 /* For Query Command response, reserved in all other cases */ 1011 #define ICE_AQC_DCB_DIS 0 1012 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 1013 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 1014 u8 rsvd[15]; 1015 }; 1016 1017 /* Set DCB Parameters (direct 0x0306) */ 1018 struct ice_aqc_set_dcb_params { 1019 u8 cmd_flags; /* unused in response */ 1020 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1021 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1022 u8 valid_flags; /* unused in response */ 1023 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1024 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1025 u8 rsvd[14]; 1026 }; 1027 1028 /* Get Default Topology (indirect 0x0400) */ 1029 struct ice_aqc_get_topo { 1030 u8 port_num; 1031 u8 num_branches; 1032 __le16 reserved1; 1033 __le32 reserved2; 1034 __le32 addr_high; 1035 __le32 addr_low; 1036 }; 1037 1038 /* Update TSE (indirect 0x0403) 1039 * Get TSE (indirect 0x0404) 1040 * Add TSE (indirect 0x0401) 1041 * Delete TSE (indirect 0x040F) 1042 * Move TSE (indirect 0x0408) 1043 * Suspend Nodes (indirect 0x0409) 1044 * Resume Nodes (indirect 0x040A) 1045 */ 1046 struct ice_aqc_sched_elem_cmd { 1047 __le16 num_elem_req; /* Used by commands */ 1048 __le16 num_elem_resp; /* Used by responses */ 1049 __le32 reserved; 1050 __le32 addr_high; 1051 __le32 addr_low; 1052 }; 1053 1054 struct ice_aqc_txsched_move_grp_info_hdr { 1055 __le32 src_parent_teid; 1056 __le32 dest_parent_teid; 1057 __le16 num_elems; 1058 u8 flags; 1059 u8 reserved; 1060 }; 1061 1062 struct ice_aqc_move_elem { 1063 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1064 __le32 teid[STRUCT_HACK_VAR_LEN]; 1065 }; 1066 1067 struct ice_aqc_elem_info_bw { 1068 __le16 bw_profile_idx; 1069 __le16 bw_alloc; 1070 }; 1071 1072 struct ice_aqc_txsched_elem { 1073 u8 elem_type; /* Special field, reserved for some aq calls */ 1074 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1075 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1076 #define ICE_AQC_ELEM_TYPE_TC 0x2 1077 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1078 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1079 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1080 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1081 u8 valid_sections; 1082 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1083 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1084 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1085 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1086 u8 generic; 1087 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1088 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1089 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1090 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1091 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1092 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1093 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1094 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1095 u8 flags; /* Special field, reserved for some aq calls */ 1096 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1097 struct ice_aqc_elem_info_bw cir_bw; 1098 struct ice_aqc_elem_info_bw eir_bw; 1099 __le16 srl_id; 1100 __le16 reserved2; 1101 }; 1102 1103 struct ice_aqc_txsched_elem_data { 1104 __le32 parent_teid; 1105 __le32 node_teid; 1106 struct ice_aqc_txsched_elem data; 1107 }; 1108 1109 struct ice_aqc_txsched_topo_grp_info_hdr { 1110 __le32 parent_teid; 1111 __le16 num_elems; 1112 __le16 reserved2; 1113 }; 1114 1115 struct ice_aqc_add_elem { 1116 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1117 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1118 }; 1119 1120 struct ice_aqc_get_topo_elem { 1121 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1122 struct ice_aqc_txsched_elem_data 1123 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1124 }; 1125 1126 struct ice_aqc_delete_elem { 1127 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1128 __le32 teid[STRUCT_HACK_VAR_LEN]; 1129 }; 1130 1131 /* Query Port ETS (indirect 0x040E) 1132 * 1133 * This indirect command is used to query port TC node configuration. 1134 */ 1135 struct ice_aqc_query_port_ets { 1136 __le32 port_teid; 1137 __le32 reserved; 1138 __le32 addr_high; 1139 __le32 addr_low; 1140 }; 1141 1142 struct ice_aqc_port_ets_elem { 1143 u8 tc_valid_bits; 1144 u8 reserved[3]; 1145 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1146 __le32 up2tc; 1147 u8 tc_bw_share[8]; 1148 __le32 port_eir_prof_id; 1149 __le32 port_cir_prof_id; 1150 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1151 __le32 tc_node_prio; 1152 #define ICE_TC_NODE_PRIO_S 0x4 1153 u8 reserved1[4]; 1154 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1155 }; 1156 1157 /* Rate limiting profile for 1158 * Add RL profile (indirect 0x0410) 1159 * Query RL profile (indirect 0x0411) 1160 * Remove RL profile (indirect 0x0415) 1161 * These indirect commands acts on single or multiple 1162 * RL profiles with specified data. 1163 */ 1164 struct ice_aqc_rl_profile { 1165 __le16 num_profiles; 1166 __le16 num_processed; /* Only for response. Reserved in Command. */ 1167 u8 reserved[4]; 1168 __le32 addr_high; 1169 __le32 addr_low; 1170 }; 1171 1172 struct ice_aqc_rl_profile_elem { 1173 u8 level; 1174 u8 flags; 1175 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1176 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1177 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1178 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1179 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1180 /* The following flag is used for Query RL Profile Data */ 1181 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1182 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1183 1184 __le16 profile_id; 1185 __le16 max_burst_size; 1186 __le16 rl_multiply; 1187 __le16 wake_up_calc; 1188 __le16 rl_encode; 1189 }; 1190 1191 /* Configure L2 Node CGD (indirect 0x0414) 1192 * This indirect command allows configuring a congestion domain for given L2 1193 * node TEIDs in the scheduler topology. 1194 */ 1195 struct ice_aqc_cfg_l2_node_cgd { 1196 __le16 num_l2_nodes; 1197 u8 reserved[6]; 1198 __le32 addr_high; 1199 __le32 addr_low; 1200 }; 1201 1202 struct ice_aqc_cfg_l2_node_cgd_elem { 1203 __le32 node_teid; 1204 u8 cgd; 1205 u8 reserved[3]; 1206 }; 1207 1208 /* Query Scheduler Resource Allocation (indirect 0x0412) 1209 * This indirect command retrieves the scheduler resources allocated by 1210 * EMP Firmware to the given PF. 1211 */ 1212 struct ice_aqc_query_txsched_res { 1213 u8 reserved[8]; 1214 __le32 addr_high; 1215 __le32 addr_low; 1216 }; 1217 1218 struct ice_aqc_generic_sched_props { 1219 __le16 phys_levels; 1220 __le16 logical_levels; 1221 u8 flattening_bitmap; 1222 u8 max_device_cgds; 1223 u8 max_pf_cgds; 1224 u8 rsvd0; 1225 __le16 rdma_qsets; 1226 u8 rsvd1[22]; 1227 }; 1228 1229 struct ice_aqc_layer_props { 1230 u8 logical_layer; 1231 u8 chunk_size; 1232 __le16 max_device_nodes; 1233 __le16 max_pf_nodes; 1234 u8 rsvd0[4]; 1235 __le16 max_sibl_grp_sz; 1236 __le16 max_cir_rl_profiles; 1237 __le16 max_eir_rl_profiles; 1238 __le16 max_srl_profiles; 1239 u8 rsvd1[14]; 1240 }; 1241 1242 struct ice_aqc_query_txsched_res_resp { 1243 struct ice_aqc_generic_sched_props sched_props; 1244 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1245 }; 1246 1247 /* Query Node to Root Topology (indirect 0x0413) 1248 * This command uses ice_aqc_get_elem as its data buffer. 1249 */ 1250 struct ice_aqc_query_node_to_root { 1251 __le32 teid; 1252 __le32 num_nodes; /* Response only */ 1253 __le32 addr_high; 1254 __le32 addr_low; 1255 }; 1256 1257 /* Get PHY capabilities (indirect 0x0600) */ 1258 struct ice_aqc_get_phy_caps { 1259 u8 lport_num; 1260 u8 reserved; 1261 __le16 param0; 1262 /* 18.0 - Report qualified modules */ 1263 #define ICE_AQC_GET_PHY_RQM BIT(0) 1264 /* 18.1 - 18.3 : Report mode 1265 * 000b - Report NVM capabilities 1266 * 001b - Report topology capabilities 1267 * 010b - Report SW configured 1268 * 100b - Report default capabilities 1269 */ 1270 #define ICE_AQC_REPORT_MODE_S 1 1271 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1272 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1273 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1274 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1275 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1276 __le32 reserved1; 1277 __le32 addr_high; 1278 __le32 addr_low; 1279 }; 1280 1281 /* This is #define of PHY type (Extended): 1282 * The first set of defines is for phy_type_low. 1283 */ 1284 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1285 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1286 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1287 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1288 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1289 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1290 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1291 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1292 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1293 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1294 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1295 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1296 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1297 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1298 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1299 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1300 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1301 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1302 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1303 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1304 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1305 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1306 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1307 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1308 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1309 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1310 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1311 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1312 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1313 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1314 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1315 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1316 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1317 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1318 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1319 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1320 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1321 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1322 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1323 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1324 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1325 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1326 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1327 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1328 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1329 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1330 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1331 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1332 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1333 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1334 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1335 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1336 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1337 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1338 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1339 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1340 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1341 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1342 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1343 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1344 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1345 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1346 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1347 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1348 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1349 /* The second set of defines is for phy_type_high. */ 1350 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1351 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1352 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1353 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1354 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1355 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1356 1357 struct ice_aqc_get_phy_caps_data { 1358 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1359 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1360 u8 caps; 1361 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1362 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1363 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1364 #define ICE_AQC_PHY_EN_LINK BIT(3) 1365 #define ICE_AQC_PHY_AN_MODE BIT(4) 1366 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1367 #define ICE_AQC_PHY_EN_LESM BIT(6) 1368 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1369 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1370 u8 low_power_ctrl_an; 1371 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1372 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1373 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1374 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1375 __le16 eee_cap; 1376 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1377 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1378 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1379 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1380 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1381 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1382 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1383 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1384 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1385 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1386 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1387 __le16 eeer_value; 1388 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1389 u8 phy_fw_ver[8]; 1390 u8 link_fec_options; 1391 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1392 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1393 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1394 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1395 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1396 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1397 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1398 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1399 u8 module_compliance_enforcement; 1400 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1401 u8 extended_compliance_code; 1402 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1403 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1404 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1405 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1406 #define ICE_AQC_MOD_TYPE_IDENT 1 1407 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1408 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1409 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1410 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1411 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1412 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1413 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1414 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1415 u8 qualified_module_count; 1416 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1417 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1418 struct { 1419 u8 v_oui[3]; 1420 u8 rsvd3; 1421 u8 v_part[16]; 1422 __le32 v_rev; 1423 __le64 rsvd4; 1424 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1425 }; 1426 1427 /* Set PHY capabilities (direct 0x0601) 1428 * NOTE: This command must be followed by setup link and restart auto-neg 1429 */ 1430 struct ice_aqc_set_phy_cfg { 1431 u8 lport_num; 1432 u8 reserved[7]; 1433 __le32 addr_high; 1434 __le32 addr_low; 1435 }; 1436 1437 /* Set PHY config command data structure */ 1438 struct ice_aqc_set_phy_cfg_data { 1439 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1440 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1441 u8 caps; 1442 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1443 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1444 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1445 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1446 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1447 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1448 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1449 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1450 u8 low_power_ctrl_an; 1451 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1452 __le16 eeer_value; 1453 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1454 u8 module_compliance_enforcement; 1455 }; 1456 1457 /* Set MAC Config command data structure (direct 0x0603) */ 1458 struct ice_aqc_set_mac_cfg { 1459 __le16 max_frame_size; 1460 u8 params; 1461 #define ICE_AQ_SET_MAC_PACE_S 3 1462 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1463 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1464 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1465 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1466 u8 tx_tmr_priority; 1467 __le16 tx_tmr_value; 1468 __le16 fc_refresh_threshold; 1469 u8 drop_opts; 1470 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1471 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1472 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1473 u8 reserved[7]; 1474 }; 1475 1476 /* Restart AN command data structure (direct 0x0605) 1477 * Also used for response, with only the lport_num field present. 1478 */ 1479 struct ice_aqc_restart_an { 1480 u8 lport_num; 1481 u8 reserved; 1482 u8 cmd_flags; 1483 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1484 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1485 u8 reserved2[13]; 1486 }; 1487 1488 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1489 struct ice_aqc_get_link_status { 1490 u8 lport_num; 1491 u8 reserved; 1492 __le16 cmd_flags; 1493 #define ICE_AQ_LSE_M 0x3 1494 #define ICE_AQ_LSE_NOP 0x0 1495 #define ICE_AQ_LSE_DIS 0x2 1496 #define ICE_AQ_LSE_ENA 0x3 1497 /* only response uses this flag */ 1498 #define ICE_AQ_LSE_IS_ENABLED 0x1 1499 __le32 reserved2; 1500 __le32 addr_high; 1501 __le32 addr_low; 1502 }; 1503 1504 /* Get link status response data structure, also used for Link Status Event */ 1505 struct ice_aqc_get_link_status_data { 1506 u8 topo_media_conflict; 1507 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1508 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1509 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1510 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1511 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1512 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1513 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1514 u8 link_cfg_err; 1515 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1516 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1517 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1518 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1519 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1520 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1521 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1522 u8 link_info; 1523 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1524 #define ICE_AQ_LINK_FAULT BIT(1) 1525 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1526 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1527 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1528 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1529 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1530 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1531 u8 an_info; 1532 #define ICE_AQ_AN_COMPLETED BIT(0) 1533 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1534 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1535 #define ICE_AQ_FEC_EN BIT(3) 1536 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1537 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1538 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1539 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1540 u8 ext_info; 1541 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1542 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1543 /* Port Tx Suspended */ 1544 #define ICE_AQ_LINK_TX_S 2 1545 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1546 #define ICE_AQ_LINK_TX_ACTIVE 0 1547 #define ICE_AQ_LINK_TX_DRAINED 1 1548 #define ICE_AQ_LINK_TX_FLUSHED 3 1549 u8 lb_status; 1550 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1551 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1552 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1553 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1554 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1555 __le16 max_frame_size; 1556 u8 cfg; 1557 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1558 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1559 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1560 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1561 /* Pacing Config */ 1562 #define ICE_AQ_CFG_PACING_S 3 1563 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1564 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1565 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1566 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1567 /* External Device Power Ability */ 1568 u8 power_desc; 1569 #define ICE_AQ_PWR_CLASS_M 0x3F 1570 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1571 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1572 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1573 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1574 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1575 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1576 __le16 link_speed; 1577 #define ICE_AQ_LINK_SPEED_M 0x7FF 1578 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1579 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1580 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1581 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1582 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1583 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1584 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1585 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1586 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1587 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1588 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1589 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1590 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1591 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1592 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1593 }; 1594 1595 /* Set event mask command (direct 0x0613) */ 1596 struct ice_aqc_set_event_mask { 1597 u8 lport_num; 1598 u8 reserved[7]; 1599 __le16 event_mask; 1600 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1601 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1602 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1603 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1604 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1605 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1606 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1607 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1608 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1609 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1610 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1611 u8 reserved1[6]; 1612 }; 1613 1614 /* Set MAC Loopback command (direct 0x0620) */ 1615 struct ice_aqc_set_mac_lb { 1616 u8 lb_mode; 1617 #define ICE_AQ_MAC_LB_EN BIT(0) 1618 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1619 u8 reserved[15]; 1620 }; 1621 1622 struct ice_aqc_link_topo_params { 1623 u8 lport_num; 1624 u8 lport_num_valid; 1625 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1626 u8 node_type_ctx; 1627 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1628 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1629 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1630 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1631 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1632 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1633 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1634 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1635 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1636 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1637 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1638 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1639 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1640 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1641 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1642 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1643 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1644 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1645 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1646 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1647 u8 index; 1648 }; 1649 1650 struct ice_aqc_link_topo_addr { 1651 struct ice_aqc_link_topo_params topo_params; 1652 __le16 handle; 1653 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1654 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1655 /* Used to decode the handle field */ 1656 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1657 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1658 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1659 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1660 /* In case of a Mezzanine type */ 1661 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1662 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1663 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1664 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1665 /* In case of a LOM type */ 1666 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1667 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1668 }; 1669 1670 /* Get Link Topology Handle (direct, 0x06E0) */ 1671 struct ice_aqc_get_link_topo { 1672 struct ice_aqc_link_topo_addr addr; 1673 u8 node_part_num; 1674 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1675 u8 rsvd[9]; 1676 }; 1677 1678 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1679 struct ice_aqc_i2c { 1680 struct ice_aqc_link_topo_addr topo_addr; 1681 __le16 i2c_addr; 1682 u8 i2c_params; 1683 #define ICE_AQC_I2C_DATA_SIZE_S 0 1684 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1685 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1686 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1687 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1688 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1689 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1690 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1691 u8 rsvd; 1692 __le16 i2c_bus_addr; 1693 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1694 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1695 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1696 }; 1697 1698 /* Read I2C Response (direct, 0x06E2) */ 1699 struct ice_aqc_read_i2c_resp { 1700 u8 i2c_data[16]; 1701 }; 1702 1703 /* Set Port Identification LED (direct, 0x06E9) */ 1704 struct ice_aqc_set_port_id_led { 1705 u8 lport_num; 1706 u8 lport_num_valid; 1707 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1708 u8 ident_mode; 1709 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1710 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1711 u8 rsvd[13]; 1712 }; 1713 1714 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1715 struct ice_aqc_gpio { 1716 __le16 gpio_ctrl_handle; 1717 #define ICE_AQC_GPIO_HANDLE_S 0 1718 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1719 u8 gpio_num; 1720 u8 gpio_val; 1721 u8 rsvd[12]; 1722 }; 1723 1724 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1725 struct ice_aqc_sff_eeprom { 1726 u8 lport_num; 1727 u8 lport_num_valid; 1728 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1729 __le16 i2c_bus_addr; 1730 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1731 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1732 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1733 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1734 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1735 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1736 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1737 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1738 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1739 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1740 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1741 __le16 i2c_mem_addr; 1742 __le16 eeprom_page; 1743 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1744 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1745 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1746 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1747 __le32 addr_high; 1748 __le32 addr_low; 1749 }; 1750 1751 /* SW Set GPIO command (indirect 0x6EF) 1752 * SW Get GPIO command (indirect 0x6F0) 1753 */ 1754 struct ice_aqc_sw_gpio { 1755 __le16 gpio_ctrl_handle; 1756 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 1757 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 1758 u8 gpio_num; 1759 #define ICE_AQC_SW_GPIO_NUMBER_S 0 1760 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 1761 u8 gpio_params; 1762 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 1763 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 1764 u8 rsvd[12]; 1765 }; 1766 1767 /* Program Topology Device NVM (direct, 0x06F2) */ 1768 struct ice_aqc_prog_topo_dev_nvm { 1769 struct ice_aqc_link_topo_params topo_params; 1770 u8 rsvd[12]; 1771 }; 1772 1773 /* Read Topology Device NVM (direct, 0x06F3) */ 1774 struct ice_aqc_read_topo_dev_nvm { 1775 struct ice_aqc_link_topo_params topo_params; 1776 __le32 start_address; 1777 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 1778 u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; 1779 }; 1780 1781 /* NVM Read command (indirect 0x0701) 1782 * NVM Erase commands (direct 0x0702) 1783 * NVM Write commands (indirect 0x0703) 1784 * NVM Write Activate commands (direct 0x0707) 1785 * NVM Shadow RAM Dump commands (direct 0x0707) 1786 */ 1787 struct ice_aqc_nvm { 1788 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1789 __le16 offset_low; 1790 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 1791 u8 cmd_flags; 1792 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1793 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 1794 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 1795 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1796 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1797 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1798 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1799 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1800 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1801 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1802 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1803 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1804 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1805 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 1806 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1807 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ 1808 #define ICE_AQC_NVM_PERST_FLAG 1 1809 #define ICE_AQC_NVM_EMPR_FLAG 2 1810 #define ICE_AQC_NVM_EMPR_ENA BIT(0) 1811 __le16 module_typeid; 1812 __le16 length; 1813 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1814 __le32 addr_high; 1815 __le32 addr_low; 1816 }; 1817 1818 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 1819 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 1820 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 1821 1822 #define ICE_AQC_NVM_START_POINT 0 1823 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 1824 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 1825 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 1826 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 1827 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 1828 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 1829 1830 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 1831 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 1832 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 1833 1834 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 1835 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 1836 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 1837 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 1838 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 1839 1840 /* Used for 0x0704 as well as for 0x0705 commands */ 1841 struct ice_aqc_nvm_cfg { 1842 u8 cmd_flags; 1843 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1844 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1845 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1846 u8 reserved; 1847 __le16 count; 1848 __le16 id; 1849 u8 reserved1[2]; 1850 __le32 addr_high; 1851 __le32 addr_low; 1852 }; 1853 1854 struct ice_aqc_nvm_cfg_data { 1855 __le16 field_id; 1856 __le16 field_options; 1857 __le16 field_value; 1858 }; 1859 1860 /* NVM Checksum Command (direct, 0x0706) */ 1861 struct ice_aqc_nvm_checksum { 1862 u8 flags; 1863 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1864 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1865 u8 rsvd; 1866 __le16 checksum; /* Used only by response */ 1867 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1868 u8 rsvd2[12]; 1869 }; 1870 1871 /* Get LLDP MIB (indirect 0x0A00) 1872 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1873 * as the format is the same. 1874 */ 1875 struct ice_aqc_lldp_get_mib { 1876 u8 type; 1877 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1878 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1879 #define ICE_AQ_LLDP_MIB_LOCAL 0 1880 #define ICE_AQ_LLDP_MIB_REMOTE 1 1881 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1882 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1883 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1884 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1885 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1886 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1887 #define ICE_AQ_LLDP_TX_S 0x4 1888 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1889 #define ICE_AQ_LLDP_TX_ACTIVE 0 1890 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1891 #define ICE_AQ_LLDP_TX_FLUSHED 3 1892 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1893 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1894 * Get LLDP MIB (0x0A00) response only. 1895 */ 1896 u8 reserved1; 1897 __le16 local_len; 1898 __le16 remote_len; 1899 u8 reserved2[2]; 1900 __le32 addr_high; 1901 __le32 addr_low; 1902 }; 1903 1904 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1905 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1906 struct ice_aqc_lldp_set_mib_change { 1907 u8 command; 1908 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1909 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1910 u8 reserved[15]; 1911 }; 1912 1913 /* Add LLDP TLV (indirect 0x0A02) 1914 * Delete LLDP TLV (indirect 0x0A04) 1915 */ 1916 struct ice_aqc_lldp_add_delete_tlv { 1917 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1918 u8 reserved1[1]; 1919 __le16 len; 1920 u8 reserved2[4]; 1921 __le32 addr_high; 1922 __le32 addr_low; 1923 }; 1924 1925 /* Update LLDP TLV (indirect 0x0A03) */ 1926 struct ice_aqc_lldp_update_tlv { 1927 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1928 u8 reserved; 1929 __le16 old_len; 1930 __le16 new_offset; 1931 __le16 new_len; 1932 __le32 addr_high; 1933 __le32 addr_low; 1934 }; 1935 1936 /* Stop LLDP (direct 0x0A05) */ 1937 struct ice_aqc_lldp_stop { 1938 u8 command; 1939 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1940 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1941 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1942 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1943 u8 reserved[15]; 1944 }; 1945 1946 /* Start LLDP (direct 0x0A06) */ 1947 struct ice_aqc_lldp_start { 1948 u8 command; 1949 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1950 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1951 u8 reserved[15]; 1952 }; 1953 1954 /* Get CEE DCBX Oper Config (0x0A07) 1955 * The command uses the generic descriptor struct and 1956 * returns the struct below as an indirect response. 1957 */ 1958 struct ice_aqc_get_cee_dcb_cfg_resp { 1959 u8 oper_num_tc; 1960 u8 oper_prio_tc[4]; 1961 u8 oper_tc_bw[8]; 1962 u8 oper_pfc_en; 1963 __le16 oper_app_prio; 1964 #define ICE_AQC_CEE_APP_FCOE_S 0 1965 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1966 #define ICE_AQC_CEE_APP_ISCSI_S 3 1967 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1968 #define ICE_AQC_CEE_APP_FIP_S 8 1969 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1970 __le32 tlv_status; 1971 #define ICE_AQC_CEE_PG_STATUS_S 0 1972 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1973 #define ICE_AQC_CEE_PFC_STATUS_S 3 1974 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1975 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1976 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1977 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1978 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1979 #define ICE_AQC_CEE_FIP_STATUS_S 16 1980 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1981 u8 reserved[12]; 1982 }; 1983 1984 /* Set Local LLDP MIB (indirect 0x0A08) 1985 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1986 */ 1987 struct ice_aqc_lldp_set_local_mib { 1988 u8 type; 1989 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1990 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1991 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1992 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1993 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1994 u8 reserved0; 1995 __le16 length; 1996 u8 reserved1[4]; 1997 __le32 addr_high; 1998 __le32 addr_low; 1999 }; 2000 2001 struct ice_aqc_lldp_set_local_mib_resp { 2002 u8 status; 2003 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2004 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2005 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2006 u8 reserved[15]; 2007 }; 2008 2009 /* Stop/Start LLDP Agent (direct 0x0A09) 2010 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2011 * The same structure is used for the response, with the command field 2012 * being used as the status field. 2013 */ 2014 struct ice_aqc_lldp_stop_start_specific_agent { 2015 u8 command; 2016 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2017 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2018 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2019 u8 reserved[15]; 2020 }; 2021 2022 /* LLDP Filter Control (direct 0x0A0A) */ 2023 struct ice_aqc_lldp_filter_ctrl { 2024 u8 cmd_flags; 2025 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2026 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2027 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2028 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2029 u8 reserved1; 2030 __le16 vsi_num; 2031 u8 reserved2[12]; 2032 }; 2033 2034 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2035 struct ice_aqc_get_set_rss_key { 2036 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2037 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2038 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2039 __le16 vsi_id; 2040 u8 reserved[6]; 2041 __le32 addr_high; 2042 __le32 addr_low; 2043 }; 2044 2045 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2046 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2047 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2048 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2049 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2050 2051 /** 2052 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2053 * @standard_rss_key: 40 most significant bytes of hash key 2054 * @extended_hash_key: 12 least significant bytes of hash key 2055 * 2056 * Set/Get 40 byte hash key using standard_rss_key field, and set 2057 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2058 * standard_rss_key field for 40 most significant bytes and the 2059 * extended_hash_key field for the 12 least significant bytes of hash key. 2060 */ 2061 struct ice_aqc_get_set_rss_keys { 2062 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2063 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2064 }; 2065 2066 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2067 struct ice_aqc_get_set_rss_lut { 2068 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2069 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2070 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2071 __le16 vsi_id; 2072 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2073 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2074 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2075 2076 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2077 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2078 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2079 2080 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2081 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2082 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2083 2084 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2085 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2086 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2087 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2088 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2089 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2090 2091 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2092 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2093 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2094 2095 __le16 flags; 2096 __le32 reserved; 2097 __le32 addr_high; 2098 __le32 addr_low; 2099 }; 2100 2101 /* Clear FD Table Command (direct, 0x0B06) */ 2102 struct ice_aqc_clear_fd_table { 2103 u8 clear_type; 2104 #define CL_FD_VM_VF_TYPE_VSI_IDX 1 2105 #define CL_FD_VM_VF_TYPE_PF_IDX 2 2106 u8 rsvd; 2107 __le16 vsi_index; 2108 u8 reserved[12]; 2109 }; 2110 2111 /* Allocate ACL table (indirect 0x0C10) */ 2112 #define ICE_AQC_ACL_KEY_WIDTH 40 2113 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5 2114 #define ICE_AQC_ACL_TCAM_DEPTH 512 2115 #define ICE_ACL_ENTRY_ALLOC_UNIT 64 2116 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15 2117 #define ICE_AQC_MAX_ACTION_MEMORIES 20 2118 #define ICE_AQC_MAX_ACTION_ENTRIES 512 2119 #define ICE_AQC_ACL_SLICES 16 2120 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000 2121 /* The ACL block supports up to 8 actions per a single output. */ 2122 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4 2123 2124 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \ 2125 ICE_ACL_ENTRY_ALLOC_UNIT) 2126 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \ 2127 ICE_AQC_MAX_TCAM_ALLOC_UNITS) 2128 2129 struct ice_aqc_acl_alloc_table { 2130 __le16 table_width; 2131 __le16 table_depth; 2132 u8 act_pairs_per_entry; 2133 /* For non-concurrent table allocation, this field needs 2134 * to be set to zero(0) otherwise it shall specify the 2135 * amount of concurrent tables whose AllocIDs are 2136 * specified in buffer. Thus the newly allocated table 2137 * is concurrent with table IDs specified in AllocIDs. 2138 */ 2139 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0 2140 u8 table_type; 2141 __le16 reserved; 2142 __le32 addr_high; 2143 __le32 addr_low; 2144 }; 2145 2146 /* Allocate ACL table command buffer format */ 2147 struct ice_aqc_acl_alloc_table_data { 2148 /* Dependent table AllocIDs. Each word in this 15 word array specifies 2149 * a dependent table AllocID according to the amount specified in the 2150 * "table_type" field. All unused words shall be set to 0xFFFF 2151 */ 2152 #define ICE_AQC_CONCURR_ID_INVALID 0xffff 2153 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL]; 2154 }; 2155 2156 /* Deallocate ACL table (indirect 0x0C11) 2157 * Allocate ACL action-pair (indirect 0x0C12) 2158 * Deallocate ACL action-pair (indirect 0x0C13) 2159 */ 2160 2161 /* Following structure is common and used in case of deallocation 2162 * of ACL table and action-pair 2163 */ 2164 struct ice_aqc_acl_tbl_actpair { 2165 /* Alloc ID of the table being released */ 2166 __le16 alloc_id; 2167 u8 reserved[6]; 2168 __le32 addr_high; 2169 __le32 addr_low; 2170 }; 2171 2172 /* This response structure is same in case of alloc/dealloc table, 2173 * alloc/dealloc action-pair 2174 */ 2175 struct ice_aqc_acl_generic { 2176 /* if alloc_id is below 0x1000 then alllocation failed due to 2177 * unavailable resources, else this is set by FW to identify 2178 * table allocation 2179 */ 2180 __le16 alloc_id; 2181 2182 union { 2183 /* to be used only in case of alloc/dealloc table */ 2184 struct { 2185 /* Index of the first TCAM block, otherwise set to 0xFF 2186 * for a failed allocation 2187 */ 2188 u8 first_tcam; 2189 /* Index of the last TCAM block. This index shall be 2190 * set to the value of first_tcam for single TCAM block 2191 * allocation, otherwise set to 0xFF for a failed 2192 * allocation 2193 */ 2194 u8 last_tcam; 2195 } table; 2196 /* reserved in case of alloc/dealloc action-pair */ 2197 struct { 2198 __le16 reserved; 2199 } act_pair; 2200 } ops; 2201 2202 /* index of first entry (in both TCAM and action memories), 2203 * otherwise set to 0xFF for a failed allocation 2204 */ 2205 __le16 first_entry; 2206 /* index of last entry (in both TCAM and action memories), 2207 * otherwise set to 0xFF for a failed allocation 2208 */ 2209 __le16 last_entry; 2210 2211 /* Each act_mem element specifies the order of the memory 2212 * otherwise 0xFF 2213 */ 2214 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES]; 2215 }; 2216 2217 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate 2218 * response buffer since original command buffer gets updated with 2219 * 'scen_id' in case of success 2220 */ 2221 struct ice_aqc_acl_alloc_scen { 2222 union { 2223 struct { 2224 u8 reserved[8]; 2225 } cmd; 2226 struct { 2227 __le16 scen_id; 2228 u8 reserved[6]; 2229 } resp; 2230 } ops; 2231 __le32 addr_high; 2232 __le32 addr_low; 2233 }; 2234 2235 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need 2236 * separate response buffer since nothing to be returned as a response 2237 * except status. 2238 */ 2239 struct ice_aqc_acl_dealloc_scen { 2240 __le16 scen_id; 2241 u8 reserved[14]; 2242 }; 2243 2244 /* Update ACL scenario (direct 0x0C1B) 2245 * Query ACL scenario (direct 0x0C23) 2246 */ 2247 struct ice_aqc_acl_update_query_scen { 2248 __le16 scen_id; 2249 u8 reserved[6]; 2250 __le32 addr_high; 2251 __le32 addr_low; 2252 }; 2253 2254 /* Input buffer format in case allocate/update ACL scenario and same format 2255 * is used for response buffer in case of query ACL scenario. 2256 * NOTE: de-allocate ACL scenario is direct command and doesn't require 2257 * "buffer", hence no buffer format. 2258 */ 2259 struct ice_aqc_acl_scen { 2260 struct { 2261 /* Byte [x] selection for the TCAM key. This value must be 2262 * set to 0x0 for unusued TCAM. 2263 * Only Bit 6..0 is used in each byte and MSB is reserved 2264 */ 2265 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F 2266 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20 2267 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E 2268 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE 2269 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F 2270 u8 tcam_select[5]; 2271 /* TCAM Block entry masking. This value should be set to 0x0 for 2272 * unused TCAM 2273 */ 2274 u8 chnk_msk; 2275 /* Bit 0 : masks TCAM entries 0-63 2276 * Bit 1 : masks TCAM entries 64-127 2277 * Bit 2 to 7 : follow the pattern of bit 0 and 1 2278 */ 2279 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0) 2280 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1) 2281 u8 start_cmp_set; 2282 2283 } tcam_cfg[ICE_AQC_ACL_SLICES]; 2284 2285 /* Each byte, Bit 6..0: Action memory association to a TCAM block, 2286 * otherwise it shall be set to 0x0 for disabled memory action. 2287 * Bit 7 : Action memory enable for this scenario 2288 */ 2289 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F 2290 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7) 2291 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES]; 2292 }; 2293 2294 /* Allocate ACL counters (indirect 0x0C16) */ 2295 struct ice_aqc_acl_alloc_counters { 2296 /* Amount of contiguous counters requested. Min value is 1 and 2297 * max value is 255 2298 */ 2299 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1 2300 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF 2301 u8 counter_amount; 2302 2303 /* Counter type: 'single counter' which can be configured to count 2304 * either bytes or packets 2305 */ 2306 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0 2307 2308 /* Counter type: 'counter pair' which counts number of bytes and number 2309 * of packets. 2310 */ 2311 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1 2312 /* requested counter type, single/dual */ 2313 u8 counters_type; 2314 2315 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */ 2316 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3 2317 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */ 2318 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1 2319 /* requested counter bank allocation */ 2320 u8 bank_alloc; 2321 2322 u8 reserved; 2323 2324 union { 2325 /* Applicable only in case of command */ 2326 struct { 2327 u8 reserved[12]; 2328 } cmd; 2329 /* Applicable only in case of response */ 2330 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF 2331 struct { 2332 /* Index of first allocated counter. 0xFFFF in case 2333 * of unsuccessful allocation 2334 */ 2335 __le16 first_counter; 2336 /* Index of last allocated counter. 0xFFFF in case 2337 * of unsuccessful allocation 2338 */ 2339 __le16 last_counter; 2340 u8 rsvd[8]; 2341 } resp; 2342 } ops; 2343 }; 2344 2345 /* De-allocate ACL counters (direct 0x0C17) */ 2346 struct ice_aqc_acl_dealloc_counters { 2347 /* first counter being released */ 2348 __le16 first_counter; 2349 /* last counter being released */ 2350 __le16 last_counter; 2351 /* requested counter type, single/dual */ 2352 u8 counters_type; 2353 /* requested counter bank allocation */ 2354 u8 bank_alloc; 2355 u8 reserved[10]; 2356 }; 2357 2358 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the 2359 * resources allocated for it using a single command 2360 */ 2361 struct ice_aqc_acl_dealloc_res { 2362 u8 reserved[16]; 2363 }; 2364 2365 /* Program ACL actionpair (indirect 0x0C1C) 2366 * Query ACL actionpair (indirect 0x0C25) 2367 */ 2368 struct ice_aqc_acl_actpair { 2369 /* action mem index to program/update */ 2370 u8 act_mem_index; 2371 u8 reserved; 2372 /* The entry index in action memory to be programmed/updated */ 2373 __le16 act_entry_index; 2374 __le32 reserved2; 2375 __le32 addr_high; 2376 __le32 addr_low; 2377 }; 2378 2379 /* Input buffer format for program/query action-pair admin command */ 2380 struct ice_acl_act_entry { 2381 /* Action priority, values must be between 0..7 */ 2382 #define ICE_AQC_ACT_PRIO_VALID_MAX 7 2383 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0) 2384 u8 prio; 2385 /* Action meta-data identifier. This field should be set to 0x0 2386 * for a NOP action 2387 */ 2388 #define ICE_AQC_ACT_MDID_S 8 2389 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S) 2390 u8 mdid; 2391 /* Action value */ 2392 #define ICE_AQC_ACT_VALUE_S 16 2393 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16) 2394 __le16 value; 2395 }; 2396 2397 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2 2398 struct ice_aqc_actpair { 2399 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR]; 2400 }; 2401 2402 /* Generic format used to describe either input or response buffer 2403 * for admin commands related to ACL profile 2404 */ 2405 struct ice_aqc_acl_prof_generic_frmt { 2406 /* The first byte of the byte selection base is reserved to keep the 2407 * first byte of the field vector where the packet direction info is 2408 * available. Thus we should start at index 1 of the field vector to 2409 * map its entries to the byte selection base. 2410 */ 2411 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1 2412 /* In each byte: 2413 * Bit 0..5 = Byte selection for the byte selection base from the 2414 * extracted fields (expressed as byte offset in extracted fields). 2415 * Applicable values are 0..63 2416 * Bit 6..7 = Reserved 2417 */ 2418 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30 2419 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS]; 2420 /* In each byte: 2421 * Bit 0..4 = Word selection for the word selection base from the 2422 * extracted fields (expressed as word offset in extracted fields). 2423 * Applicable values are 0..31 2424 * Bit 5..7 = Reserved 2425 */ 2426 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32 2427 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS]; 2428 /* In each byte: 2429 * Bit 0..3 = Double word selection for the double-word selection base 2430 * from the extracted fields (expressed as double-word offset in 2431 * extracted fields). 2432 * Applicable values are 0..15 2433 * Bit 4..7 = Reserved 2434 */ 2435 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15 2436 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS]; 2437 /* Scenario numbers for individual Physical Function's */ 2438 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8 2439 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS]; 2440 }; 2441 2442 /* Program ACL profile extraction (indirect 0x0C1D) 2443 * Program ACL profile ranges (indirect 0x0C1E) 2444 * Query ACL profile (indirect 0x0C21) 2445 * Query ACL profile ranges (indirect 0x0C22) 2446 */ 2447 struct ice_aqc_acl_profile { 2448 u8 profile_id; /* Programmed/Updated profile ID */ 2449 u8 reserved[7]; 2450 __le32 addr_high; 2451 __le32 addr_low; 2452 }; 2453 2454 /* Input buffer format for program profile extraction admin command and 2455 * response buffer format for query profile admin command is as defined 2456 * in struct ice_aqc_acl_prof_generic_frmt 2457 */ 2458 2459 /* Input buffer format for program profile ranges and query profile ranges 2460 * admin commands. Same format is used for response buffer in case of query 2461 * profile ranges command 2462 */ 2463 struct ice_acl_rng_data { 2464 /* The range checker output shall be sent when the value 2465 * related to this range checker is lower than low boundary 2466 */ 2467 __be16 low_boundary; 2468 /* The range checker output shall be sent when the value 2469 * related to this range checker is higher than high boundary 2470 */ 2471 __be16 high_boundary; 2472 /* A value of '0' in bit shall clear the relevant bit input 2473 * to the range checker 2474 */ 2475 __be16 mask; 2476 }; 2477 2478 struct ice_aqc_acl_profile_ranges { 2479 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8 2480 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG]; 2481 }; 2482 2483 /* Program ACL entry (indirect 0x0C20) 2484 * Query ACL entry (indirect 0x0C24) 2485 */ 2486 struct ice_aqc_acl_entry { 2487 u8 tcam_index; /* Updated TCAM block index */ 2488 u8 reserved; 2489 __le16 entry_index; /* Updated entry index */ 2490 __le32 reserved2; 2491 __le32 addr_high; 2492 __le32 addr_low; 2493 }; 2494 2495 /* Input buffer format in case of program ACL entry and response buffer format 2496 * in case of query ACL entry 2497 */ 2498 struct ice_aqc_acl_data { 2499 /* Entry key and entry key invert are 40 bits wide. 2500 * Byte 0..4 : entry key and Byte 5..7 are reserved 2501 * Byte 8..12: entry key invert and Byte 13..15 are reserved 2502 */ 2503 struct { 2504 u8 val[5]; 2505 u8 reserved[3]; 2506 } entry_key, entry_key_invert; 2507 }; 2508 2509 /* Query ACL counter (direct 0x0C27) */ 2510 struct ice_aqc_acl_query_counter { 2511 /* Queried counter index */ 2512 __le16 counter_index; 2513 /* Queried counter bank */ 2514 u8 counter_bank; 2515 union { 2516 struct { 2517 u8 reserved[13]; 2518 } cmd; 2519 struct { 2520 /* Holds counter value/packet counter value */ 2521 u8 val[5]; 2522 u8 reserved[8]; 2523 } resp; 2524 } ops; 2525 }; 2526 2527 /* Add Tx LAN Queues (indirect 0x0C30) */ 2528 struct ice_aqc_add_txqs { 2529 u8 num_qgrps; 2530 u8 reserved[3]; 2531 __le32 reserved1; 2532 __le32 addr_high; 2533 __le32 addr_low; 2534 }; 2535 2536 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2537 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2538 */ 2539 struct ice_aqc_add_txqs_perq { 2540 __le16 txq_id; 2541 u8 rsvd[2]; 2542 __le32 q_teid; 2543 u8 txq_ctx[22]; 2544 u8 rsvd2[2]; 2545 struct ice_aqc_txsched_elem info; 2546 }; 2547 2548 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2549 * is an array of the following structs. Please note that the length of 2550 * each struct ice_aqc_add_tx_qgrp is variable due 2551 * to the variable number of queues in each group! 2552 */ 2553 struct ice_aqc_add_tx_qgrp { 2554 __le32 parent_teid; 2555 u8 num_txqs; 2556 u8 rsvd[3]; 2557 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2558 }; 2559 2560 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2561 struct ice_aqc_dis_txqs { 2562 u8 cmd_type; 2563 #define ICE_AQC_Q_DIS_CMD_S 0 2564 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2565 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2566 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2567 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2568 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2569 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2570 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2571 u8 num_entries; 2572 __le16 vmvf_and_timeout; 2573 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2574 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2575 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2576 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2577 __le32 blocked_cgds; 2578 __le32 addr_high; 2579 __le32 addr_low; 2580 }; 2581 2582 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2583 * contains the following structures, arrayed one after the 2584 * other. 2585 * Note: Since the q_id is 16 bits wide, if the 2586 * number of queues is even, then 2 bytes of alignment MUST be 2587 * added before the start of the next group, to allow correct 2588 * alignment of the parent_teid field. 2589 */ 2590 #pragma pack(1) 2591 struct ice_aqc_dis_txq_item { 2592 __le32 parent_teid; 2593 u8 num_qs; 2594 u8 rsvd; 2595 /* The length of the q_id array varies according to num_qs */ 2596 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2597 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2598 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2599 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2600 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2601 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2602 }; 2603 2604 #pragma pack() 2605 2606 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2607 struct ice_aqc_txqs_cleanup { 2608 __le16 caller_opc; 2609 __le16 cmd_tag; 2610 u8 reserved[12]; 2611 }; 2612 2613 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2614 struct ice_aqc_move_txqs { 2615 u8 cmd_type; 2616 #define ICE_AQC_Q_CMD_TYPE_S 0 2617 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2618 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2619 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2620 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2621 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2622 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2623 u8 num_qs; 2624 u8 rsvd; 2625 u8 timeout; 2626 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2627 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2628 __le32 blocked_cgds; 2629 __le32 addr_high; 2630 __le32 addr_low; 2631 }; 2632 2633 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2634 struct ice_aqc_move_txqs_elem { 2635 __le16 txq_id; 2636 u8 q_cgd; 2637 u8 rsvd; 2638 __le32 q_teid; 2639 }; 2640 2641 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2642 struct ice_aqc_move_txqs_data { 2643 __le32 src_teid; 2644 __le32 dest_teid; 2645 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2646 }; 2647 2648 /* Download Package (indirect 0x0C40) */ 2649 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2650 struct ice_aqc_download_pkg { 2651 u8 flags; 2652 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2653 u8 reserved[3]; 2654 __le32 reserved1; 2655 __le32 addr_high; 2656 __le32 addr_low; 2657 }; 2658 2659 struct ice_aqc_download_pkg_resp { 2660 __le32 error_offset; 2661 __le32 error_info; 2662 __le32 addr_high; 2663 __le32 addr_low; 2664 }; 2665 2666 /* Get Package Info List (indirect 0x0C43) */ 2667 struct ice_aqc_get_pkg_info_list { 2668 __le32 reserved1; 2669 __le32 reserved2; 2670 __le32 addr_high; 2671 __le32 addr_low; 2672 }; 2673 2674 /* Version format for packages */ 2675 struct ice_pkg_ver { 2676 u8 major; 2677 u8 minor; 2678 u8 update; 2679 u8 draft; 2680 }; 2681 2682 #define ICE_PKG_NAME_SIZE 32 2683 #define ICE_SEG_ID_SIZE 28 2684 #define ICE_SEG_NAME_SIZE 28 2685 2686 struct ice_aqc_get_pkg_info { 2687 struct ice_pkg_ver ver; 2688 char name[ICE_SEG_NAME_SIZE]; 2689 __le32 track_id; 2690 u8 is_in_nvm; 2691 u8 is_active; 2692 u8 is_active_at_boot; 2693 u8 is_modified; 2694 }; 2695 2696 /* Get Package Info List response buffer format (0x0C43) */ 2697 struct ice_aqc_get_pkg_info_resp { 2698 __le32 count; 2699 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2700 }; 2701 2702 /* Driver Shared Parameters (direct, 0x0C90) */ 2703 struct ice_aqc_driver_shared_params { 2704 u8 set_or_get_op; 2705 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2706 #define ICE_AQC_DRIVER_PARAM_SET 0 2707 #define ICE_AQC_DRIVER_PARAM_GET 1 2708 u8 param_indx; 2709 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2710 u8 rsvd[2]; 2711 __le32 param_val; 2712 __le32 addr_high; 2713 __le32 addr_low; 2714 }; 2715 2716 enum ice_aqc_driver_params { 2717 /* OS clock index for PTP timer Domain 0 */ 2718 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0, 2719 /* OS clock index for PTP timer Domain 1 */ 2720 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1, 2721 2722 /* Add new parameters above */ 2723 ICE_AQC_DRIVER_PARAM_MAX = 16, 2724 }; 2725 2726 /* Lan Queue Overflow Event (direct, 0x1001) */ 2727 struct ice_aqc_event_lan_overflow { 2728 __le32 prtdcb_ruptq; 2729 __le32 qtx_ctl; 2730 u8 reserved[8]; 2731 }; 2732 2733 /* Debug Dump Internal Data (indirect 0xFF08) */ 2734 struct ice_aqc_debug_dump_internals { 2735 u8 cluster_id; 2736 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 2737 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL 1 2738 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 2739 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 2740 /* EMP_DRAM only dumpable in device debug mode */ 2741 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 2742 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 2743 /* AUX_REGS only dumpable in device debug mode */ 2744 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 2745 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 2746 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 2747 u8 reserved; 2748 __le16 table_id; /* Used only for non-memory clusters */ 2749 __le32 idx; /* In table entries for tables, in bytes for memory */ 2750 __le32 addr_high; 2751 __le32 addr_low; 2752 }; 2753 2754 /* Set Health Status (direct 0xFF20) */ 2755 struct ice_aqc_set_health_status_config { 2756 u8 event_source; 2757 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2758 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2759 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2760 u8 reserved[15]; 2761 }; 2762 2763 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2764 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2765 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2766 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2767 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2768 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2769 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2770 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2771 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2772 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2773 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2774 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2775 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2776 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2777 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2778 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2779 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2780 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2781 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2782 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2783 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 2784 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 2785 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2786 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2787 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2788 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2789 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2790 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2791 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2792 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2793 2794 /* Get Health Status codes (indirect 0xFF21) */ 2795 struct ice_aqc_get_supported_health_status_codes { 2796 __le16 health_code_count; 2797 u8 reserved[6]; 2798 __le32 addr_high; 2799 __le32 addr_low; 2800 }; 2801 2802 /* Get Health Status (indirect 0xFF22) */ 2803 struct ice_aqc_get_health_status { 2804 __le16 health_status_count; 2805 u8 reserved[6]; 2806 __le32 addr_high; 2807 __le32 addr_low; 2808 }; 2809 2810 /* Get Health Status event buffer entry, (0xFF22) 2811 * repeated per reported health status 2812 */ 2813 struct ice_aqc_health_status_elem { 2814 __le16 health_status_code; 2815 __le16 event_source; 2816 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2817 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2818 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2819 __le32 internal_data1; 2820 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2821 __le32 internal_data2; 2822 }; 2823 2824 /* Clear Health Status (direct 0xFF23) */ 2825 struct ice_aqc_clear_health_status { 2826 __le32 reserved[4]; 2827 }; 2828 2829 /** 2830 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2831 * @flags: ICE_AQ_FLAG_* flags 2832 * @opcode: AQ command opcode 2833 * @datalen: length in bytes of indirect/external data buffer 2834 * @retval: return value from firmware 2835 * @cookie_high: opaque data high-half 2836 * @cookie_low: opaque data low-half 2837 * @params: command-specific parameters 2838 * 2839 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2840 * (ATQ). The firmware writes back onto the command descriptor and returns 2841 * the result of the command. Asynchronous events that are not an immediate 2842 * result of the command are written to the Admin Receive Queue (ARQ) using 2843 * the same descriptor format. Descriptors are in little-endian notation with 2844 * 32-bit words. 2845 */ 2846 struct ice_aq_desc { 2847 __le16 flags; 2848 __le16 opcode; 2849 __le16 datalen; 2850 __le16 retval; 2851 __le32 cookie_high; 2852 __le32 cookie_low; 2853 union { 2854 u8 raw[16]; 2855 struct ice_aqc_generic generic; 2856 struct ice_aqc_get_ver get_ver; 2857 struct ice_aqc_driver_ver driver_ver; 2858 struct ice_aqc_q_shutdown q_shutdown; 2859 struct ice_aqc_req_res res_owner; 2860 struct ice_aqc_manage_mac_read mac_read; 2861 struct ice_aqc_manage_mac_write mac_write; 2862 struct ice_aqc_clear_pxe clear_pxe; 2863 struct ice_aqc_config_no_drop_policy no_drop; 2864 struct ice_aqc_add_update_mir_rule add_update_rule; 2865 struct ice_aqc_delete_mir_rule del_rule; 2866 struct ice_aqc_list_caps get_cap; 2867 struct ice_aqc_get_phy_caps get_phy; 2868 struct ice_aqc_set_phy_cfg set_phy; 2869 struct ice_aqc_restart_an restart_an; 2870 struct ice_aqc_i2c read_write_i2c; 2871 struct ice_aqc_read_i2c_resp read_i2c_resp; 2872 struct ice_aqc_gpio read_write_gpio; 2873 struct ice_aqc_sw_gpio sw_read_write_gpio; 2874 struct ice_aqc_sff_eeprom read_write_sff_param; 2875 struct ice_aqc_set_port_id_led set_port_id_led; 2876 struct ice_aqc_get_sw_cfg get_sw_conf; 2877 struct ice_aqc_set_port_params set_port_params; 2878 struct ice_aqc_sw_rules sw_rules; 2879 struct ice_aqc_storm_cfg storm_conf; 2880 struct ice_aqc_add_get_recipe add_get_recipe; 2881 struct ice_aqc_recipe_to_profile recipe_to_profile; 2882 struct ice_aqc_get_topo get_topo; 2883 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2884 struct ice_aqc_query_txsched_res query_sched_res; 2885 struct ice_aqc_query_node_to_root query_node_to_root; 2886 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2887 struct ice_aqc_query_port_ets port_ets; 2888 struct ice_aqc_rl_profile rl_profile; 2889 struct ice_aqc_nvm nvm; 2890 struct ice_aqc_nvm_cfg nvm_cfg; 2891 struct ice_aqc_nvm_checksum nvm_checksum; 2892 struct ice_aqc_pfc_ignore pfc_ignore; 2893 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2894 struct ice_aqc_set_dcb_params set_dcb_params; 2895 struct ice_aqc_lldp_get_mib lldp_get_mib; 2896 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2897 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2898 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2899 struct ice_aqc_lldp_stop lldp_stop; 2900 struct ice_aqc_lldp_start lldp_start; 2901 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2902 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2903 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2904 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2905 struct ice_aqc_get_set_rss_key get_set_rss_key; 2906 struct ice_aqc_clear_fd_table clear_fd_table; 2907 struct ice_aqc_acl_alloc_table alloc_table; 2908 struct ice_aqc_acl_tbl_actpair tbl_actpair; 2909 struct ice_aqc_acl_alloc_scen alloc_scen; 2910 struct ice_aqc_acl_dealloc_scen dealloc_scen; 2911 struct ice_aqc_acl_update_query_scen update_query_scen; 2912 struct ice_aqc_acl_alloc_counters alloc_counters; 2913 struct ice_aqc_acl_dealloc_counters dealloc_counters; 2914 struct ice_aqc_acl_dealloc_res dealloc_res; 2915 struct ice_aqc_acl_entry program_query_entry; 2916 struct ice_aqc_acl_actpair program_query_actpair; 2917 struct ice_aqc_acl_profile profile; 2918 struct ice_aqc_acl_query_counter query_counter; 2919 struct ice_aqc_add_txqs add_txqs; 2920 struct ice_aqc_dis_txqs dis_txqs; 2921 struct ice_aqc_move_txqs move_txqs; 2922 struct ice_aqc_txqs_cleanup txqs_cleanup; 2923 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2924 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2925 struct ice_aqc_get_vsi_resp get_vsi_resp; 2926 struct ice_aqc_download_pkg download_pkg; 2927 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2928 struct ice_aqc_driver_shared_params drv_shared_params; 2929 struct ice_aqc_debug_dump_internals debug_dump; 2930 struct ice_aqc_set_mac_lb set_mac_lb; 2931 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2932 struct ice_aqc_get_res_alloc get_res; 2933 struct ice_aqc_get_allocd_res_desc get_res_desc; 2934 struct ice_aqc_set_mac_cfg set_mac_cfg; 2935 struct ice_aqc_set_event_mask set_event_mask; 2936 struct ice_aqc_get_link_status get_link_status; 2937 struct ice_aqc_event_lan_overflow lan_overflow; 2938 struct ice_aqc_get_link_topo get_link_topo; 2939 struct ice_aqc_set_health_status_config 2940 set_health_status_config; 2941 struct ice_aqc_get_supported_health_status_codes 2942 get_supported_health_status_codes; 2943 struct ice_aqc_get_health_status get_health_status; 2944 struct ice_aqc_clear_health_status clear_health_status; 2945 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm; 2946 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm; 2947 } params; 2948 }; 2949 2950 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2951 #define ICE_AQ_LG_BUF 512 2952 2953 /* Flags sub-structure 2954 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2955 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2956 */ 2957 2958 /* command flags and offsets */ 2959 #define ICE_AQ_FLAG_DD_S 0 2960 #define ICE_AQ_FLAG_CMP_S 1 2961 #define ICE_AQ_FLAG_ERR_S 2 2962 #define ICE_AQ_FLAG_VFE_S 3 2963 #define ICE_AQ_FLAG_LB_S 9 2964 #define ICE_AQ_FLAG_RD_S 10 2965 #define ICE_AQ_FLAG_VFC_S 11 2966 #define ICE_AQ_FLAG_BUF_S 12 2967 #define ICE_AQ_FLAG_SI_S 13 2968 #define ICE_AQ_FLAG_EI_S 14 2969 #define ICE_AQ_FLAG_FE_S 15 2970 2971 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2972 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2973 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2974 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2975 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2976 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2977 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2978 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2979 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2980 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2981 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2982 2983 /* error codes */ 2984 enum ice_aq_err { 2985 ICE_AQ_RC_OK = 0, /* Success */ 2986 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2987 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2988 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2989 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2990 ICE_AQ_RC_EIO = 5, /* I/O error */ 2991 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2992 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2993 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2994 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2995 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2996 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2997 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2998 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2999 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 3000 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 3001 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 3002 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 3003 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 3004 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 3005 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 3006 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 3007 ICE_AQ_RC_EFBIG = 22, /* File too big */ 3008 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 3009 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 3010 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 3011 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 3012 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 3013 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 3014 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 3015 }; 3016 3017 /* Admin Queue command opcodes */ 3018 enum ice_adminq_opc { 3019 /* AQ commands */ 3020 ice_aqc_opc_get_ver = 0x0001, 3021 ice_aqc_opc_driver_ver = 0x0002, 3022 ice_aqc_opc_q_shutdown = 0x0003, 3023 ice_aqc_opc_get_exp_err = 0x0005, 3024 3025 /* resource ownership */ 3026 ice_aqc_opc_req_res = 0x0008, 3027 ice_aqc_opc_release_res = 0x0009, 3028 3029 /* device/function capabilities */ 3030 ice_aqc_opc_list_func_caps = 0x000A, 3031 ice_aqc_opc_list_dev_caps = 0x000B, 3032 3033 /* manage MAC address */ 3034 ice_aqc_opc_manage_mac_read = 0x0107, 3035 ice_aqc_opc_manage_mac_write = 0x0108, 3036 3037 /* PXE */ 3038 ice_aqc_opc_clear_pxe_mode = 0x0110, 3039 3040 ice_aqc_opc_config_no_drop_policy = 0x0112, 3041 3042 /* internal switch commands */ 3043 ice_aqc_opc_get_sw_cfg = 0x0200, 3044 ice_aqc_opc_set_port_params = 0x0203, 3045 3046 /* Alloc/Free/Get Resources */ 3047 ice_aqc_opc_get_res_alloc = 0x0204, 3048 ice_aqc_opc_alloc_res = 0x0208, 3049 ice_aqc_opc_free_res = 0x0209, 3050 ice_aqc_opc_get_allocd_res_desc = 0x020A, 3051 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 3052 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 3053 3054 /* VSI commands */ 3055 ice_aqc_opc_add_vsi = 0x0210, 3056 ice_aqc_opc_update_vsi = 0x0211, 3057 ice_aqc_opc_get_vsi_params = 0x0212, 3058 ice_aqc_opc_free_vsi = 0x0213, 3059 3060 /* Mirroring rules - add/update, delete */ 3061 ice_aqc_opc_add_update_mir_rule = 0x0260, 3062 ice_aqc_opc_del_mir_rule = 0x0261, 3063 3064 /* storm configuration */ 3065 ice_aqc_opc_set_storm_cfg = 0x0280, 3066 ice_aqc_opc_get_storm_cfg = 0x0281, 3067 3068 /* recipe commands */ 3069 ice_aqc_opc_add_recipe = 0x0290, 3070 ice_aqc_opc_recipe_to_profile = 0x0291, 3071 ice_aqc_opc_get_recipe = 0x0292, 3072 ice_aqc_opc_get_recipe_to_profile = 0x0293, 3073 3074 /* switch rules population commands */ 3075 ice_aqc_opc_add_sw_rules = 0x02A0, 3076 ice_aqc_opc_update_sw_rules = 0x02A1, 3077 ice_aqc_opc_remove_sw_rules = 0x02A2, 3078 ice_aqc_opc_get_sw_rules = 0x02A3, 3079 ice_aqc_opc_clear_pf_cfg = 0x02A4, 3080 3081 /* DCB commands */ 3082 ice_aqc_opc_pfc_ignore = 0x0301, 3083 ice_aqc_opc_query_pfc_mode = 0x0302, 3084 ice_aqc_opc_set_pfc_mode = 0x0303, 3085 ice_aqc_opc_set_dcb_params = 0x0306, 3086 3087 /* transmit scheduler commands */ 3088 ice_aqc_opc_get_dflt_topo = 0x0400, 3089 ice_aqc_opc_add_sched_elems = 0x0401, 3090 ice_aqc_opc_cfg_sched_elems = 0x0403, 3091 ice_aqc_opc_get_sched_elems = 0x0404, 3092 ice_aqc_opc_move_sched_elems = 0x0408, 3093 ice_aqc_opc_suspend_sched_elems = 0x0409, 3094 ice_aqc_opc_resume_sched_elems = 0x040A, 3095 ice_aqc_opc_query_port_ets = 0x040E, 3096 ice_aqc_opc_delete_sched_elems = 0x040F, 3097 ice_aqc_opc_add_rl_profiles = 0x0410, 3098 ice_aqc_opc_query_rl_profiles = 0x0411, 3099 ice_aqc_opc_query_sched_res = 0x0412, 3100 ice_aqc_opc_query_node_to_root = 0x0413, 3101 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 3102 ice_aqc_opc_remove_rl_profiles = 0x0415, 3103 3104 /* PHY commands */ 3105 ice_aqc_opc_get_phy_caps = 0x0600, 3106 ice_aqc_opc_set_phy_cfg = 0x0601, 3107 ice_aqc_opc_set_mac_cfg = 0x0603, 3108 ice_aqc_opc_restart_an = 0x0605, 3109 ice_aqc_opc_get_link_status = 0x0607, 3110 ice_aqc_opc_set_event_mask = 0x0613, 3111 ice_aqc_opc_set_mac_lb = 0x0620, 3112 ice_aqc_opc_get_link_topo = 0x06E0, 3113 ice_aqc_opc_get_link_topo_pin = 0x06E1, 3114 ice_aqc_opc_read_i2c = 0x06E2, 3115 ice_aqc_opc_write_i2c = 0x06E3, 3116 ice_aqc_opc_set_port_id_led = 0x06E9, 3117 ice_aqc_opc_get_port_options = 0x06EA, 3118 ice_aqc_opc_set_port_option = 0x06EB, 3119 ice_aqc_opc_set_gpio = 0x06EC, 3120 ice_aqc_opc_get_gpio = 0x06ED, 3121 ice_aqc_opc_sff_eeprom = 0x06EE, 3122 ice_aqc_opc_sw_set_gpio = 0x06EF, 3123 ice_aqc_opc_sw_get_gpio = 0x06F0, 3124 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2, 3125 ice_aqc_opc_read_topo_dev_nvm = 0x06F3, 3126 3127 /* NVM commands */ 3128 ice_aqc_opc_nvm_read = 0x0701, 3129 ice_aqc_opc_nvm_erase = 0x0702, 3130 ice_aqc_opc_nvm_write = 0x0703, 3131 ice_aqc_opc_nvm_cfg_read = 0x0704, 3132 ice_aqc_opc_nvm_cfg_write = 0x0705, 3133 ice_aqc_opc_nvm_checksum = 0x0706, 3134 ice_aqc_opc_nvm_write_activate = 0x0707, 3135 ice_aqc_opc_nvm_sr_dump = 0x0707, 3136 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3137 ice_aqc_opc_nvm_update_empr = 0x0709, 3138 3139 /* LLDP commands */ 3140 ice_aqc_opc_lldp_get_mib = 0x0A00, 3141 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3142 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3143 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3144 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3145 ice_aqc_opc_lldp_stop = 0x0A05, 3146 ice_aqc_opc_lldp_start = 0x0A06, 3147 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3148 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3149 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3150 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3151 3152 /* RSS commands */ 3153 ice_aqc_opc_set_rss_key = 0x0B02, 3154 ice_aqc_opc_set_rss_lut = 0x0B03, 3155 ice_aqc_opc_get_rss_key = 0x0B04, 3156 ice_aqc_opc_get_rss_lut = 0x0B05, 3157 ice_aqc_opc_clear_fd_table = 0x0B06, 3158 /* ACL commands */ 3159 ice_aqc_opc_alloc_acl_tbl = 0x0C10, 3160 ice_aqc_opc_dealloc_acl_tbl = 0x0C11, 3161 ice_aqc_opc_alloc_acl_actpair = 0x0C12, 3162 ice_aqc_opc_dealloc_acl_actpair = 0x0C13, 3163 ice_aqc_opc_alloc_acl_scen = 0x0C14, 3164 ice_aqc_opc_dealloc_acl_scen = 0x0C15, 3165 ice_aqc_opc_alloc_acl_counters = 0x0C16, 3166 ice_aqc_opc_dealloc_acl_counters = 0x0C17, 3167 ice_aqc_opc_dealloc_acl_res = 0x0C1A, 3168 ice_aqc_opc_update_acl_scen = 0x0C1B, 3169 ice_aqc_opc_program_acl_actpair = 0x0C1C, 3170 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D, 3171 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E, 3172 ice_aqc_opc_program_acl_entry = 0x0C20, 3173 ice_aqc_opc_query_acl_prof = 0x0C21, 3174 ice_aqc_opc_query_acl_prof_ranges = 0x0C22, 3175 ice_aqc_opc_query_acl_scen = 0x0C23, 3176 ice_aqc_opc_query_acl_entry = 0x0C24, 3177 ice_aqc_opc_query_acl_actpair = 0x0C25, 3178 ice_aqc_opc_query_acl_counter = 0x0C27, 3179 3180 /* Tx queue handling commands/events */ 3181 ice_aqc_opc_add_txqs = 0x0C30, 3182 ice_aqc_opc_dis_txqs = 0x0C31, 3183 ice_aqc_opc_txqs_cleanup = 0x0C31, 3184 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3185 3186 /* package commands */ 3187 ice_aqc_opc_download_pkg = 0x0C40, 3188 ice_aqc_opc_upload_section = 0x0C41, 3189 ice_aqc_opc_update_pkg = 0x0C42, 3190 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3191 3192 ice_aqc_opc_driver_shared_params = 0x0C90, 3193 3194 /* Standalone Commands/Events */ 3195 ice_aqc_opc_event_lan_overflow = 0x1001, 3196 3197 /* debug commands */ 3198 ice_aqc_opc_debug_dump_internals = 0xFF08, 3199 3200 /* SystemDiagnostic commands */ 3201 ice_aqc_opc_set_health_status_config = 0xFF20, 3202 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3203 ice_aqc_opc_get_health_status = 0xFF22, 3204 ice_aqc_opc_clear_health_status = 0xFF23, 3205 }; 3206 3207 #endif /* _ICE_ADMINQ_CMD_H_ */ 3208