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Searched defs:_reg (Results 1 – 25 of 35) sorted by relevance

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/f-stack/freebsd/arm/altera/socfpga/
H A Dsocfpga_common.h33 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
34 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
35 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
36 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
37 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
38 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
/f-stack/freebsd/arm/freescale/vybrid/
H A Dvf_common.h31 #define READ4(_sc, _reg) \ argument
33 #define WRITE4(_sc, _reg, _val) \ argument
35 #define READ2(_sc, _reg) \ argument
37 #define WRITE2(_sc, _reg, _val) \ argument
39 #define READ1(_sc, _reg) \ argument
41 #define WRITE1(_sc, _reg, _val) \ argument
H A Dvf_dmamux.h46 #define MUX_READ1(_sc, _mux, _reg) \ argument
49 #define MUX_WRITE1(_sc, _mux, _reg, _val) \ argument
H A Dvf_ehci.c112 #define PHY_READ4(_sc, _reg) \ argument
114 #define PHY_WRITE4(_sc, _reg, _val) \ argument
117 #define USBC_READ4(_sc, _reg) \ argument
119 #define USBC_WRITE4(_sc, _reg, _val) \ argument
H A Dvf_edma.h113 #define TCD_READ4(_sc, _reg) \ argument
115 #define TCD_WRITE4(_sc, _reg, _val) \ argument
117 #define TCD_READ2(_sc, _reg) \ argument
119 #define TCD_WRITE2(_sc, _reg, _val) \ argument
121 #define TCD_READ1(_sc, _reg) \ argument
123 #define TCD_WRITE1(_sc, _reg, _val) \ argument
/f-stack/freebsd/mips/broadcom/
H A Dbcm_machdep.h112 #define BCM_SOC_WRITE_4(_addr, _reg, _val) \ argument
115 #define BCM_CORE_ADDR(_bp, _name, _reg) \ argument
118 #define BCM_CORE_READ_4(_bp, _name, _reg) \ argument
120 #define BCM_CORE_WRITE_4(_bp, _name, _reg, _val) \ argument
123 #define BCM_CHIPC_READ_4(_bp, _reg) \ argument
125 #define BCM_CHIPC_WRITE_4(_bp, _reg, _val) \ argument
128 #define BCM_CPU_READ_4(_bp, _reg) \ argument
130 #define BCM_CPU_WRITE_4(_bp, _reg, _val) \ argument
133 #define BCM_PMU_READ_4(_bp, _reg) \ argument
135 #define BCM_PMU_WRITE_4(_bp, _reg, _val) \ argument
/f-stack/freebsd/mips/ingenic/
H A Djz4780_common.h33 #define READ4(_sc, _reg) \ argument
35 #define WRITE4(_sc, _reg, _val) \ argument
H A Djz4780_intr.c91 #define READ4(_sc, _reg) bus_read_4((_sc)->pic_res[0], _reg) argument
92 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) argument
H A Djz4780_mmc.c131 #define JZ_MMC_READ_2(_sc, _reg) \ argument
133 #define JZ_MMC_WRITE_2(_sc, _reg, _value) \ argument
135 #define JZ_MMC_READ_4(_sc, _reg) \ argument
137 #define JZ_MMC_WRITE_4(_sc, _reg, _value) \ argument
/f-stack/freebsd/mips/mediatek/
H A Dmtk_xhci.c251 #define RD4(_sc, _reg) bus_read_4((_sc)->sc_io_res, (_reg)) argument
252 #define WR4(_sc, _reg, _val) bus_write_4((_sc)->sc_io_res, (_reg), (_val)) argument
253 #define CLRSET4(_sc, _reg, _clr, _set) \ argument
H A Dmtk_intr_v1.c104 #define READ4(_sc, _reg) bus_read_4((_sc)->pic_res[0], _reg) argument
105 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) argument
H A Dmtk_intr_v2.c99 #define READ4(_sc, _reg) bus_read_4((_sc)->pic_res[0], _reg) argument
100 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) argument
H A Dmtk_pinctrl.h50 #define GROUP(_name, _reg, _off, _mask, _funcs) \ argument
H A Dmtk_intr_gic.c106 #define READ4(_sc, _reg) bus_read_4((_sc)->gic_res[0], (_reg)) argument
107 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val)) argument
H A Dmtk_pcie.c865 #define mtk_pcie_phy_set(_sc, _reg, _s, _n, _v) \ argument
945 #define mtk_gpio_clr_set(_reg, _clr, _set) \ argument
/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_attach.c595 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_read_revisions() argument
610 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_read_revisions() argument
774 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); in ar9300_attach() argument
775 #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) in ar9300_attach() argument
796 #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) in ar9300_attach() argument
2323 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_attach() argument
H A Dar9300_reset.c1737 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_set_reset() argument
1794 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_set_reset() argument
1795 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); in ar9300_set_reset() argument
1797 #define DDR_REG_READ(_ah, _reg) \ in ar9300_set_reset() argument
1799 #define DDR_REG_WRITE(_ah, _reg, _val) \ in ar9300_set_reset() argument
1976 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_phy_disable() argument
1977 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); in ar9300_phy_disable() argument
3122 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_process_ini() argument
5273 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) in ar9300_reset() argument
5380 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val) in ar9300_reset() argument
[all …]
/f-stack/dpdk/drivers/net/axgbe/
H A Daxgbe_common.h1429 #define AXGMAC_IOREAD(_pdata, _reg) \ argument
1480 #define AXGMAC_DMA_IOREAD(_channel, _reg) \ argument
1541 #define XSIR0_IOREAD(_pdata, _reg) \ argument
1549 #define XSIR0_IOWRITE(_pdata, _reg, _val) \ argument
1562 #define XSIR1_IOREAD(_pdata, _reg) \ argument
1586 #define XRXTX_IOREAD(_pdata, _reg) \ argument
1620 #define XP_IOREAD(_pdata, _reg) \ argument
1628 #define XP_IOWRITE(_pdata, _reg, _val) \ argument
1654 #define XI2C_IOREAD(_pdata, _reg) \ argument
1662 #define XI2C_IOWRITE(_pdata, _reg, _val) \ argument
[all …]
/f-stack/freebsd/arm/freescale/imx/
H A Dimx6_audmux.c55 #define READ4(_sc, _reg) \ argument
57 #define WRITE4(_sc, _reg, _val) \ argument
H A Dimx6_sdma.c65 #define READ4(_sc, _reg) \ argument
67 #define WRITE4(_sc, _reg, _val) \ argument
/f-stack/dpdk/drivers/common/sfc_efx/base/
H A Defx_impl.h1050 #define EFX_CHECK_REG(_enp, _reg) \ argument
1089 #define EFX_CHECK_REG(_enp, _reg) do { \ argument
1094 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ argument
1105 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ argument
1116 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ argument
1128 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ argument
1140 #define EFX_BAR_READO(_enp, _reg, _eop) \ argument
1154 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ argument
1221 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ argument
1290 #define EFX_BAR_FCW_READD(_enp, _reg, _edp) \ argument
[all …]
/f-stack/freebsd/arm/arm/
H A Dgic.c146 #define gic_c_read_4(_sc, _reg) \ argument
148 #define gic_c_write_4(_sc, _reg, _val) \ argument
150 #define gic_d_read_4(_sc, _reg) \ argument
152 #define gic_d_write_1(_sc, _reg, _val) \ argument
154 #define gic_d_write_4(_sc, _reg, _val) \ argument
/f-stack/freebsd/arm/allwinner/
H A Daw_nmi.c63 #define SC_NMI_READ(_sc, _reg) bus_read_4(_sc->res[0], _reg) argument
64 #define SC_NMI_WRITE(_sc, _reg, _val) bus_write_4(_sc->res[0], _reg, _val) argument
/f-stack/freebsd/arm64/freescale/imx/
H A Dimx_ccm_clk.h139 #define ROOT_GATE(_id, _name, _pname, _reg) \ argument
/f-stack/freebsd/mips/atheros/
H A Dif_argevar.h91 #define ARGE_MDIO_WRITE(_sc, _reg, _val) \ argument
93 #define ARGE_MDIO_READ(_sc, _reg) \ argument

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