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Searched defs:_i (Results 1 – 22 of 22) sorted by relevance

/dpdk/drivers/crypto/nitrox/
H A Dnitrox_csr.h15 #define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060UL + ((_i) * 0x40000UL)) argument
16 #define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068UL + ((_i) * 0x40000UL)) argument
17 #define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070UL + ((_i) * 0x40000UL)) argument
18 #define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080UL + ((_i) * 0x40000UL)) argument
19 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078UL + ((_i) * 0x40000UL)) argument
20 #define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088UL + ((_i) * 0x40000UL)) argument
21 #define NPS_PKT_SLC_CTLX(_i) (0x10000UL + ((_i) * 0x40000UL)) argument
22 #define NPS_PKT_SLC_CNTSX(_i) (0x10008UL + ((_i) * 0x40000UL)) argument
23 #define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010UL + ((_i) * 0x40000UL)) argument
26 #define AQMQ_QSZX(_i) (0x20008UL + ((_i) * 0x40000UL)) argument
/dpdk/drivers/net/i40e/base/
H A Di40e_register.h437 #define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
1415 #define I40E_PRTMAC_PCS_LINK_STATUS1(_i) (0x0008C200 + ((_i) * 4)) argument
1588 #define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */ argument
2446 #define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2466 #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2486 #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2622 #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2626 #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2634 #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2638 #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
[all …]
/dpdk/drivers/net/ice/base/
H A Dice_hw_autogen.h10 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4)) argument
11 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4)) argument
36 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */ argument
40 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ argument
46 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ argument
50 #define MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ argument
779 #define GL_SWT_L2TAG0(_i) (0x000492A8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ argument
783 #define GL_SWT_L2TAG1(_i) (0x000492C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ argument
5635 #define MSIX_PBA1(_i) (0x00008000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */ argument
9024 #define PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */ argument
[all …]
H A Dice_ptp_hw.h424 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4)) argument
431 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32)) argument
432 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32)) argument
H A Dice_type.h855 #define ice_for_each_traffic_class(_i) \ argument
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_osdep.h78 #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i) argument
79 #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i) argument
80 #define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i) argument
81 #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i) argument
82 #define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i) argument
83 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i) argument
84 #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i) argument
85 #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i) argument
86 #define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i) argument
H A Dixgbe_type.h323 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) argument
324 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) argument
325 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) argument
326 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) argument
417 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) argument
428 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) argument
461 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) argument
1437 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) argument
2032 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) argument
2039 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) argument
[all …]
/dpdk/drivers/common/iavf/
H A Diavf_register.h80 #define IAVF_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ argument
81 #define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _IN… argument
85 #define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ argument
86 #define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ argument
88 #define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ argument
/dpdk/drivers/net/igc/base/
H A Digc_ich8lan.h46 #define IGC_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) argument
47 #define IGC_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) argument
120 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) argument
121 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) argument
122 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) argument
123 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) argument
124 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) argument
H A Digc_regs.h250 #define IGC_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
262 #define IGC_SHRAL(_i) (0x05438 + ((_i) * 8)) argument
263 #define IGC_SHRAH(_i) (0x0543C + ((_i) * 8)) argument
264 #define IGC_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) argument
265 #define IGC_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) argument
266 #define IGC_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
267 #define IGC_FFMT_REG(_i) (0x09000 + ((_i) * 8)) argument
268 #define IGC_FFVT_REG(_i) (0x09800 + ((_i) * 8)) argument
269 #define IGC_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) argument
542 #define IGC_RETA(_i) (0x05C00 + ((_i) * 4)) argument
[all …]
H A Digc_defines.h1112 #define IGC_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) argument
/dpdk/drivers/net/e1000/base/
H A De1000_ich8lan.h46 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) argument
47 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) argument
121 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) argument
122 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) argument
123 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) argument
124 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) argument
125 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) argument
H A De1000_regs.h258 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
263 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) argument
264 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) argument
265 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) argument
266 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) argument
267 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
268 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) argument
269 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) argument
270 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) argument
532 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) argument
[all …]
H A De1000_defines.h1030 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) argument
/dpdk/drivers/net/ionic/
H A Dionic_dev.h134 #define IONIC_INFO_IDX(_q, _i) (_i) argument
135 #define IONIC_INFO_PTR(_q, _i) (&(_q)->info[IONIC_INFO_IDX((_q), _i)]) argument
/dpdk/app/test/
H A Dtest_link_bonding_mode4.c121 #define FOR_EACH(_i, _item, _array, _size) \ argument
129 #define FOR_EACH_PORT(_i, _port) \ argument
140 #define FOR_EACH_PORT_IF(_i, _port, _condition) FOR_EACH_PORT((_i), (_port)) \ argument
148 #define FOR_EACH_SLAVE(_i, _slave) \ argument
H A Dtest_link_bonding_rssconf.c109 #define FOR_EACH(_i, _item, _array, _size) \ argument
117 #define FOR_EACH_PORT(_i, _port) \ argument
/dpdk/lib/eal/windows/include/
H A Dsched.h49 unsigned int _i; in count_cpu() local
/dpdk/drivers/net/qede/base/
H A Decore_iov_api.h769 #define ecore_for_each_vf(_p_hwfn, _i) \ argument
/dpdk/drivers/net/i40e/
H A Di40e_ethdev.c53 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4)) argument
744 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) argument
747 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) argument
750 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4)) argument
8940 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) argument
10166 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4)) argument
H A Di40e_ethdev.h28 #define I40E_GL_RXERR1_H(_i) (0x00318004 + ((_i) * 8)) argument
200 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) argument
/dpdk/drivers/net/ixgbe/
H A Dixgbe_ethdev.c124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ argument