1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, SPONENTRY, 74 75 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. 76 /// Materializes the offset from the local object pointer of another 77 /// function to a particular local object passed to llvm.localescape. The 78 /// operand is the MCSymbol label used to represent this offset, since 79 /// typically the offset is not known until after code generation of the 80 /// parent. 81 LOCAL_RECOVER, 82 83 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 84 /// the DAG, which implements the named register global variables extension. 85 READ_REGISTER, 86 WRITE_REGISTER, 87 88 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 89 /// first (possible) on-stack argument. This is needed for correct stack 90 /// adjustment during unwind. 91 FRAME_TO_ARGS_OFFSET, 92 93 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical 94 /// Frame Address (CFA), generally the value of the stack pointer at the 95 /// call site in the previous frame. 96 EH_DWARF_CFA, 97 98 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 99 /// 'eh_return' gcc dwarf builtin, which is used to return from 100 /// exception. The general meaning is: adjust stack by OFFSET and pass 101 /// execution to HANDLER. Many platform-related details also :) 102 EH_RETURN, 103 104 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 105 /// This corresponds to the eh.sjlj.setjmp intrinsic. 106 /// It takes an input chain and a pointer to the jump buffer as inputs 107 /// and returns an outchain. 108 EH_SJLJ_SETJMP, 109 110 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 111 /// This corresponds to the eh.sjlj.longjmp intrinsic. 112 /// It takes an input chain and a pointer to the jump buffer as inputs 113 /// and returns an outchain. 114 EH_SJLJ_LONGJMP, 115 116 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) 117 /// The target initializes the dispatch table here. 118 EH_SJLJ_SETUP_DISPATCH, 119 120 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 121 /// simplification, or lowering of the constant. They are used for constants 122 /// which are known to fit in the immediate fields of their users, or for 123 /// carrying magic numbers which are not values which need to be 124 /// materialized in registers. 125 TargetConstant, 126 TargetConstantFP, 127 128 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 129 /// anything else with this node, and this is valid in the target-specific 130 /// dag, turning into a GlobalAddress operand. 131 TargetGlobalAddress, 132 TargetGlobalTLSAddress, 133 TargetFrameIndex, 134 TargetJumpTable, 135 TargetConstantPool, 136 TargetExternalSymbol, 137 TargetBlockAddress, 138 139 MCSymbol, 140 141 /// TargetIndex - Like a constant pool entry, but with completely 142 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 143 /// 64-bit index. Targets can use this however they like. 144 TargetIndex, 145 146 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 147 /// This node represents a target intrinsic function with no side effects. 148 /// The first operand is the ID number of the intrinsic from the 149 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 150 /// node returns the result of the intrinsic. 151 INTRINSIC_WO_CHAIN, 152 153 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 154 /// This node represents a target intrinsic function with side effects that 155 /// returns a result. The first operand is a chain pointer. The second is 156 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 157 /// operands to the intrinsic follow. The node has two results, the result 158 /// of the intrinsic and an output chain. 159 INTRINSIC_W_CHAIN, 160 161 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 162 /// This node represents a target intrinsic function with side effects that 163 /// does not return a result. The first operand is a chain pointer. The 164 /// second is the ID number of the intrinsic from the llvm::Intrinsic 165 /// namespace. The operands to the intrinsic follow. 166 INTRINSIC_VOID, 167 168 /// CopyToReg - This node has three operands: a chain, a register number to 169 /// set to this value, and a value. 170 CopyToReg, 171 172 /// CopyFromReg - This node indicates that the input value is a virtual or 173 /// physical register that is defined outside of the scope of this 174 /// SelectionDAG. The register is available from the RegisterSDNode object. 175 CopyFromReg, 176 177 /// UNDEF - An undefined node. 178 UNDEF, 179 180 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 181 /// a Constant, which is required to be operand #1) half of the integer or 182 /// float value specified as operand #0. This is only for use before 183 /// legalization, for values that will be broken into multiple registers. 184 EXTRACT_ELEMENT, 185 186 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 187 /// Given two values of the same integer value type, this produces a value 188 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 189 /// legalization. The lower part of the composite value should be in 190 /// element 0 and the upper part should be in element 1. 191 BUILD_PAIR, 192 193 /// MERGE_VALUES - This node takes multiple discrete operands and returns 194 /// them all as its individual results. This nodes has exactly the same 195 /// number of inputs and outputs. This node is useful for some pieces of the 196 /// code generator that want to think about a single node with multiple 197 /// results, not multiple nodes. 198 MERGE_VALUES, 199 200 /// Simple integer binary arithmetic operators. 201 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 202 203 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 204 /// a signed/unsigned value of type i[2*N], and return the full value as 205 /// two results, each of type iN. 206 SMUL_LOHI, UMUL_LOHI, 207 208 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 209 /// remainder result. 210 SDIVREM, UDIVREM, 211 212 /// CARRY_FALSE - This node is used when folding other nodes, 213 /// like ADDC/SUBC, which indicate the carry result is always false. 214 CARRY_FALSE, 215 216 /// Carry-setting nodes for multiple precision addition and subtraction. 217 /// These nodes take two operands of the same value type, and produce two 218 /// results. The first result is the normal add or sub result, the second 219 /// result is the carry flag result. 220 /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY. 221 /// They are kept around for now to provide a smooth transition path 222 /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed. 223 ADDC, SUBC, 224 225 /// Carry-using nodes for multiple precision addition and subtraction. These 226 /// nodes take three operands: The first two are the normal lhs and rhs to 227 /// the add or sub, and the third is the input carry flag. These nodes 228 /// produce two results; the normal result of the add or sub, and the output 229 /// carry flag. These nodes both read and write a carry flag to allow them 230 /// to them to be chained together for add and sub of arbitrarily large 231 /// values. 232 ADDE, SUBE, 233 234 /// Carry-using nodes for multiple precision addition and subtraction. 235 /// These nodes take three operands: The first two are the normal lhs and 236 /// rhs to the add or sub, and the third is a boolean indicating if there 237 /// is an incoming carry. These nodes produce two results: the normal 238 /// result of the add or sub, and the output carry so they can be chained 239 /// together. The use of this opcode is preferable to adde/sube if the 240 /// target supports it, as the carry is a regular value rather than a 241 /// glue, which allows further optimisation. 242 ADDCARRY, SUBCARRY, 243 244 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 245 /// These nodes take two operands: the normal LHS and RHS to the add. They 246 /// produce two results: the normal result of the add, and a boolean that 247 /// indicates if an overflow occurred (*not* a flag, because it may be store 248 /// to memory, etc.). If the type of the boolean is not i1 then the high 249 /// bits conform to getBooleanContents. 250 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 251 SADDO, UADDO, 252 253 /// Same for subtraction. 254 SSUBO, USUBO, 255 256 /// Same for multiplication. 257 SMULO, UMULO, 258 259 /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 260 /// integers with the same bit width (W). If the true value of LHS + RHS 261 /// exceeds the largest value that can be represented by W bits, the 262 /// resulting value is this maximum value. Otherwise, if this value is less 263 /// than the smallest value that can be represented by W bits, the 264 /// resulting value is this minimum value. 265 SADDSAT, UADDSAT, 266 267 /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 268 /// integers with the same bit width (W). If the true value of LHS - RHS 269 /// exceeds the largest value that can be represented by W bits, the 270 /// resulting value is this maximum value. Otherwise, if this value is less 271 /// than the smallest value that can be represented by W bits, the 272 /// resulting value is this minimum value. 273 SSUBSAT, USUBSAT, 274 275 /// RESULT = SMULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 276 /// 2 integers with the same width and scale. SCALE represents the scale of 277 /// both operands as fixed point numbers. This SCALE parameter must be a 278 /// constant integer. A scale of zero is effectively performing 279 /// multiplication on 2 integers. 280 SMULFIX, 281 282 /// Simple binary floating point operators. 283 FADD, FSUB, FMUL, FDIV, FREM, 284 285 /// Constrained versions of the binary floating point operators. 286 /// These will be lowered to the simple operators before final selection. 287 /// They are used to limit optimizations while the DAG is being 288 /// optimized. 289 STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM, 290 STRICT_FMA, 291 292 /// Constrained versions of libm-equivalent floating point intrinsics. 293 /// These will be lowered to the equivalent non-constrained pseudo-op 294 /// (or expanded to the equivalent library call) before final selection. 295 /// They are used to limit optimizations while the DAG is being optimized. 296 STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS, 297 STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2, 298 STRICT_FRINT, STRICT_FNEARBYINT, STRICT_FMAXNUM, STRICT_FMINNUM, 299 STRICT_FCEIL, STRICT_FFLOOR, STRICT_FROUND, STRICT_FTRUNC, 300 301 /// FMA - Perform a * b + c with no intermediate rounding step. 302 FMA, 303 304 /// FMAD - Perform a * b + c, while getting the same result as the 305 /// separately rounded operations. 306 FMAD, 307 308 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 309 /// DAG node does not require that X and Y have the same type, just that 310 /// they are both floating point. X and the result must have the same type. 311 /// FCOPYSIGN(f32, f64) is allowed. 312 FCOPYSIGN, 313 314 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 315 /// value as an integer 0/1 value. 316 FGETSIGN, 317 318 /// Returns platform specific canonical encoding of a floating point number. 319 FCANONICALIZE, 320 321 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 322 /// specified, possibly variable, elements. The number of elements is 323 /// required to be a power of two. The types of the operands must all be 324 /// the same and must match the vector element type, except that integer 325 /// types are allowed to be larger than the element type, in which case 326 /// the operands are implicitly truncated. 327 BUILD_VECTOR, 328 329 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 330 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 331 /// element type then VAL is truncated before replacement. 332 INSERT_VECTOR_ELT, 333 334 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 335 /// identified by the (potentially variable) element number IDX. If the 336 /// return type is an integer type larger than the element type of the 337 /// vector, the result is extended to the width of the return type. In 338 /// that case, the high bits are undefined. 339 EXTRACT_VECTOR_ELT, 340 341 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 342 /// vector type with the same length and element type, this produces a 343 /// concatenated vector result value, with length equal to the sum of the 344 /// lengths of the input vectors. 345 CONCAT_VECTORS, 346 347 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 348 /// with VECTOR2 inserted into VECTOR1 at the (potentially 349 /// variable) element number IDX, which must be a multiple of the 350 /// VECTOR2 vector length. The elements of VECTOR1 starting at 351 /// IDX are overwritten with VECTOR2. Elements IDX through 352 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 353 INSERT_SUBVECTOR, 354 355 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 356 /// vector value) starting with the element number IDX, which must be a 357 /// constant multiple of the result vector length. 358 EXTRACT_SUBVECTOR, 359 360 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 361 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 362 /// values that indicate which value (or undef) each result element will 363 /// get. These constant ints are accessible through the 364 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 365 /// 'vperm' instruction, except that the indices must be constants and are 366 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 367 VECTOR_SHUFFLE, 368 369 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 370 /// scalar value into element 0 of the resultant vector type. The top 371 /// elements 1 to N-1 of the N-element vector are undefined. The type 372 /// of the operand must match the vector element type, except when they 373 /// are integer types. In this case the operand is allowed to be wider 374 /// than the vector element type, and is implicitly truncated to it. 375 SCALAR_TO_VECTOR, 376 377 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 378 /// producing an unsigned/signed value of type i[2*N], then return the top 379 /// part. 380 MULHU, MULHS, 381 382 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned 383 /// integers. 384 SMIN, SMAX, UMIN, UMAX, 385 386 /// Bitwise operators - logical and, logical or, logical xor. 387 AND, OR, XOR, 388 389 /// ABS - Determine the unsigned absolute value of a signed integer value of 390 /// the same bitwidth. 391 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow 392 /// is performed. 393 ABS, 394 395 /// Shift and rotation operations. After legalization, the type of the 396 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 397 /// the shift amount can be any type, but care must be taken to ensure it is 398 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 399 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 400 /// to represent the shift amount. 401 /// When the 1st operand is a vector, the shift amount must be in the same 402 /// type. (TLI.getShiftAmountTy() will return the same type when the input 403 /// type is a vector.) 404 /// For rotates and funnel shifts, the shift amount is treated as an unsigned 405 /// amount modulo the element size of the first operand. 406 /// 407 /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount. 408 /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 409 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 410 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, 411 412 /// Byte Swap and Counting operators. 413 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, 414 415 /// Bit counting operators with an undefined result for zero inputs. 416 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 417 418 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 419 /// i1 then the high bits must conform to getBooleanContents. 420 SELECT, 421 422 /// Select with a vector condition (op #0) and two vector operands (ops #1 423 /// and #2), returning a vector result. All vectors have the same length. 424 /// Much like the scalar select and setcc, each bit in the condition selects 425 /// whether the corresponding result element is taken from op #1 or op #2. 426 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 427 /// change the condition type in order to match the VSELECT node using a 428 /// pattern. The condition follows the BooleanContent format of the target. 429 VSELECT, 430 431 /// Select with condition operator - This selects between a true value and 432 /// a false value (ops #2 and #3) based on the boolean result of comparing 433 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 434 /// condition code in op #4, a CondCodeSDNode. 435 SELECT_CC, 436 437 /// SetCC operator - This evaluates to a true value iff the condition is 438 /// true. If the result value type is not i1 then the high bits conform 439 /// to getBooleanContents. The operands to this are the left and right 440 /// operands to compare (ops #0, and #1) and the condition code to compare 441 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 442 /// then the result type must also be a vector type. 443 SETCC, 444 445 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but 446 /// op #2 is a boolean indicating if there is an incoming carry. This 447 /// operator checks the result of "LHS - RHS - Carry", and can be used to 448 /// compare two wide integers: 449 /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc). 450 /// Only valid for integers. 451 SETCCCARRY, 452 453 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 454 /// integer shift operations. The operation ordering is: 455 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 456 SHL_PARTS, SRA_PARTS, SRL_PARTS, 457 458 /// Conversion operators. These are all single input single output 459 /// operations. For all of these, the result type must be strictly 460 /// wider or narrower (depending on the operation) than the source 461 /// type. 462 463 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 464 /// into new bits. 465 SIGN_EXTEND, 466 467 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 468 ZERO_EXTEND, 469 470 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 471 ANY_EXTEND, 472 473 /// TRUNCATE - Completely drop the high bits. 474 TRUNCATE, 475 476 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 477 /// depends on the first letter) to floating point. 478 SINT_TO_FP, 479 UINT_TO_FP, 480 481 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 482 /// sign extend a small value in a large integer register (e.g. sign 483 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 484 /// with the 7th bit). The size of the smaller type is indicated by the 1th 485 /// operand, a ValueType node. 486 SIGN_EXTEND_INREG, 487 488 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 489 /// in-register any-extension of the low lanes of an integer vector. The 490 /// result type must have fewer elements than the operand type, and those 491 /// elements must be larger integer types such that the total size of the 492 /// operand type is less than or equal to the size of the result type. Each 493 /// of the low operand elements is any-extended into the corresponding, 494 /// wider result elements with the high bits becoming undef. 495 /// NOTE: The type legalizer prefers to make the operand and result size 496 /// the same to allow expansion to shuffle vector during op legalization. 497 ANY_EXTEND_VECTOR_INREG, 498 499 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 500 /// in-register sign-extension of the low lanes of an integer vector. The 501 /// result type must have fewer elements than the operand type, and those 502 /// elements must be larger integer types such that the total size of the 503 /// operand type is less than or equal to the size of the result type. Each 504 /// of the low operand elements is sign-extended into the corresponding, 505 /// wider result elements. 506 /// NOTE: The type legalizer prefers to make the operand and result size 507 /// the same to allow expansion to shuffle vector during op legalization. 508 SIGN_EXTEND_VECTOR_INREG, 509 510 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 511 /// in-register zero-extension of the low lanes of an integer vector. The 512 /// result type must have fewer elements than the operand type, and those 513 /// elements must be larger integer types such that the total size of the 514 /// operand type is less than or equal to the size of the result type. Each 515 /// of the low operand elements is zero-extended into the corresponding, 516 /// wider result elements. 517 /// NOTE: The type legalizer prefers to make the operand and result size 518 /// the same to allow expansion to shuffle vector during op legalization. 519 ZERO_EXTEND_VECTOR_INREG, 520 521 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 522 /// integer. These have the same semantics as fptosi and fptoui in IR. If 523 /// the FP value cannot fit in the integer type, the results are undefined. 524 FP_TO_SINT, 525 FP_TO_UINT, 526 527 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 528 /// down to the precision of the destination VT. TRUNC is a flag, which is 529 /// always an integer that is zero or one. If TRUNC is 0, this is a 530 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 531 /// value of Y. 532 /// 533 /// The TRUNC = 1 case is used in cases where we know that the value will 534 /// not be modified by the node, because Y is not using any of the extra 535 /// precision of source type. This allows certain transformations like 536 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 537 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 538 FP_ROUND, 539 540 /// FLT_ROUNDS_ - Returns current rounding mode: 541 /// -1 Undefined 542 /// 0 Round to 0 543 /// 1 Round to nearest 544 /// 2 Round to +inf 545 /// 3 Round to -inf 546 FLT_ROUNDS_, 547 548 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 549 /// rounds it to a floating point value. It then promotes it and returns it 550 /// in a register of the same size. This operation effectively just 551 /// discards excess precision. The type to round down to is specified by 552 /// the VT operand, a VTSDNode. 553 FP_ROUND_INREG, 554 555 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 556 FP_EXTEND, 557 558 /// BITCAST - This operator converts between integer, vector and FP 559 /// values, as if the value was stored to memory with one type and loaded 560 /// from the same address with the other type (or equivalently for vector 561 /// format conversions, etc). The source and result are required to have 562 /// the same bit size (e.g. f32 <-> i32). This can also be used for 563 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 564 /// getNode(). 565 /// 566 /// This operator is subtly different from the bitcast instruction from 567 /// LLVM-IR since this node may change the bits in the register. For 568 /// example, this occurs on big-endian NEON and big-endian MSA where the 569 /// layout of the bits in the register depends on the vector type and this 570 /// operator acts as a shuffle operation for some vector type combinations. 571 BITCAST, 572 573 /// ADDRSPACECAST - This operator converts between pointers of different 574 /// address spaces. 575 ADDRSPACECAST, 576 577 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 578 /// and truncation for half-precision (16 bit) floating numbers. These nodes 579 /// form a semi-softened interface for dealing with f16 (as an i16), which 580 /// is often a storage-only type but has native conversions. 581 FP16_TO_FP, FP_TO_FP16, 582 583 /// Perform various unary floating-point operations inspired by libm. 584 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, 585 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 586 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 587 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two 588 /// values. 589 // 590 /// In the case where a single input is a NaN (either signaling or quiet), 591 /// the non-NaN input is returned. 592 /// 593 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 594 FMINNUM, FMAXNUM, 595 596 /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on 597 /// two values, following the IEEE-754 2008 definition. This differs from 598 /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a 599 /// signaling NaN, returns a quiet NaN. 600 FMINNUM_IEEE, FMAXNUM_IEEE, 601 602 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 603 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008 604 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics. 605 FMINIMUM, FMAXIMUM, 606 607 /// FSINCOS - Compute both fsin and fcos as a single operation. 608 FSINCOS, 609 610 /// LOAD and STORE have token chains as their first operand, then the same 611 /// operands as an LLVM load/store instruction, then an offset node that 612 /// is added / subtracted from the base pointer to form the address (for 613 /// indexed memory ops). 614 LOAD, STORE, 615 616 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 617 /// to a specified boundary. This node always has two return values: a new 618 /// stack pointer value and a chain. The first operand is the token chain, 619 /// the second is the number of bytes to allocate, and the third is the 620 /// alignment boundary. The size is guaranteed to be a multiple of the 621 /// stack alignment, and the alignment is guaranteed to be bigger than the 622 /// stack alignment (if required) or 0 to get standard stack alignment. 623 DYNAMIC_STACKALLOC, 624 625 /// Control flow instructions. These all have token chains. 626 627 /// BR - Unconditional branch. The first operand is the chain 628 /// operand, the second is the MBB to branch to. 629 BR, 630 631 /// BRIND - Indirect branch. The first operand is the chain, the second 632 /// is the value to branch to, which must be of the same type as the 633 /// target's pointer type. 634 BRIND, 635 636 /// BR_JT - Jumptable branch. The first operand is the chain, the second 637 /// is the jumptable index, the last one is the jumptable entry index. 638 BR_JT, 639 640 /// BRCOND - Conditional branch. The first operand is the chain, the 641 /// second is the condition, the third is the block to branch to if the 642 /// condition is true. If the type of the condition is not i1, then the 643 /// high bits must conform to getBooleanContents. 644 BRCOND, 645 646 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 647 /// that the condition is represented as condition code, and two nodes to 648 /// compare, rather than as a combined SetCC node. The operands in order 649 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 650 BR_CC, 651 652 /// INLINEASM - Represents an inline asm block. This node always has two 653 /// return values: a chain and a flag result. The inputs are as follows: 654 /// Operand #0 : Input chain. 655 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 656 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 657 /// Operand #3 : HasSideEffect, IsAlignStack bits. 658 /// After this, it is followed by a list of operands with this format: 659 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 660 /// of operands that follow, etc. See InlineAsm.h. 661 /// ... however many operands ... 662 /// Operand #last: Optional, an incoming flag. 663 /// 664 /// The variable width operands are required to represent target addressing 665 /// modes as a single "operand", even though they may have multiple 666 /// SDOperands. 667 INLINEASM, 668 669 /// EH_LABEL - Represents a label in mid basic block used to track 670 /// locations needed for debug and exception handling tables. These nodes 671 /// take a chain as input and return a chain. 672 EH_LABEL, 673 674 /// ANNOTATION_LABEL - Represents a mid basic block label used by 675 /// annotations. This should remain within the basic block and be ordered 676 /// with respect to other call instructions, but loads and stores may float 677 /// past it. 678 ANNOTATION_LABEL, 679 680 /// CATCHPAD - Represents a catchpad instruction. 681 CATCHPAD, 682 683 /// CATCHRET - Represents a return from a catch block funclet. Used for 684 /// MSVC compatible exception handling. Takes a chain operand and a 685 /// destination basic block operand. 686 CATCHRET, 687 688 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for 689 /// MSVC compatible exception handling. Takes only a chain operand. 690 CLEANUPRET, 691 692 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 693 /// value, the same type as the pointer type for the system, and an output 694 /// chain. 695 STACKSAVE, 696 697 /// STACKRESTORE has two operands, an input chain and a pointer to restore 698 /// to it returns an output chain. 699 STACKRESTORE, 700 701 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 702 /// of a call sequence, and carry arbitrary information that target might 703 /// want to know. The first operand is a chain, the rest are specified by 704 /// the target and not touched by the DAG optimizers. 705 /// Targets that may use stack to pass call arguments define additional 706 /// operands: 707 /// - size of the call frame part that must be set up within the 708 /// CALLSEQ_START..CALLSEQ_END pair, 709 /// - part of the call frame prepared prior to CALLSEQ_START. 710 /// Both these parameters must be constants, their sum is the total call 711 /// frame size. 712 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 713 CALLSEQ_START, // Beginning of a call sequence 714 CALLSEQ_END, // End of a call sequence 715 716 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 717 /// and the alignment. It returns a pair of values: the vaarg value and a 718 /// new chain. 719 VAARG, 720 721 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 722 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 723 /// source. 724 VACOPY, 725 726 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 727 /// pointer, and a SRCVALUE. 728 VAEND, VASTART, 729 730 /// SRCVALUE - This is a node type that holds a Value* that is used to 731 /// make reference to a value in the LLVM IR. 732 SRCVALUE, 733 734 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 735 /// reference metadata in the IR. 736 MDNODE_SDNODE, 737 738 /// PCMARKER - This corresponds to the pcmarker intrinsic. 739 PCMARKER, 740 741 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 742 /// It produces a chain and one i64 value. The only operand is a chain. 743 /// If i64 is not legal, the result will be expanded into smaller values. 744 /// Still, it returns an i64, so targets should set legality for i64. 745 /// The result is the content of the architecture-specific cycle 746 /// counter-like register (or other high accuracy low latency clock source). 747 READCYCLECOUNTER, 748 749 /// HANDLENODE node - Used as a handle for various purposes. 750 HANDLENODE, 751 752 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 753 /// takes as input a token chain, the pointer to the trampoline, the pointer 754 /// to the nested function, the pointer to pass for the 'nest' parameter, a 755 /// SRCVALUE for the trampoline and another for the nested function 756 /// (allowing targets to access the original Function*). 757 /// It produces a token chain as output. 758 INIT_TRAMPOLINE, 759 760 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 761 /// It takes a pointer to the trampoline and produces a (possibly) new 762 /// pointer to the same trampoline with platform-specific adjustments 763 /// applied. The pointer it returns points to an executable block of code. 764 ADJUST_TRAMPOLINE, 765 766 /// TRAP - Trapping instruction 767 TRAP, 768 769 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 770 DEBUGTRAP, 771 772 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 773 /// is the chain. The other operands are the address to prefetch, 774 /// read / write specifier, locality specifier and instruction / data cache 775 /// specifier. 776 PREFETCH, 777 778 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 779 /// This corresponds to the fence instruction. It takes an input chain, and 780 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 781 ATOMIC_FENCE, 782 783 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 784 /// This corresponds to "load atomic" instruction. 785 ATOMIC_LOAD, 786 787 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 788 /// This corresponds to "store atomic" instruction. 789 ATOMIC_STORE, 790 791 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 792 /// For double-word atomic operations: 793 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 794 /// swapLo, swapHi) 795 /// This corresponds to the cmpxchg instruction. 796 ATOMIC_CMP_SWAP, 797 798 /// Val, Success, OUTCHAIN 799 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 800 /// N.b. this is still a strong cmpxchg operation, so 801 /// Success == "Val == cmp". 802 ATOMIC_CMP_SWAP_WITH_SUCCESS, 803 804 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 805 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 806 /// For double-word atomic operations: 807 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 808 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 809 /// These correspond to the atomicrmw instruction. 810 ATOMIC_SWAP, 811 ATOMIC_LOAD_ADD, 812 ATOMIC_LOAD_SUB, 813 ATOMIC_LOAD_AND, 814 ATOMIC_LOAD_CLR, 815 ATOMIC_LOAD_OR, 816 ATOMIC_LOAD_XOR, 817 ATOMIC_LOAD_NAND, 818 ATOMIC_LOAD_MIN, 819 ATOMIC_LOAD_MAX, 820 ATOMIC_LOAD_UMIN, 821 ATOMIC_LOAD_UMAX, 822 823 // Masked load and store - consecutive vector load and store operations 824 // with additional mask operand that prevents memory accesses to the 825 // masked-off lanes. 826 // 827 // Val, OutChain = MLOAD(BasePtr, Mask, PassThru) 828 // OutChain = MSTORE(Value, BasePtr, Mask) 829 MLOAD, MSTORE, 830 831 // Masked gather and scatter - load and store operations for a vector of 832 // random addresses with additional mask operand that prevents memory 833 // accesses to the masked-off lanes. 834 // 835 // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale) 836 // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale) 837 // 838 // The Index operand can have more vector elements than the other operands 839 // due to type legalization. The extra elements are ignored. 840 MGATHER, MSCATTER, 841 842 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 843 /// is the chain and the second operand is the alloca pointer. 844 LIFETIME_START, LIFETIME_END, 845 846 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the 847 /// beginning and end of GC transition sequence, and carry arbitrary 848 /// information that target might need for lowering. The first operand is 849 /// a chain, the rest are specified by the target and not touched by the DAG 850 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be 851 /// nested. 852 GC_TRANSITION_START, 853 GC_TRANSITION_END, 854 855 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of 856 /// the most recent dynamic alloca. For most targets that would be 0, but 857 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time 858 /// known nonzero constant. The only operand here is the chain. 859 GET_DYNAMIC_AREA_OFFSET, 860 861 /// Generic reduction nodes. These nodes represent horizontal vector 862 /// reduction operations, producing a scalar result. 863 /// The STRICT variants perform reductions in sequential order. The first 864 /// operand is an initial scalar accumulator value, and the second operand 865 /// is the vector to reduce. 866 VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL, 867 /// These reductions are non-strict, and have a single vector operand. 868 VECREDUCE_FADD, VECREDUCE_FMUL, 869 VECREDUCE_ADD, VECREDUCE_MUL, 870 VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR, 871 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, 872 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants. 873 VECREDUCE_FMAX, VECREDUCE_FMIN, 874 875 /// BUILTIN_OP_END - This must be the last enum value in this list. 876 /// The target-specific pre-isel opcode values start here. 877 BUILTIN_OP_END 878 }; 879 880 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 881 /// which do not reference a specific memory location should be less than 882 /// this value. Those that do must not be less than this value, and can 883 /// be used with SelectionDAG::getMemIntrinsicNode. 884 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+400; 885 886 //===--------------------------------------------------------------------===// 887 /// MemIndexedMode enum - This enum defines the load / store indexed 888 /// addressing modes. 889 /// 890 /// UNINDEXED "Normal" load / store. The effective address is already 891 /// computed and is available in the base pointer. The offset 892 /// operand is always undefined. In addition to producing a 893 /// chain, an unindexed load produces one value (result of the 894 /// load); an unindexed store does not produce a value. 895 /// 896 /// PRE_INC Similar to the unindexed mode where the effective address is 897 /// PRE_DEC the value of the base pointer add / subtract the offset. 898 /// It considers the computation as being folded into the load / 899 /// store operation (i.e. the load / store does the address 900 /// computation as well as performing the memory transaction). 901 /// The base operand is always undefined. In addition to 902 /// producing a chain, pre-indexed load produces two values 903 /// (result of the load and the result of the address 904 /// computation); a pre-indexed store produces one value (result 905 /// of the address computation). 906 /// 907 /// POST_INC The effective address is the value of the base pointer. The 908 /// POST_DEC value of the offset operand is then added to / subtracted 909 /// from the base after memory transaction. In addition to 910 /// producing a chain, post-indexed load produces two values 911 /// (the result of the load and the result of the base +/- offset 912 /// computation); a post-indexed store produces one value (the 913 /// the result of the base +/- offset computation). 914 enum MemIndexedMode { 915 UNINDEXED = 0, 916 PRE_INC, 917 PRE_DEC, 918 POST_INC, 919 POST_DEC 920 }; 921 922 static const int LAST_INDEXED_MODE = POST_DEC + 1; 923 924 //===--------------------------------------------------------------------===// 925 /// LoadExtType enum - This enum defines the three variants of LOADEXT 926 /// (load with extension). 927 /// 928 /// SEXTLOAD loads the integer operand and sign extends it to a larger 929 /// integer result type. 930 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 931 /// integer result type. 932 /// EXTLOAD is used for two things: floating point extending loads and 933 /// integer extending loads [the top bits are undefined]. 934 enum LoadExtType { 935 NON_EXTLOAD = 0, 936 EXTLOAD, 937 SEXTLOAD, 938 ZEXTLOAD 939 }; 940 941 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1; 942 943 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 944 945 //===--------------------------------------------------------------------===// 946 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 947 /// below work out, when considering SETFALSE (something that never exists 948 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 949 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 950 /// to. If the "N" column is 1, the result of the comparison is undefined if 951 /// the input is a NAN. 952 /// 953 /// All of these (except for the 'always folded ops') should be handled for 954 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 955 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 956 /// 957 /// Note that these are laid out in a specific order to allow bit-twiddling 958 /// to transform conditions. 959 enum CondCode { 960 // Opcode N U L G E Intuitive operation 961 SETFALSE, // 0 0 0 0 Always false (always folded) 962 SETOEQ, // 0 0 0 1 True if ordered and equal 963 SETOGT, // 0 0 1 0 True if ordered and greater than 964 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 965 SETOLT, // 0 1 0 0 True if ordered and less than 966 SETOLE, // 0 1 0 1 True if ordered and less than or equal 967 SETONE, // 0 1 1 0 True if ordered and operands are unequal 968 SETO, // 0 1 1 1 True if ordered (no nans) 969 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 970 SETUEQ, // 1 0 0 1 True if unordered or equal 971 SETUGT, // 1 0 1 0 True if unordered or greater than 972 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 973 SETULT, // 1 1 0 0 True if unordered or less than 974 SETULE, // 1 1 0 1 True if unordered, less than, or equal 975 SETUNE, // 1 1 1 0 True if unordered or not equal 976 SETTRUE, // 1 1 1 1 Always true (always folded) 977 // Don't care operations: undefined if the input is a nan. 978 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 979 SETEQ, // 1 X 0 0 1 True if equal 980 SETGT, // 1 X 0 1 0 True if greater than 981 SETGE, // 1 X 0 1 1 True if greater than or equal 982 SETLT, // 1 X 1 0 0 True if less than 983 SETLE, // 1 X 1 0 1 True if less than or equal 984 SETNE, // 1 X 1 1 0 True if not equal 985 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 986 987 SETCC_INVALID // Marker value. 988 }; 989 990 /// Return true if this is a setcc instruction that performs a signed 991 /// comparison when used with integer operands. isSignedIntSetCC(CondCode Code)992 inline bool isSignedIntSetCC(CondCode Code) { 993 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 994 } 995 996 /// Return true if this is a setcc instruction that performs an unsigned 997 /// comparison when used with integer operands. isUnsignedIntSetCC(CondCode Code)998 inline bool isUnsignedIntSetCC(CondCode Code) { 999 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 1000 } 1001 1002 /// Return true if the specified condition returns true if the two operands to 1003 /// the condition are equal. Note that if one of the two operands is a NaN, 1004 /// this value is meaningless. isTrueWhenEqual(CondCode Cond)1005 inline bool isTrueWhenEqual(CondCode Cond) { 1006 return ((int)Cond & 1) != 0; 1007 } 1008 1009 /// This function returns 0 if the condition is always false if an operand is 1010 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if 1011 /// the condition is undefined if the operand is a NaN. getUnorderedFlavor(CondCode Cond)1012 inline unsigned getUnorderedFlavor(CondCode Cond) { 1013 return ((int)Cond >> 3) & 3; 1014 } 1015 1016 /// Return the operation corresponding to !(X op Y), where 'op' is a valid 1017 /// SetCC operation. 1018 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 1019 1020 /// Return the operation corresponding to (Y op X) when given the operation 1021 /// for (X op Y). 1022 CondCode getSetCCSwappedOperands(CondCode Operation); 1023 1024 /// Return the result of a logical OR between different comparisons of 1025 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns 1026 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 1027 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 1028 1029 /// Return the result of a logical AND between different comparisons of 1030 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns 1031 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 1032 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 1033 1034 } // end llvm::ISD namespace 1035 1036 } // end llvm namespace 1037 1038 #endif 1039