Searched defs:SubReg0 (Results 1 – 7 of 7) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 206 unsigned SubReg0; in isProfitableToTransform() local
298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
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| H A D | AArch64ISelLowering.cpp | 17153 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32); in createGPRPairNode() local
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1843 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
1854 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode() local
1865 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode() local
1876 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode() local
1888 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createQuadSRegsNode() local
1903 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createQuadDRegsNode() local
1918 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQuadQRegsNode() local
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| H A D | ARMISelLowering.cpp | 10040 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 187 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl() local
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 140 unsigned RegClassID, unsigned SubReg0) { in createTupleImpl()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 846 SDValue RC, SubReg0, SubReg1; in Select() local
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