1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2019 Marvell International Ltd.
3  */
4 
5 #ifndef __OTX2_SDP_HW_H_
6 #define __OTX2_SDP_HW_H_
7 
8 /* SDP VF IOQs */
9 #define SDP_MIN_RINGS_PER_VF        (1)
10 #define SDP_MAX_RINGS_PER_VF        (8)
11 
12 /* SDP VF IQ configuration */
13 #define SDP_VF_MAX_IQ_DESCRIPTORS   (512)
14 #define SDP_VF_MIN_IQ_DESCRIPTORS   (128)
15 
16 #define SDP_VF_DB_MIN               (1)
17 #define SDP_VF_DB_TIMEOUT           (1)
18 #define SDP_VF_INTR_THRESHOLD       (0xFFFFFFFF)
19 
20 #define SDP_VF_64BYTE_INSTR         (64)
21 #define SDP_VF_32BYTE_INSTR         (32)
22 
23 /* SDP VF OQ configuration */
24 #define SDP_VF_MAX_OQ_DESCRIPTORS   (512)
25 #define SDP_VF_MIN_OQ_DESCRIPTORS   (128)
26 #define SDP_VF_OQ_BUF_SIZE          (2048)
27 #define SDP_VF_OQ_REFIL_THRESHOLD   (16)
28 
29 #define SDP_VF_OQ_INFOPTR_MODE      (1)
30 #define SDP_VF_OQ_BUFPTR_MODE       (0)
31 
32 #define SDP_VF_OQ_INTR_PKT          (1)
33 #define SDP_VF_OQ_INTR_TIME         (10)
34 #define SDP_VF_CFG_IO_QUEUES        SDP_MAX_RINGS_PER_VF
35 
36 /* Wait time in milliseconds for FLR */
37 #define SDP_VF_PCI_FLR_WAIT         (100)
38 #define SDP_VF_BUSY_LOOP_COUNT      (10000)
39 
40 #define SDP_VF_MAX_IO_QUEUES        SDP_MAX_RINGS_PER_VF
41 #define SDP_VF_MIN_IO_QUEUES        SDP_MIN_RINGS_PER_VF
42 
43 /* SDP VF IOQs per rawdev */
44 #define SDP_VF_MAX_IOQS_PER_RAWDEV      SDP_VF_MAX_IO_QUEUES
45 #define SDP_VF_DEFAULT_IOQS_PER_RAWDEV  SDP_VF_MIN_IO_QUEUES
46 
47 /* SDP VF Register definitions */
48 #define SDP_VF_RING_OFFSET                (0x1ull << 17)
49 
50 /* SDP VF IQ Registers */
51 #define SDP_VF_R_IN_CONTROL_START         (0x10000)
52 #define SDP_VF_R_IN_ENABLE_START          (0x10010)
53 #define SDP_VF_R_IN_INSTR_BADDR_START     (0x10020)
54 #define SDP_VF_R_IN_INSTR_RSIZE_START     (0x10030)
55 #define SDP_VF_R_IN_INSTR_DBELL_START     (0x10040)
56 #define SDP_VF_R_IN_CNTS_START            (0x10050)
57 #define SDP_VF_R_IN_INT_LEVELS_START      (0x10060)
58 #define SDP_VF_R_IN_PKT_CNT_START         (0x10080)
59 #define SDP_VF_R_IN_BYTE_CNT_START        (0x10090)
60 
61 #define SDP_VF_R_IN_CONTROL(ring)  \
62 	(SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
63 
64 #define SDP_VF_R_IN_ENABLE(ring)   \
65 	(SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
66 
67 #define SDP_VF_R_IN_INSTR_BADDR(ring)   \
68 	(SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
69 
70 #define SDP_VF_R_IN_INSTR_RSIZE(ring)   \
71 	(SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
72 
73 #define SDP_VF_R_IN_INSTR_DBELL(ring)   \
74 	(SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
75 
76 #define SDP_VF_R_IN_CNTS(ring)          \
77 	(SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
78 
79 #define SDP_VF_R_IN_INT_LEVELS(ring)    \
80 	(SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
81 
82 #define SDP_VF_R_IN_PKT_CNT(ring)       \
83 	(SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
84 
85 #define SDP_VF_R_IN_BYTE_CNT(ring)          \
86 	(SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
87 
88 /* SDP VF IQ Masks */
89 #define SDP_VF_R_IN_CTL_RPVF_MASK       (0xF)
90 #define	SDP_VF_R_IN_CTL_RPVF_POS        (48)
91 
92 #define SDP_VF_R_IN_CTL_IDLE            (0x1ull << 28)
93 #define SDP_VF_R_IN_CTL_RDSIZE          (0x3ull << 25) /* Setting to max(4) */
94 #define SDP_VF_R_IN_CTL_IS_64B          (0x1ull << 24)
95 #define SDP_VF_R_IN_CTL_D_NSR           (0x1ull << 8)
96 #define SDP_VF_R_IN_CTL_D_ESR           (0x1ull << 6)
97 #define SDP_VF_R_IN_CTL_D_ROR           (0x1ull << 5)
98 #define SDP_VF_R_IN_CTL_NSR             (0x1ull << 3)
99 #define SDP_VF_R_IN_CTL_ESR             (0x1ull << 1)
100 #define SDP_VF_R_IN_CTL_ROR             (0x1ull << 0)
101 
102 #define SDP_VF_R_IN_CTL_MASK  \
103 	(SDP_VF_R_IN_CTL_RDSIZE | SDP_VF_R_IN_CTL_IS_64B)
104 
105 /* SDP VF OQ Registers */
106 #define SDP_VF_R_OUT_CNTS_START              (0x10100)
107 #define SDP_VF_R_OUT_INT_LEVELS_START        (0x10110)
108 #define SDP_VF_R_OUT_SLIST_BADDR_START       (0x10120)
109 #define SDP_VF_R_OUT_SLIST_RSIZE_START       (0x10130)
110 #define SDP_VF_R_OUT_SLIST_DBELL_START       (0x10140)
111 #define SDP_VF_R_OUT_CONTROL_START           (0x10150)
112 #define SDP_VF_R_OUT_ENABLE_START            (0x10160)
113 #define SDP_VF_R_OUT_PKT_CNT_START           (0x10180)
114 #define SDP_VF_R_OUT_BYTE_CNT_START          (0x10190)
115 
116 #define SDP_VF_R_OUT_CONTROL(ring)    \
117 	(SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
118 
119 #define SDP_VF_R_OUT_ENABLE(ring)     \
120 	(SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
121 
122 #define SDP_VF_R_OUT_SLIST_BADDR(ring)  \
123 	(SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
124 
125 #define SDP_VF_R_OUT_SLIST_RSIZE(ring)  \
126 	(SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
127 
128 #define SDP_VF_R_OUT_SLIST_DBELL(ring)  \
129 	(SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
130 
131 #define SDP_VF_R_OUT_CNTS(ring)   \
132 	(SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
133 
134 #define SDP_VF_R_OUT_INT_LEVELS(ring)   \
135 	(SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
136 
137 #define SDP_VF_R_OUT_PKT_CNT(ring)   \
138 	(SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
139 
140 #define SDP_VF_R_OUT_BYTE_CNT(ring)   \
141 	(SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
142 
143 /* SDP VF OQ Masks */
144 #define SDP_VF_R_OUT_CTL_IDLE         (1ull << 40)
145 #define SDP_VF_R_OUT_CTL_ES_I         (1ull << 34)
146 #define SDP_VF_R_OUT_CTL_NSR_I        (1ull << 33)
147 #define SDP_VF_R_OUT_CTL_ROR_I        (1ull << 32)
148 #define SDP_VF_R_OUT_CTL_ES_D         (1ull << 30)
149 #define SDP_VF_R_OUT_CTL_NSR_D        (1ull << 29)
150 #define SDP_VF_R_OUT_CTL_ROR_D        (1ull << 28)
151 #define SDP_VF_R_OUT_CTL_ES_P         (1ull << 26)
152 #define SDP_VF_R_OUT_CTL_NSR_P        (1ull << 25)
153 #define SDP_VF_R_OUT_CTL_ROR_P        (1ull << 24)
154 #define SDP_VF_R_OUT_CTL_IMODE        (1ull << 23)
155 
156 #define SDP_VF_R_OUT_INT_LEVELS_BMODE     (1ull << 63)
157 #define SDP_VF_R_OUT_INT_LEVELS_TIMET     (32)
158 
159 /* SDP Instruction Header */
160 struct sdp_instr_ih {
161 	/* Data Len */
162 	uint64_t tlen:16;
163 
164 	/* Reserved1 */
165 	uint64_t rsvd1:20;
166 
167 	/* PKIND for SDP */
168 	uint64_t pkind:6;
169 
170 	/* Front Data size */
171 	uint64_t fsz:6;
172 
173 	/* No. of entries in gather list */
174 	uint64_t gsz:14;
175 
176 	/* Gather indicator */
177 	uint64_t gather:1;
178 
179 	/* Reserved2 */
180 	uint64_t rsvd2:1;
181 } __rte_packed;
182 
183 #endif /* __OTX2_SDP_HW_H_  */
184 
185