1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 */ 4 5 #ifndef _RTE_VECT_H_ 6 #define _RTE_VECT_H_ 7 8 /** 9 * @file 10 * SIMD vector types and control 11 * 12 * This file defines types to use vector instructions with generic C code 13 * and APIs to enable the code using them. 14 */ 15 16 #include <stdint.h> 17 18 #include <rte_compat.h> 19 20 /* Unsigned vector types */ 21 22 /** 23 * 64 bits vector size to use with unsigned 8 bits elements. 24 * 25 * a = (rte_v64u8_t){ a0, a1, a2, a3, a4, a5, a6, a7 } 26 */ 27 typedef uint8_t rte_v64u8_t __attribute__((vector_size(8), aligned(8))); 28 29 /** 30 * 64 bits vector size to use with unsigned 16 bits elements. 31 * 32 * a = (rte_v64u16_t){ a0, a1, a2, a3 } 33 */ 34 typedef uint16_t rte_v64u16_t __attribute__((vector_size(8), aligned(8))); 35 36 /** 37 * 64 bits vector size to use with unsigned 32 bits elements. 38 * 39 * a = (rte_v64u32_t){ a0, a1 } 40 */ 41 typedef uint32_t rte_v64u32_t __attribute__((vector_size(8), aligned(8))); 42 43 /** 44 * 128 bits vector size to use with unsigned 8 bits elements. 45 * 46 * a = (rte_v128u8_t){ a00, a01, a02, a03, a04, a05, a06, a07, 47 * a08, a09, a10, a11, a12, a13, a14, a15 } 48 */ 49 typedef uint8_t rte_v128u8_t __attribute__((vector_size(16), aligned(16))); 50 51 /** 52 * 128 bits vector size to use with unsigned 16 bits elements. 53 * 54 * a = (rte_v128u16_t){ a0, a1, a2, a3, a4, a5, a6, a7 } 55 */ 56 typedef uint16_t rte_v128u16_t __attribute__((vector_size(16), aligned(16))); 57 58 /** 59 * 128 bits vector size to use with unsigned 32 bits elements. 60 * 61 * a = (rte_v128u32_t){ a0, a1, a2, a3 } 62 */ 63 typedef uint32_t rte_v128u32_t __attribute__((vector_size(16), aligned(16))); 64 65 /** 66 * 128 bits vector size to use with unsigned 64 bits elements. 67 * 68 * a = (rte_v128u64_t){ a0, a1 } 69 */ 70 typedef uint64_t rte_v128u64_t __attribute__((vector_size(16), aligned(16))); 71 72 /** 73 * 256 bits vector size to use with unsigned 8 bits elements. 74 * 75 * a = (rte_v256u8_t){ a00, a01, a02, a03, a04, a05, a06, a07, 76 * a08, a09, a10, a11, a12, a13, a14, a15, 77 * a16, a17, a18, a19, a20, a21, a22, a23, 78 * a24, a25, a26, a27, a28, a29, a30, a31 } 79 */ 80 typedef uint8_t rte_v256u8_t __attribute__((vector_size(32), aligned(32))); 81 82 /** 83 * 256 bits vector size to use with unsigned 16 bits elements. 84 * 85 * a = (rte_v256u16_t){ a00, a01, a02, a03, a04, a05, a06, a07, 86 * a08, a09, a10, a11, a12, a13, a14, a15 } 87 */ 88 typedef uint16_t rte_v256u16_t __attribute__((vector_size(32), aligned(32))); 89 90 /** 91 * 256 bits vector size to use with unsigned 32 bits elements. 92 * 93 * a = (rte_v256u32_t){ a0, a1, a2, a3, a4, a5, a6, a7 } 94 */ 95 typedef uint32_t rte_v256u32_t __attribute__((vector_size(32), aligned(32))); 96 97 /** 98 * 256 bits vector size to use with unsigned 64 bits elements. 99 * 100 * a = (rte_v256u64_t){ a0, a1, a2, a3 } 101 */ 102 typedef uint64_t rte_v256u64_t __attribute__((vector_size(32), aligned(32))); 103 104 105 /* Signed vector types */ 106 107 /** 108 * 64 bits vector size to use with 8 bits elements. 109 * 110 * a = (rte_v64s8_t){ a0, a1, a2, a3, a4, a5, a6, a7 } 111 */ 112 typedef int8_t rte_v64s8_t __attribute__((vector_size(8), aligned(8))); 113 114 /** 115 * 64 bits vector size to use with 16 bits elements. 116 * 117 * a = (rte_v64s16_t){ a0, a1, a2, a3 } 118 */ 119 typedef int16_t rte_v64s16_t __attribute__((vector_size(8), aligned(8))); 120 121 /** 122 * 64 bits vector size to use with 32 bits elements. 123 * 124 * a = (rte_v64s32_t){ a0, a1 } 125 */ 126 typedef int32_t rte_v64s32_t __attribute__((vector_size(8), aligned(8))); 127 128 /** 129 * 128 bits vector size to use with 8 bits elements. 130 * 131 * a = (rte_v128s8_t){ a00, a01, a02, a03, a04, a05, a06, a07, 132 * a08, a09, a10, a11, a12, a13, a14, a15 } 133 */ 134 typedef int8_t rte_v128s8_t __attribute__((vector_size(16), aligned(16))); 135 136 /** 137 * 128 bits vector size to use with 16 bits elements. 138 * 139 * a = (rte_v128s16_t){ a0, a1, a2, a3, a4, a5, a6, a7 } 140 */ 141 typedef int16_t rte_v128s16_t __attribute__((vector_size(16), aligned(16))); 142 143 /** 144 * 128 bits vector size to use with 32 bits elements. 145 * 146 * a = (rte_v128s32_t){ a0, a1, a2, a3 } 147 */ 148 typedef int32_t rte_v128s32_t __attribute__((vector_size(16), aligned(16))); 149 150 /** 151 * 128 bits vector size to use with 64 bits elements. 152 * 153 * a = (rte_v128s64_t){ a1, a2 } 154 */ 155 typedef int64_t rte_v128s64_t __attribute__((vector_size(16), aligned(16))); 156 157 /** 158 * 256 bits vector size to use with 8 bits elements. 159 * 160 * a = (rte_v256s8_t){ a00, a01, a02, a03, a04, a05, a06, a07, 161 * a08, a09, a10, a11, a12, a13, a14, a15, 162 * a16, a17, a18, a19, a20, a21, a22, a23, 163 * a24, a25, a26, a27, a28, a29, a30, a31 } 164 */ 165 typedef int8_t rte_v256s8_t __attribute__((vector_size(32), aligned(32))); 166 167 /** 168 * 256 bits vector size to use with 16 bits elements. 169 * 170 * a = (rte_v256s16_t){ a00, a01, a02, a03, a04, a05, a06, a07, 171 * a08, a09, a10, a11, a12, a13, a14, a15 } 172 */ 173 typedef int16_t rte_v256s16_t __attribute__((vector_size(32), aligned(32))); 174 175 /** 176 * 256 bits vector size to use with 32 bits elements. 177 * 178 * a = (rte_v256s32_t){ a0, a1, a2, a3, a4, a5, a6, a7 } 179 */ 180 typedef int32_t rte_v256s32_t __attribute__((vector_size(32), aligned(32))); 181 182 /** 183 * 256 bits vector size to use with 64 bits elements. 184 * 185 * a = (rte_v256s64_t){ a0, a1, a2, a3 } 186 */ 187 typedef int64_t rte_v256s64_t __attribute__((vector_size(32), aligned(32))); 188 189 /** 190 * The max SIMD bitwidth value to limit vector path selection. 191 */ 192 enum rte_vect_max_simd { 193 RTE_VECT_SIMD_DISABLED = 64, 194 /**< Limits path selection to scalar, disables all vector paths. */ 195 RTE_VECT_SIMD_128 = 128, 196 /**< Limits path selection to SSE/NEON/Altivec or below. */ 197 RTE_VECT_SIMD_256 = 256, /**< Limits path selection to AVX2 or below. */ 198 RTE_VECT_SIMD_512 = 512, /**< Limits path selection to AVX512 or below. */ 199 RTE_VECT_SIMD_MAX = INT16_MAX + 1, 200 /**< 201 * Disables limiting by max SIMD bitwidth, allows all suitable paths. 202 * This value is used as it is a large number and a power of 2. 203 */ 204 }; 205 206 /** 207 * @warning 208 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice 209 * 210 * Get the supported SIMD bitwidth. 211 * 212 * @return 213 * uint16_t bitwidth. 214 */ 215 __rte_experimental 216 uint16_t rte_vect_get_max_simd_bitwidth(void); 217 218 /** 219 * @warning 220 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice 221 * 222 * Set the supported SIMD bitwidth. 223 * This API should only be called once at initialization, before EAL init. 224 * 225 * @param bitwidth 226 * uint16_t bitwidth. 227 * @return 228 * - 0 on success. 229 * - -EINVAL on invalid bitwidth parameter. 230 * - -EPERM if bitwidth is forced. 231 */ 232 __rte_experimental 233 int rte_vect_set_max_simd_bitwidth(uint16_t bitwidth); 234 235 #endif /* _RTE_VECT_H_ */ 236