1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4 #ifndef _ROC_NIX_INL_H_
5 #define _ROC_NIX_INL_H_
6
7 /* ONF INB HW area */
8 #define ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ \
9 PLT_ALIGN(sizeof(struct roc_onf_ipsec_inb_sa), ROC_ALIGN)
10 /* ONF INB SW reserved area */
11 #define ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD 384
12 #define ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ \
13 (ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ + ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD)
14 #define ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2 9
15
16 /* ONF OUTB HW area */
17 #define ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ \
18 PLT_ALIGN(sizeof(struct roc_onf_ipsec_outb_sa), ROC_ALIGN)
19 /* ONF OUTB SW reserved area */
20 #define ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD 128
21 #define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ \
22 (ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD)
23 #define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2 8
24
25 /* OT INB HW area */
26 #define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \
27 PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN)
28 /* OT INB SW reserved area */
29 #define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128
30 #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ \
31 (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD)
32 #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10
33
34 /* OT OUTB HW area */
35 #define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ \
36 PLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN)
37 /* OT OUTB SW reserved area */
38 #define ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD 128
39 #define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ \
40 (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD)
41 #define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2 9
42
43 /* Alignment of SA Base */
44 #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)
45
46 #define ROC_NIX_INL_SA_SOFT_EXP_ERR_MAX_POLL_COUNT 25
47
48 #define ROC_NIX_SOFT_EXP_ERR_RING_MAX_ENTRY_LOG2 16
49
50 #define ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS 4
51
52 #define ROC_NIX_MAX_TOTAL_OUTB_IPSEC_SA \
53 (ROC_IPSEC_ERR_RING_MAX_ENTRY * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS)
54
55 #define ROC_NIX_INL_MAX_SOFT_EXP_RNGS \
56 (PLT_MAX_ETHPORTS * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS)
57
58 /* Reassembly configuration */
59 #define ROC_NIX_INL_REAS_ACTIVE_LIMIT 0xFFF
60 #define ROC_NIX_INL_REAS_ACTIVE_THRESHOLD 10
61 #define ROC_NIX_INL_REAS_ZOMBIE_LIMIT 0xFFF
62 #define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10
63
64 static inline struct roc_onf_ipsec_inb_sa *
roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base,uint64_t idx)65 roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx)
66 {
67 uint64_t off = idx << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2;
68
69 return PLT_PTR_ADD(base, off);
70 }
71
72 static inline struct roc_onf_ipsec_outb_sa *
roc_nix_inl_onf_ipsec_outb_sa(uintptr_t base,uint64_t idx)73 roc_nix_inl_onf_ipsec_outb_sa(uintptr_t base, uint64_t idx)
74 {
75 uint64_t off = idx << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2;
76
77 return PLT_PTR_ADD(base, off);
78 }
79
80 static inline void *
roc_nix_inl_onf_ipsec_inb_sa_sw_rsvd(void * sa)81 roc_nix_inl_onf_ipsec_inb_sa_sw_rsvd(void *sa)
82 {
83 return PLT_PTR_ADD(sa, ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ);
84 }
85
86 static inline void *
roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd(void * sa)87 roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd(void *sa)
88 {
89 return PLT_PTR_ADD(sa, ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ);
90 }
91
92 static inline struct roc_ot_ipsec_inb_sa *
roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base,uint64_t idx)93 roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx)
94 {
95 uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2;
96
97 return PLT_PTR_ADD(base, off);
98 }
99
100 static inline struct roc_ot_ipsec_outb_sa *
roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base,uint64_t idx)101 roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx)
102 {
103 uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2;
104
105 return PLT_PTR_ADD(base, off);
106 }
107
108 static inline void *
roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void * sa)109 roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void *sa)
110 {
111 return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_INB_HW_SZ);
112 }
113
114 static inline void *
roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void * sa)115 roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa)
116 {
117 return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ);
118 }
119
120 /* Inline device SSO Work callback */
121 typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args,
122 uint32_t soft_exp_event);
123
124 struct roc_nix_inl_dev {
125 /* Input parameters */
126 struct plt_pci_device *pci_dev;
127 uint32_t ipsec_in_min_spi;
128 uint32_t ipsec_in_max_spi;
129 bool selftest;
130 bool is_multi_channel;
131 uint16_t channel;
132 uint16_t chan_mask;
133 bool attach_cptlf;
134 bool wqe_skip;
135 uint8_t spb_drop_pc;
136 uint8_t lpb_drop_pc;
137 bool set_soft_exp_poll;
138 /* End of input parameters */
139
140 #define ROC_NIX_INL_MEM_SZ (1280)
141 uint8_t reserved[ROC_NIX_INL_MEM_SZ] __plt_cache_aligned;
142 } __plt_cache_aligned;
143
144 /* NIX Inline Device API */
145 int __roc_api roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev);
146 int __roc_api roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev);
147 void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);
148 bool __roc_api roc_nix_inl_dev_is_probed(void);
149 void __roc_api roc_nix_inl_dev_lock(void);
150 void __roc_api roc_nix_inl_dev_unlock(void);
151 int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
152 uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void);
153
154 /* NIX Inline Inbound API */
155 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
156 int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);
157 bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);
158 uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,
159 bool inl_dev_sa);
160 uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix,
161 bool inl_dev_sa, uint32_t *min,
162 uint32_t *max);
163 uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix,
164 bool inl_dev_sa);
165 uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix,
166 bool inl_dev_sa, uint32_t spi);
167 void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev);
168 int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq);
169 int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq);
170 bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix);
171 struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(struct roc_nix *roc_nix);
172 int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix,
173 uint32_t tag_const, uint8_t tt);
174 int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time,
175 uint16_t max_frags);
176 int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,
177 bool inb_inl_dev);
178
179 /* NIX Inline Outbound API */
180 int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);
181 int __roc_api roc_nix_inl_outb_fini(struct roc_nix *roc_nix);
182 bool __roc_api roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix);
183 uintptr_t __roc_api roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix);
184 struct roc_cpt_lf *__roc_api
185 roc_nix_inl_outb_lf_base_get(struct roc_nix *roc_nix);
186 uint16_t __roc_api roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix);
187 int __roc_api roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args);
188 int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb,
189 void *args);
190 int __roc_api roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix,
191 bool poll);
192 /* NIX Inline/Outbound API */
193 enum roc_nix_inl_sa_sync_op {
194 ROC_NIX_INL_SA_OP_FLUSH,
195 ROC_NIX_INL_SA_OP_FLUSH_INVAL,
196 ROC_NIX_INL_SA_OP_RELOAD,
197 };
198
199 int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
200 enum roc_nix_inl_sa_sync_op op);
201 int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr,
202 void *sa_cptr, bool inb, uint16_t sa_len);
203
204 #endif /* _ROC_NIX_INL_H_ */
205