1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 #ifndef _ROC_CONSTANTS_H_ 5 #define _ROC_CONSTANTS_H_ 6 7 /* ROC Cache */ 8 #define ROC_CACHE_LINE_SZ 128 9 #define ROC_ALIGN ROC_CACHE_LINE_SZ 10 11 /* LMTST constants */ 12 /* [CN10K, .) */ 13 #define ROC_LMT_LINE_SZ 128 14 #define ROC_NUM_LMT_LINES 2048 15 #define ROC_LMT_LINES_PER_CORE_LOG2 5 16 #define ROC_LMT_LINE_SIZE_LOG2 7 17 #define ROC_LMT_BASE_PER_CORE_LOG2 \ 18 (ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2) 19 #define ROC_LMT_MAX_THREADS 42UL 20 #define ROC_LMT_CPT_LINES_PER_CORE_LOG2 4 21 #define ROC_LMT_CPT_BASE_ID_OFF \ 22 (ROC_LMT_MAX_THREADS << ROC_LMT_LINES_PER_CORE_LOG2) 23 24 /* PCI IDs */ 25 #define PCI_VENDOR_ID_CAVIUM 0x177D 26 #define PCI_DEVID_CNXK_RVU_PF 0xA063 27 #define PCI_DEVID_CNXK_RVU_VF 0xA064 28 #define PCI_DEVID_CNXK_RVU_AF 0xA065 29 #define PCI_DEVID_CNXK_RVU_SSO_TIM_PF 0xA0F9 30 #define PCI_DEVID_CNXK_RVU_SSO_TIM_VF 0xA0FA 31 #define PCI_DEVID_CNXK_RVU_NPA_PF 0xA0FB 32 #define PCI_DEVID_CNXK_RVU_NPA_VF 0xA0FC 33 #define PCI_DEVID_CNXK_RVU_AF_VF 0xA0f8 34 #define PCI_DEVID_CNXK_DPI_VF 0xA081 35 #define PCI_DEVID_CNXK_EP_VF 0xB203 36 #define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6 37 #define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7 38 #define PCI_DEVID_CNXK_BPHY 0xA089 39 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0 40 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1 41 #define PCI_DEVID_CNXK_RVU_REE_PF 0xA0f4 42 #define PCI_DEVID_CNXK_RVU_REE_VF 0xA0f5 43 44 #define PCI_DEVID_CN9K_CGX 0xA059 45 #define PCI_DEVID_CN10K_RPM 0xA060 46 47 #define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD 48 #define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE 49 #define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2 50 #define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3 51 52 #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900 53 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900 54 #define PCI_SUBSYSTEM_DEVID_CNF10KA 0xBA00 55 56 #define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000 57 #define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400 58 #define PCI_SUBSYSTEM_DEVID_CN9KC 0x0200 59 #define PCI_SUBSYSTEM_DEVID_CN9KD 0xB200 60 #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100 61 62 #endif /* _ROC_CONSTANTS_H_ */ 63